Patents Issued in February 20, 2020
  • Publication number: 20200058590
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha
  • Publication number: 20200058591
    Abstract: A method for manufacturing a semiconductor device includes forming a plurality of trenches in a dielectric layer, wherein the plurality of trenches each comprise a rounded surface, depositing a liner layer on the rounded surface of each of plurality of trenches, and depositing a conductive layer on the liner layer in each of the plurality of trenches, wherein the conductive layer and the liner layer form a plurality of interconnects, and each of the plurality of interconnects has a cylindrical shape.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Benjamin D. Briggs, Michael Rizzolo, Christopher J. Penny, Huai Huang, Lawrence A. Clevenger, Hosadurga Shobha
  • Publication number: 20200058592
    Abstract: Various embodiments of an integrated circuit package and a method of forming such package are disclosed. The package includes a substrate having a core layer disposed between a first dielectric layer and a second dielectric layer, a die disposed in a cavity of the core layer, and an encapsulant disposed in the cavity between the die and a sidewall of the cavity. The package further includes a first patterned conductive layer disposed within the first dielectric layer, a device disposed on an outer surface of the first dielectric layer such that the first patterned conductive layer is between the device and the core layer, a second patterned conductive layer disposed within the second dielectric layer, and a conductive pad disposed on an outer surface of the second dielectric layer such that the second patterned conductive layer is between the conductive pad and the core layer.
    Type: Application
    Filed: August 9, 2019
    Publication date: February 20, 2020
    Inventors: Chunho KIM, Mark R. BOONE, Randolph E. CRUTCHFIELD
  • Publication number: 20200058593
    Abstract: Various methods and structures for fabricating BEOL metallization layer including at least one bulk cobalt contact, the at least one bulk cobalt contact including a replacement non-cobalt metal cap integral to the at least one bulk cobalt contact. The method includes performing selective deposition, by a chemical exchange reaction of metal between a non-cobalt metal and Cobalt in the at least one bulk cobalt contact, of the replacement non-cobalt metal cap integrally formed in a top surface region of the bulk cobalt contact.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Inventors: James J. KELLY, Cornelius Brown PEETHALA
  • Publication number: 20200058594
    Abstract: A semiconductor device and method for forming the semiconductor device are described. The method includes recessing a device pad to below a top surface of an interconnect layer and depositing a cap in the recess over the device pad. A topography assist layer is formed over each of at least one alignment mark using a selective deposition process that deposits material on conductive material of the at least one alignment mark selective to the metal nitride of the device pad such that a top surface of the topography assist feature is higher than a top surface of the cap. Device layers are deposited conformally over the interconnect layer such that the topography assist layer causes a topographical feature in a top surface of the deposited device layers, the topographical feature being vertically aligned with the topography assist layer. The device pad is aligned according to the topographical feature.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Michael Rizzolo, Chih-Chao Yang, Lawrence A. Clevenger, Benjamin D. Briggs
  • Publication number: 20200058595
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first overlay grating over a substrate. The method includes forming a layer over the first overlay grating. The method includes forming a second overlay grating over the layer. The second overlay grating has a third strip portion and a fourth strip portion, the third strip portion and the fourth strip portion are elongated in the first elongated axis and are spaced apart from each other, there is a second distance between a third sidewall of the third strip portion and a fourth sidewall of the fourth strip portion, the third sidewall faces away from the fourth strip portion, the fourth sidewall faces the third strip portion, the first distance is substantially equal to the second distance, and the first trench extends across the third strip portion and the fourth strip portion.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Long-Yi CHEN, Jia-Hong CHU, Chi-Wen LAI, Chia-Ching LIANG, Kai-Hsiung CHEN, Yu-Ching WANG, Po-Chung CHENG, Hsin-Chin LIN, Meng-Wei CHEN, Kuei-Shun CHEN
  • Publication number: 20200058596
    Abstract: A back alignment mark on a surface of a semiconductor substrate is detected and a resist mask patterned into a circuit pattern corresponding to a surface element structure is formed on a back of the semiconductor substrate. Detection of the back alignment mark is performed by using a detector opposing the back of the semiconductor substrate and measuring contrast based on the intensity of reflected infrared light irradiated from the back of the semiconductor substrate. The back alignment mark is configured by a step formed by the surface of the semiconductor substrate and bottoms of trenches formed from the surface of the semiconductor substrate. A polysilicon film is embedded in the trenches. The back alignment mark has, for example, a cross-shaped planar layout in which three or more trenches are disposed in a direction parallel to the surface of the semiconductor substrate.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Naoko KODAMA
  • Publication number: 20200058597
    Abstract: A substrate includes at least first, second, and third metal layers and adjacent substrate portions having rotated arrangements of signal traces provided by the metal layers. Each metal layer includes first and second spaced portions. The first portion of the first metal layer includes a first trace configured to carry a first signal and the second portion of the first metal layer includes a second trace configured to carry a second signal. The first portion of the second metal layer includes third and fourth spaced traces configured to carry the second signal and the second portion includes fifth and sixth spaced traces configured to carry the first signal. The first portion of the third metal layer includes a seventh trace configured to carry the first signal and the second portion includes an eighth trace configured to carry the second signal.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Allegro MicroSystems, LLC
    Inventors: Cristian David Almiron, Juan Jose Baudino
  • Publication number: 20200058598
    Abstract: A semiconductor device includes a single lead frame, a semiconductor element, and a mold material. The semiconductor element is joined onto one main surface of the lead frame. The lead frame includes a die-attach portion, a signal terminal portion, and a ground terminal portion. The die-attach portion, the signal terminal portion, and the ground terminal portion are disposed directly below the mold material so as to be arranged in a direction along one main surface. A groove portion is provided by partially removing the lead frame so as to allow the groove portion to pass therethrough, the groove portion being provided between the die-attach portion and the ground terminal portion adjacent to each other in the lead frame and between the signal terminal portion and the ground terminal portion adjacent to each other in the lead frame.
    Type: Application
    Filed: April 19, 2018
    Publication date: February 20, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Kiyoshi ISHIDA, Hidenori ISHIBASHI, Makoto KIMURA
  • Publication number: 20200058599
    Abstract: A circuit module (101) includes a circuit board (1) having a main surface (1u), an electronic component (3) mounted on the main surface (1u), and a sealing resin (4) covering at least part of the electronic component (3) on the main surface (1u). A recess (7) is formed on at least part of a side surface (11) of the sealing resin (4). At least the recess (7) is covered with an electrically conductive film (6).
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Takahiro OKADA, Kazushige SATO, Takafumi KANNO, Nobumitsu AMACHI
  • Publication number: 20200058600
    Abstract: An object of the present invention is to provide a semiconductor device capable of reducing external stress transmitted to a semiconductor chip through a lead frame. A semiconductor device includes a base plate, a semiconductor element held on the base plate, a housing disposed on the base plate and having a frame shape enclosing the semiconductor element, a terminal section provided in an outer surface of the housing and connectable to an external device, a lead frame that is long and has one end disposed so as to be connectable to the terminal section provided in the housing and another end connected onto the semiconductor element via a bonding material, a sealing material disposed in the housing to seal the lead frame and the semiconductor element, and a fixing section that fixes, in the housing, part of the lead frame to the base plate or the housing.
    Type: Application
    Filed: November 29, 2016
    Publication date: February 20, 2020
    Applicant: Mitsubishi Electric Corporation
    Inventors: Takahiko MURAKAMI, Arata IIZUKA, Ryoji MURAI, Katsuji ANDO
  • Publication number: 20200058601
    Abstract: A system and method for preventing cracks in a passivation layer is provided. In an embodiment a contact pad has a first diameter and an opening through the passivation layer has a second diameter, wherein the first diameter is greater than the second diameter by a first distance of about 10 ?m. In another embodiment, an underbump metallization is formed through the opening, and the underbump metallization has a third diameter that is greater than the first diameter by a second distance of about 5 ?m. In yet another embodiment, a sum of the first distance and the second distance is greater than about 15 ?m. In another embodiment the underbump metallization has a first dimension that is less than a dimension of the contact pad and a second dimension that is greater than a dimension of the contact pad.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Yu-Feng Chen, Yen-Liang Lin, Tin-Hao Kuo, Sheng-Yu Wu, Chen-Shien Chen
  • Publication number: 20200058602
    Abstract: An electronic device includes: a base layer; a first layer located at least partially over the base layer; a second layer located at least partially over the first layer; a first metal layer located at least partially over the second layer, wherein one or more signal outputs of the electronic device are formed in the first metal layer; and a second metal layer located at least partially over the first metal layer, wherein one or more gate connection is formed in the second metal layer, wherein removing a portion of the second metal layer disrupts at least one gate connection and deactivates the device.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 20, 2020
    Inventor: William Eli Thacker, III
  • Publication number: 20200058603
    Abstract: In certain aspects, a clamp includes first and second transistors coupled in series between a power bus and a ground. The clamp also includes a resistive voltage divider configured to bias a gate of the first transistor and a gate of the second transistor based on a supply voltage on the power bus. The clamp further includes a capacitive voltage divider configured to turn on the first and second transistors in response to a voltage transient on the power bus exceeding a trigger threshold voltage.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 20, 2020
    Inventors: Jongshick AHN, Iulian MIREA, Chung-Ti HSU
  • Publication number: 20200058604
    Abstract: The present disclosure provides a fan-out antenna packaging structure for a semiconductor chip and its fabricating method. The structure is a stacked-up two sets of metal connecting columns and antenna metal patterns arranged in two sequential layers of packaging materials. In some applications there can be more than two sets of the stacked-up antenna structures, fabricated around the chip at one side of a rewiring layer. The chip is interconnected to external metal bumps on the other side of the rewiring layer.
    Type: Application
    Filed: February 4, 2019
    Publication date: February 20, 2020
    Inventors: Yenheng CHEN, Chengchung LIN, Chengtar WU
  • Publication number: 20200058605
    Abstract: The present disclosure provides a fan-out antenna packaging structure for a semiconductor chip and its fabricating method. The structure is a stacked-up two sets of metal connecting columns and antenna metal patterns arranged in two sequential layers of packaging materials sealing the chip. The two sets of metal interconnecting structures in the two layers of packaging materials may have different thicknesses. In some applications there can be more than two sets of the stacked-up antenna structures, fabricated around the chip at one side of a rewiring layer. The chip is interconnected to external metal bumps on the other side of the rewiring layer.
    Type: Application
    Filed: May 15, 2019
    Publication date: February 20, 2020
    Inventors: Yenheng CHEN, Chengchung LIN, Chengtar WU
  • Publication number: 20200058606
    Abstract: A device includes a redistribution structure, a first semiconductor device, a first antenna, and a first conductive pillar on the redistribution structure that are electrically connected to the redistribution structure, an antenna structure over the first semiconductor device, wherein the antenna structure includes a second antenna that is different from the first antenna, wherein the antenna structure includes an external connection bonded to the first conductive pillar, and a molding material extending between the antenna structure and the redistribution structure, the molding material surrounding the first semiconductor device, the first antenna, the external connection, and the first conductive pillar.
    Type: Application
    Filed: August 2, 2019
    Publication date: February 20, 2020
    Inventors: Po-Hao Tsai, Po-Yao Chuang, Ming-Chih Yew, Shin-Puu Jeng
  • Publication number: 20200058607
    Abstract: A package structure include a ground plate, a semiconductor die, a molding compound, and an antenna element. The semiconductor die is located over the ground plate. The molding compound is located over the semiconductor die. The antenna element is located in the molding compound and overlaps with the ground plate along a stacking direction of the ground plate, the semiconductor die and the molding compound. The antenna element has a first side levelled with a first surface of the molding compound, and the ground plate is located between the semiconductor die and the antenna element.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Albert Wan, Chao-Wen Shih, Shou-Zen Chang, Nan-Chin Chuang
  • Publication number: 20200058608
    Abstract: Some embodiments of the present disclosure are directed to a device. The device includes a substrate comprising a silicon layer disposed over an insulating layer. The substrate includes a transistor device region and a radio-frequency (RF) region. An interconnect structure is disposed over the substrate and includes a plurality of metal layers disposed within a dielectric structure. A handle substrate is disposed over an upper surface of the interconnect structure. A trapping layer separates the interconnect structure and the handle substrate.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Inventors: Kuo-Yu Cheng, Chih-Ping Chao, Kuan-Chi Tsai, Shih-Shiung Chen, Wei-Kung Tsai
  • Publication number: 20200058609
    Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The method includes providing a semiconductor substrate, forming a redistribution line on a top surface of the semiconductor substrate, and forming a passivation layer to cover the redistribution line on the top surface of the semiconductor substrate. The forming a redistribution line includes a first stage of forming a first segment of the redistribution line on the top surface of the semiconductor substrate, and a second stage of forming a second segment of the redistribution line on the first segment of the redistribution line. An average grain size of the second segment of the redistribution line is less than an average grain size of the first segment of the redistribution line.
    Type: Application
    Filed: March 26, 2019
    Publication date: February 20, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jeonggi JIN, Ju-ll CHOI, Teahwa JEONG, Atsushi FUJISAKI
  • Publication number: 20200058610
    Abstract: A semiconductor device includes a semiconductor chip, a bump contract, and encapsulating layer, an insulating layer, and a connection terminal.
    Type: Application
    Filed: October 15, 2019
    Publication date: February 20, 2020
    Applicant: Cypress Semiconductor Corporation
    Inventors: Masanori Onodera, Junichi Kasai
  • Publication number: 20200058611
    Abstract: A semiconductor package is provided, including a package substrate, a package component, and a number of conductive connectors. The package component has a number of conductive features on a first surface of the package component facing the package substrate. The conductive connectors electrically connect the conductive features of the package component to the package substrate. The conductive features include a first conductive feature and a second conductive feature contacting a first conductive connector and a second conductive connector, respectively. The size of the first conductive feature is smaller than the size of the second conductive feature, and the height of the first conductive connector on the first conductive feature is greater than the height of the second conductive connector on the second conductive feature.
    Type: Application
    Filed: January 28, 2019
    Publication date: February 20, 2020
    Inventors: Chih-Hao LIN, Chien-Kuo CHANG, Tzu-Kai LAN, Chung-Chih CHEN, Jr-Lin HSU
  • Publication number: 20200058612
    Abstract: A solder bump structure includes a pillar formed on an electrode pad. The pillar has a concave curve-shaped surface and a geometry defined at least in part by dimensions including a first height greater than a first width. The solder bump structure further includes solder formed on the concave curve-shaped surface of the pillar. The solder has a convex top surface and having dimensions including a second height greater than a second width due to the geometry of the pillar.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Toyohiro Aoki, Takashi Hisada, Eiji I. Nakamura
  • Publication number: 20200058613
    Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 20, 2020
    Inventors: Ming-Che Ho, Yi-Wen Wu, Chien Ling Hwang, Hung-Jui Kuo, Chung-Shi Liu
  • Publication number: 20200058614
    Abstract: A method for forming a chip package structure is provided. The method includes partially removing a first redistribution layer to form an alignment trench in the first redistribution layer. The alignment trench surrounds a bonding portion of the first redistribution layer. The method includes forming a liquid layer over the bonding portion. The method includes disposing a chip structure over the liquid layer, wherein a first width of the bonding portion is substantially equal to a second width of the chip structure. The method includes evaporating the liquid layer. The chip structure is in direct contact with the bonding portion after the liquid layer is evaporated.
    Type: Application
    Filed: April 3, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hang TUNG, Tung-Liang SHAO, Su-Chun YANG, Geng-Ming CHANG, Chen-Hua YU
  • Publication number: 20200058615
    Abstract: A flip chip bonding method includes obtaining a die including a first substrate and an adhesive layer on the first substrate; bonding the die to a second substrate different from the first substrate; and curing the adhesive layer. The curing the adhesive layer includes heating the second substrate to melt the adhesive layer, and providing the adhesive layer and the second substrate with air having pressure greater than atmospheric pressure.
    Type: Application
    Filed: August 6, 2019
    Publication date: February 20, 2020
    Inventors: HWAIL JIN, YONGWON CHOI, MYUNG-SUNG KANG, YEONGSEOK KIM, WONKEUN KIM
  • Publication number: 20200058616
    Abstract: An embodiment package includes a first integrated circuit die, an encapsulent around the first integrated circuit die, and a conductive line electrically connecting a first conductive via to a second conductive via. The conductive line includes a first segment over the first integrated circuit die and having a first lengthwise dimension extending in a first direction and a second segment having a second lengthwise dimension extending in a second direction different than the first direction. The second segment extends over a boundary between the first integrated circuit die and the encapsulant.
    Type: Application
    Filed: October 23, 2019
    Publication date: February 20, 2020
    Inventors: Cheng-Hsien Hsieh, Li-Han Hsu, Wei-Cheng Wu, Hsien-Wei Chen, Der-Chyang Yeh, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20200058617
    Abstract: A three-dimensional (3D) integrated circuit (IC) is provided. In some embodiments, a second IC die is bonded to a first IC die by a first bonding structure. The first bonding structure contacts a first interconnect structure of the first IC die and a second interconnection structure of the second IC die, and has a first portion and a second portion hybrid bonded together. A third IC die is bonded to the second IC die by a third bonding structure. The third bonding structure comprises a second TSV (through substrate via) disposed through the second substrate of the second IC die and includes varies bonding structures according to varies embodiments of the invention.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Inventors: Kuo-Ming Wu, Ching-Chun Wang, Dun-Nian Yaung, Hsing-Chih Lin, Jen-Cheng Liu, Min-Feng Kao, Yung-Lung Lin, Shih Han Huang, I-Nan Chen
  • Publication number: 20200058618
    Abstract: According to an aspect, a stack packaging structure includes a substrate, a semiconductor device coupled to a surface of the substrate, an image sensor device coupled to the semiconductor device such that the semiconductor device is disposed between the surface of the substrate and the image sensor device, at least one bond wire connected to the image sensor device and the surface of the substrate, a inner molding disposed between the surface of the substrate and the image sensor device, where the semiconductor device is encapsulated within the inner molding, and an outer molding disposed on the surface of the substrate, where the at least one bond wire is encapsulated within the outer molding.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Yu-Te HSIEH
  • Publication number: 20200058619
    Abstract: A packaged module for use in a wireless communication device has a substrate supporting a crystal and a first die that includes at least a microprocessor and one or more of radio frequency transmitter circuitry and radio frequency receiver circuitry. The first die is disposed between the crystal and the substrate. An overmold encloses the first die and the crystal. The substrate also supports a second die that includes at least a power amplifier for amplifying a radio frequency input signal, where the second die is disposed on an opposite side of the substrate from the first die and the crystal.
    Type: Application
    Filed: August 29, 2019
    Publication date: February 20, 2020
    Inventors: Darren Roger Frenette, George Khoury, Leslie Paul Wallis
  • Publication number: 20200058620
    Abstract: A chip package is provided. The chip package includes a semiconductor die and a protective layer surrounding the semiconductor die. The chip package also includes an interface between the semiconductor die and the protective layer. The chip package further includes a conductive line over the protective layer and the semiconductor die. The conductive line has a first portion and a second portion in direct contact with the first portion, and the second section at least partially covers the interface. In a top view of the conductive layer, line widths of the first portion and the second portion are different from each other.
    Type: Application
    Filed: October 24, 2019
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie CHEN, Hsien-Wei CHEN
  • Publication number: 20200058621
    Abstract: Some embodiments include apparatus, systems, and methods having a base, a first die, a second arranged in a stacked with the first die and the base, and a structure located in the stack and outside at least one of the first and second dice and configured to transfer signals between the base and at least one of the first and second dice.
    Type: Application
    Filed: October 28, 2019
    Publication date: February 20, 2020
    Inventors: Brent Keeth, Mark Hiatt, Terry R. Lee, Mark Tuttle, Rahul Advani, John F. Schreck
  • Publication number: 20200058622
    Abstract: A semiconductor package includes a first chip package including a plurality of first semiconductor dies and a first insulating encapsulant, a second semiconductor die, a third semiconductor die, and a second insulating encapsulant. The plurality of first semiconductor dies are electrically connected to each other, and the first insulating encapsulant encapsulates the plurality of first semiconductor dies. The second semiconductor die and the third semiconductor die are electrically communicated to each other by connecting to the first chip package, wherein the first chip package is stacked on the second semiconductor die and the third semiconductor die. The second insulating encapsulant encapsulates the first chip package, the second semiconductor die, and the third semiconductor die.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jie Chen, Hsien-Wei Chen
  • Publication number: 20200058623
    Abstract: A light emitting diode (LED) module and display for hiding physical gaps between modules is provided. An LED module comprises: a board including at least one edge; and an array of LEDs at the board, the array comprising: first LEDs and second LEDs, smaller than the first LEDs, the second LEDs located along the at least one edge of the board, the first and second LEDs all being at a common pitch distance, adjacent sides of adjacent first LEDs separated by a first distance, and the second LEDs being at a second distance from the at least one edge of the board, the second distance smaller than the first distance. The modules may be incorporated into an LED display.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 20, 2020
    Inventors: Daniel Robert ADEMA, Bryan HEMPHILL
  • Publication number: 20200058624
    Abstract: A micro light-emitting diode display device is disclosed in the present disclosure. The micro light-emitting diode display device includes a substrate and a plurality of display units. The substrate has a supporting surface. The plurality of display units is disposed on the substrate, with each of the plurality of display units including a plurality of micro light-emitting diodes, wherein a gap existing between any two of the plurality of display units next to each other has a varying width.
    Type: Application
    Filed: December 17, 2018
    Publication date: February 20, 2020
    Applicant: PLAYNITRIDE INC.
    Inventors: Po-Jen SU, Gwo-Jiun SHEU, Chun-Ming TSENG
  • Publication number: 20200058625
    Abstract: A transparent display panel with a light-transmitting substrate, a plurality of top-emitting micro light emitting diodes, a plurality of bottom-emitting micro light emitting diodes, and a light shielding layer. The light transmissive substrate has a surface. These top-emitting micro light emitting diodes and these bottom-emitting micro light emitting diodes are disposed on the surface of the light transmissive substrate. The bottom-emitting micro light emitting diodes has an epitaxial structure and a light shielding member, the epitaxial structure has a pair of upper and lower surfaces on the opposite sides, the lower surface faces toward the light transmissive substrate, and the light shielding member is disposed on the upper surface to shield the light emitted by the bottom-emitting micro light emitting diodes towards the upper surface.
    Type: Application
    Filed: August 13, 2019
    Publication date: February 20, 2020
    Applicant: PLAYNITRIDE INC.
    Inventors: Pei-Hsin CHEN, Yi-Chun SHIH, Yi-Ching CHEN, Ying-Tsang LIU, Yu-Chu LI
  • Publication number: 20200058626
    Abstract: A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Hsuan Tai, Hao-Yi Tsai, Yu-Chih Huang, Chia-Hung Liu, Ting-Ting Kuo, Ban-Li Wu, Ying-Cheng Tseng, Chi-Hui Lai
  • Publication number: 20200058627
    Abstract: A package includes a first redistribution structure, a bridge structure, an adhesive layer, a plurality of conductive pillars, an encapsulant, a first die, and a second die. The bridge structure is disposed on the first redistribution structure. The adhesive layer is disposed between the bridge structure and the first redistribution structure. The conductive pillars surround the bridge structure. A height of the conductive pillars is substantially equal to a sum of a height of the adhesive layer and a height of the bridge structure. The encapsulant encapsulates the bridge structure, the adhesive layer, and the conductive pillars. The first die and the second die are disposed over the bridge structure. The first die is electrically connected to the second die through the bridge structure. The first die and the second die are electrically connected to the first redistribution structure through the conductive pillars.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
  • Publication number: 20200058628
    Abstract: In a method for wafer-to-wafer bonding, an integrated circuit (IC) wafer and a phase-change material (PCM) switch wafer are provided. The IC includes at least one active device, and has an IC substrate side and a metallization side. The PCM switch wafer has a heat spreading side and a radio frequency (RF) terminal side. A heat spreader is formed in the PCM switch wafer. In one approach, the heat spreading side of the PCM switch wafer is bonded to the metallization side of the IC wafer, then a heating element is formed between the heat spreader and a PCM in the PCM switch wafer. In another approach, a heating element is formed between the heat spreader and a PCM in the PCM switch wafer, then the RF terminal side of the PCM switch wafer is bonded to the metallization side of the IC wafer.
    Type: Application
    Filed: May 15, 2019
    Publication date: February 20, 2020
    Inventors: Gregory P. Slovin, David J. Howard
  • Publication number: 20200058629
    Abstract: A display device is disclosed. In an embodiment a display device having a plurality of pixels separately operable from each other includes a semiconductor layer sequence including a first semiconductor layer, an active layer and a second semiconductor layer, a first contact structure contacting the first semiconductor layer and a second contact structure contacting the second semiconductor layer and at least one separating region extending through the first contact structure, the first semiconductor layer and the active layer into the second semiconductor layer, wherein the semiconductor layer sequence and the first contact structure have at least one first recess laterally adjacent with respect to a respective pixel, the first recess extending through the first contact structure, the first semiconductor layer and the active layer into the second semiconductor layer, and wherein the second contact structure includes second contacts extending through the at least one first recess.
    Type: Application
    Filed: November 23, 2017
    Publication date: February 20, 2020
    Inventors: Alexander F. Pfeuffer, Dominik Scholz
  • Publication number: 20200058630
    Abstract: A method of manufacturing an optoelectronic component includes: A) providing a sub-strate, B) providing a metallic liquid arranged in a structured manner and in direct mechanical contact on the substrate and including at least one first metal, C) providing semiconductor chips each having a metallic termination layer on their rear side, the metallic termination layer including at least one second metal different from the first metal, and D) self-organized arranging the semiconductor chips on the metallic liquid so that the first metal and the second metal form at least one intermetallic compound having a higher re-melting temperature than the melting temperature of the metallic liquid, wherein the intermetallic compound is a connecting layer between the substrate and the semiconductor chips.
    Type: Application
    Filed: March 6, 2018
    Publication date: February 20, 2020
    Inventors: Norwin von Malm, Andreas PIƶssl
  • Publication number: 20200058631
    Abstract: A micro LED display panel defines a display area and a border area surrounding the display area. The micro LED display panel includes a TFT array substrate, a plurality of micro LEDs on the TFT array substrate, a common electrode on the TFT array substrate, the common electrode covering and electrically coupling to all of the micro LEDs; a metal layer on a side of the common electrode away from the TFT array substrate and electrically coupling to the common electrode, and a black photoresist layer on a side of the metal layer away from the TFT array substrate. The black photoresist layer defines through holes. Each through hole extends through both the black photoresist layer and the metal layer and aligns with one micro LED. The metal layer and the black photoresist layer cover the display area and the border area.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 20, 2020
    Inventors: PO-FU CHEN, I-WEI WU, I-MIN LU, WEI-CHIH CHANG
  • Publication number: 20200058632
    Abstract: A semiconductor device includes a bottom package, a top package, and a heat dissipating structure. The bottom package includes a redistribution structure, and a die disposed on a first surface of the redistribution structure and electrically connected to the redistribution structure. The top package is disposed on a second surface of the redistribution structure opposite to the first surface. The heat dissipating structure is disposed over the bottom package, and includes a thermal relaxation block. The thermal relaxation block contacts the redistribution structure and is disposed beside the top package.
    Type: Application
    Filed: August 15, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wei Chen, Chih-Hua Chen, Hsin-Yu Pan, Hao-Yi Tsai, Lipu Kris Chuang, Tin-Hao Kuo
  • Publication number: 20200058633
    Abstract: The present disclosure provides a semiconductor package including a bottom package having a substrate, a radio-frequency (RF) die and a system-on-a-chip (SoC) die arranged on the substrate in a side-by-side manner, a molding compound covering the RF die and the SoC die, and an interposer over the molding compound. Connection elements and a column of signal interference shielding elements are disposed on the substrate. The connection elements surround the SoC die. The column of signal interference shielding elements is interposed between the RF die and the SoC die. A top package is mounted on the interposer.
    Type: Application
    Filed: August 7, 2019
    Publication date: February 20, 2020
    Inventors: Sheng-Mou Lin, Wen-Chou Wu, Hsing-Chih Liu
  • Publication number: 20200058634
    Abstract: A memory device is disclosed that includes memory cell, e strap cell, conductive segment, and logic cell. The strap cell is arranged abutting the memory cell. The strap cell includes an active region, a first gate, and a second gate. The first gate is arranged across the active region. The second gate is arranged across the active region and disposed at the end of active region. The conductive segment is disposed over the first gate and the second gate. The strap cell is disposed between the memory cell and the logic cell, and the logic cell includes a third gate. The conductive segment is spaced apart from the third gate, and the length of the conductive segment is smaller than five times of a gate pitch between the first gate and the second gate.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jacklyn CHANG, Derek C. TAO, Kuo-Yuan HSU
  • Publication number: 20200058635
    Abstract: A semiconductor die can include: first, second, third, and fourth transistors disposed at intervals, where each two of the first, second, third, and fourth transistors are separated by a separation region to form four separation regions; an isolation structure having a first doping structure of a first doping type, and a second doping structure of a second doping type, to absorb hole carriers and electron carriers flowing between the first, second, third, and fourth transistors; where the first doping structure is located in the separation region to isolate adjacent transistors in the first, second, third, and fourth transistors; and where at least a portion of the second doping structure is surrounded by the first doping structure, and the second doping structure is separated from the first doping structure.
    Type: Application
    Filed: August 12, 2019
    Publication date: February 20, 2020
    Inventors: Jianping Qiu, Yicheng Du, Meng Wang
  • Publication number: 20200058636
    Abstract: A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.
    Type: Application
    Filed: August 20, 2018
    Publication date: February 20, 2020
    Inventors: KUN-HSIEN LIN, ZI-PING CHEN, CHE-HAO CHUANG
  • Publication number: 20200058637
    Abstract: The present disclosure provides a silicon-controlled rectifier structure and a manufacturing method therefor. The silicon-controlled rectifier structure comprises a substrate; and an N-Well and a P-Well in the substrate, and an N-type heavily-doped region and a P-type heavily-doped region which are connected to an anode are provided in the N-Well, and a guard ring connected to the anode is further provided in the N-Well between the N-type heavily-doped region and the P-type heavily-doped region, the guard ring being spaced from the N-type heavily-doped region by a shallow trench isolation, and an active area having a predetermined width exists between the guard ring and the P-type heavily-doped region; and an N-type heavily-doped region and a P-type heavily-doped region which are connected to a cathode are provided in the P-Well.
    Type: Application
    Filed: November 16, 2018
    Publication date: February 20, 2020
    Inventor: Tianzhi ZHU
  • Publication number: 20200058638
    Abstract: There are disclosed herein various implementations of a semiconductor device including a group III-V layer situated over a substrate, and a phase-change material (PCM) radio frequency (RF) switch situated over the group III-V layer. The PCM RF switch couples a group III-V transistor situated over the group III-V layer to one of an integrated passive element or another group III-V transistor situated over the group III-V layer. The PCM RF switch includes a heating element transverse to the PCM, the heating element underlying an active segment of the PCM. The PCM RF switch is configured to be electrically conductive when the active segment of the PCM is in a crystalline state, and to be electrically insulative when the active segment of the PCM is in an amorphous state.
    Type: Application
    Filed: October 29, 2018
    Publication date: February 20, 2020
    Inventors: Nabil El-Hinnawy, David J. Howard, Gregory P. Slovin, Jefferson E. Rose
  • Publication number: 20200058639
    Abstract: A method for fabricating a semiconductor device includes, for a substrate having a first region protected by a cap layer, forming a first device on a second region of the substrate. The substrate includes an insulator layer disposed between a first semiconductor layer and a second semiconductor layer each including a first semiconductor material. The method further includes forming a second device on the first region, including forming one or more transistors each having a channel formed from a second semiconductor material different from the first semiconductor material.
    Type: Application
    Filed: October 25, 2019
    Publication date: February 20, 2020
    Inventors: Xin Zhang, Ko-Tao Lee, Todd E. Takken, Paul W. Coteus, Andrew Ferencz