Abstract: An image sensor includes a first column line and a second column line configured to extend in a first direction, a plurality of pixel groups configured to connect to the first column line or the second column line and to comprise a plurality of pixels in each of the plurality of pixel groups, a bias circuit configured to comprise a first current circuit and a second current circuit configured to output different bias currents in a first operational mode, and a switching circuit configured to connect the first column line to the first current circuit and connect the second column line to the second current circuit during a first time period, and to connect the first column line to the second current circuit and connect the second column line to the first current circuit during a second time period subsequent to the first time period in the first operational mode.

Abstract: A photoelectric detection substrate, a method for fabricating the same, and a photoelectric detection device are disclosed. The photoelectric detection substrate includes a thin film transistor and a photodiode coplanar with the thin film transistor. The thin film transistor has a vertical channel structure and includes a gate electrode, an active layer, a first electrode and a second electrode. The photodiode includes a first doped layer, an absorption layer and a second doped layer disposed in this order. The active layer and the absorption layer are disposed in a same layer and formed by a same patterning process. By forming a photodiode coplanar with a thin film transistor of a vertical channel structure, the overall thickness of the photoelectric detection substrate is effectively reduced, deformation of the substrate caused by stress is reduced, and damage caused by deformation of the substrate is avoided, and thereby the yield is improved.

Abstract: Disclosed herein is a solid state imaging device including a support substrate; an imaging semiconductor chip having a pixel array disposed on the support substrate; and an image processing semiconductor chip disposed on the support substrate, wherein the imaging semiconductor chip and the image processing semiconductor chip are connected by through-vias, and interconnects formed on the support substrate.

Abstract: An endoscope includes an image pickup module, and the image pickup module includes: an image pickup device an external electrode being disposed on a back surface of the image pickup device; a wiring element provided with a through-hole passing through a first main surface and a second main surface, a first electrode on the first main surface being bonded with the external electrode; a signal cable bonded with a second electrode on the second main surface of the wiring element; and a first resin that seals a first bump bonding the first electrode and the external electrode and a second bump bonding the second electrode and the signal cable, and fills the through-hole.

Abstract: An imaging device, includes: an imaging unit in which are disposed a plurality of pixels, each including a filter that is capable of changing a wavelength of light passing therethrough to a first wavelength and to a second wavelength and a light reception unit that receives light that has passed through the filter, and that captures an image via an optical system; an analysis unit that analyzes the image captured by the imaging unit; and a control unit that controls the wavelength of the light to be transmitted, by the filter based upon a result of analysis by the analysis unit.

Abstract: According to an aspect, a multi-chip packaging structure includes a first substrate having a first surface and a second surface, where the first substrate has a conductive layer portion. The multi-chip packaging structure includes an image sensor device coupled to the first surface of the first substrate, a first device coupled to the second surface of the first substrate, and a second substrate disposed apart from the first substrate, where the second substrate has a conductive layer portion. The conductive layer portion of the first substrate is communicatively connected to the conductive layer portion of the second substrate. The first device is disposed between the first substrate and the second substrate. The multi-chip packaging structure includes a second device coupled to the second substrate, and a third device coupled to the first substrate or the second substrate.

Abstract: A sensor device includes a first wafer structure and a second wafer structure bonded to the first wafer structure. The first wafer structure includes a first substrate, an integrated circuit layer integrated with the first substrate, and a three-dimensional (3D) NAND memory cell array integrated with the integrate circuit layer. The integrated circuit layer and the 3D NAND memory cell array are located at the same side of the first substrate. The second wafer structure includes a second substrate and a sensing module of a sensor integrated with the second substrate. A manufacturing method of the sensor device includes bonding the second wafer structure to the first wafer structure. A side of the first wafer structure where the 3D NAND memory cell array is located is bonded to a side of the second wafer structure where the sensing module is located.

Abstract: The invention relates to short-wave infrared (SWIR) detector arrays, and methods for forming such arrays, comprising a light conversion layer (10) having a germanium-tin alloy composition. The shortwave infrared (SWIR) detector array comprises an absorber wafer (II) and a readout wafer (I). The absorber wafer (II) comprises a SWIR conversion layer (10) which has a Gei-xSnxalloy composition. The SWIR conversion layer (10) may have an internal structure comprising an array of rods (12) extending between a patterned support layer (40) and a doped silicon layer (10c). The detector comprises also a readout wafer (I) including an array of charge collecting areas and a readout electric circuit. The readout wafer (I) and the absorber wafer (II) are bonded by a low temperature bonding technique. The invention also relates to methods of fabrication of the SWIR detector array and to SWIR detector array applications such as a multi/hyperspectral LIDAR imaging systems.

Abstract: A time-of-flight (TOF) sensor includes a light source, a plurality of avalanche photodiodes, and a plurality of pulse generators. Control circuitry is coupled to the light source, the plurality of avalanche photodiodes, and the plurality of pulse generators, and the control circuitry includes logic that when executed by the control circuitry causes the time-of-flight sensor to perform operations. The operations include emitting the light from the light source, and receiving the light reflected from an object with the plurality of avalanche photodiodes. A plurality of pulses is output from the individual pulse generators corresponding to the individual avalanche photodiodes that received the light, and a timing signal is output when the plurality of pulses overlap temporally. A time is calculated when a first avalanche photodiode in the plurality of avalanche photodiodes received the light.

Abstract: An X-ray detecting panel and a method of operating the same, and an x-ray detecting device are provided. The X-ray detecting panel includes an array substrate which includes a plurality of gate lines and a plurality of signal lines intersecting with each other to divide the array substrate into a plurality of photosensitive cells, each of which comprises a thin film transistor, and the plurality of photosensitive cells comprises one or more first photosensitive cells and one or more second photosensitive cells, the thin film transistor of the first photosensitive cell is disposed at a first side of the first photosensitive cell, the thin film transistor of the second photosensitive cell is disposed at a second side of the second photosensitive cell, and the first side is opposite to the second side.

Abstract: A photoelectric conversion device includes a photoelectric converter accumulating signal charge generated by photoelectric conversion in the first semiconductor region of a first conductivity type, a charge-to-voltage converter generating a voltage signal in accordance with amount of the signal charge, a transistor of a second conductivity type provided in a third semiconductor region of the first conductivity type and including a gate connected to the first semiconductor region, and a voltage supply circuit supplying voltage to the source and drain of the transistor. The voltage supply circuit supplies voltage that causes gate capacitance of the transistor to be a first capacitance value when signal charge accumulated in the first semiconductor region correspond to first amount and cause the gate capacitance to be a second capacitance value when signal charge accumulated in the first semiconductor region correspond to second amount.

Abstract: A light emitting device, includes: a substrate; a light emitting element on the substrate, the light emitting element having a first end portion and a second end portion arranged in a longitudinal direction; one or more partition walls disposed on the substrate, the one or more partition walls being spaced apart from the light emitting element; a first reflection electrode adjacent the first end portion of the light emitting element; a second reflection electrode adjacent the second end portion of the light emitting element; a first contact electrode connected to the first reflection electrode and the first end portion of the light emitting element; an insulating layer on the first contact electrode, the insulating layer having an opening exposing the second end portion of the light emitting element and the second reflection electrode to the outside; and a second contact electrode on the insulating layer.

Abstract: A stacked quantum computing device including: a first chip including a superconducting qubit, where the superconducting qubit includes a superconducting quantum interference device (SQUID) region, a control region, and a readout region, and a second chip bonded to the first chip, where the second chip includes a first control element overlapping with the SQUID region, a second control element displaced laterally from the control region and without overlapping the control region, and a readout device overlapping the readout region.

Abstract: In fabricating a semiconductor device, a shared material is formed in a resonator region of the semiconductor device and in a phase-change material (PCM) switch region of the semiconductor device. A portion of the shared material is removed to concurrently form a heat spreader comprising the shared material in the PCM switch region and a piezoelectric segment comprising the shared material in the resonator region. The piezoelectric segment in the resonator region and the heat spreader in the PCM switch region are situated at substantially the same level in the semiconductor device. The PCM switch region includes a heating element between the heat spreader and a PCM. The resonator region includes the piezoelectric segment between two electrodes.

Abstract: A transition metal oxide based selector, a method for preparing the same and resistive random access memory are provided. The method comprises: S1, forming a tungsten plug on a transistor; S2, using the tungsten plug to function as a lower electrode, and preparing a transition metal layer on the tungsten plug; S3, oxidizing the transition metal layer to convert the transition metal layer into a transition metal oxide layer; and S4, depositing an upper electrode on the transition metal oxide, patterning the upper electrode and the transition metal oxide. The selector of the present disclosure may provide a high current density and has a good uniformity. The formed 1S1R structure may effectively eliminate crosstalk phenomenon in a resistive random access memory array, and effectively increase the storage density without increasing the storage unit area, thereby increasing device integration.

Abstract: Substrates, assemblies, and techniques for a transmission gate that includes an n-type back end transistor and a p-type back end transistor in parallel with the n-type back end transistor. The transmission gate can be on a non-silicon substrate and include a second gate, a p-type semiconducting layer over the second gate, an n-type semiconducting layer over the p-type semiconducting layer, a bit line over the n-type semiconducting layer, a first gate over the n-type semiconducting layer, and a source line over the n-type semiconducting layer. The transmission gate may be coupled to a memory element.

Abstract: A radio frequency (RF) switching circuit includes stacked phase-change material (PCM) RF switches. The stacked PCM RF switches can include a high shunt capacitance PCM RF switch having its heating element contacts near its PCM contacts, and a low shunt capacitance PCM RF switch having its heating element contacts far from its PCM contacts. An RF voltage is substantially uniformly distributed between the high shunt capacitance PCM RF switch and the low shunt capacitance PCM RF switch. The stacked PCM RF switches can also include a wide heating element PCM RF switch having a large PCM active segment, and a narrow heating element PCM RF switch having a small PCM active segment. The wide heating element PCM RF switch will have a higher breakdown voltage than the narrow heating element PCM RF switch.

Abstract: An image sensor and a method for fabricating the same are provided. The image sensor includes a substrate including a first surface opposite a second surface that is incident to light, a first photoelectric conversion layer in the substrate, a wiring structure including a plurality of wiring layers on the first surface of the substrate, an interlayer insulating film on the second surface of the substrate, a capacitor structure in the interlayer insulating film, and a first wiring on the interlayer insulating film. The capacitor structure includes a first conductive pattern, a dielectric pattern, and a second conductive pattern sequentially stacked on the second surface of the substrate. The second conductive pattern is connected to the first wiring.

Abstract: Various embodiments provide an organic light emitting diode display device that includes a substrate having an emitting area and a non-emitting area; an overcoating layer on the substrate and including a convex portion and a concave portion. The convex portion includes a bottom surface portion, a top surface portion and a side surface portion between the bottom surface portion and the top surface portion. The organic light emitting diode further includes a first electrode on the overcoating layer; a light emitting layer on the first electrode; and a second electrode on the light emitting layer. The side surface portion is a main emission region having a first emission spectrum and the concave portion is an auxiliary emission region having a second emission spectrum different from the first emission spectrum. The main emission region and the auxiliary emission region are an effective emission region.

Abstract: An organic light emitting diode display device includes: an overcoating layer on a substrate having an emitting area and a non-emitting area and including a plurality of convex portions and a plurality of concave portions; a first electrode on the overcoating layer; a light emitting layer on the first electrode and including a first emitting material layer; and a second electrode on the light emitting layer, wherein the light emitting layer includes first, second and third emitting material layers sequentially under the second electrode, and wherein the first emitting material layer emits a first light of a first wavelength, the second emitting material layer emits the first light of the first wavelength, and the third emitting material layer emits a second light of a second wavelength different from the first wavelength.

Abstract: An organic light-emitting display panel and a display device are provided. The organic light-emitting display panel includes a bending axis, a bending region, a first non-bending region, a second non-bending region, and at least one set of touch traces. The bending axis extends in a first direction. The first non-bending region and the second non-bending region are respectively located at two opposite sides of the bending region in a second direction perpendicular to the first direction. The at least one set of touch traces includes a plurality of touch traces. In the bending region, the plurality of touch traces extends from the first non-bending region to the second non-bending region. In the bending region, an angle between each of the plurality of touch traces and the bending axis is not 90°.

Abstract: A display device including: a display panel; a first force sensor disposed under the display panel; and a waterproofing member disposed under the display panel and disposed adjacent to the first force sensor, a part of the first force sensor and a part of the waterproofing member overlap each other in a height direction of the display panel.

Abstract: A display device includes: a display panel; a first force sensor disposed below the display panel; a display circuit board attached to a first side of the display panel; and a first flexible circuit board connecting the first force sensor and the display circuit board, wherein the display circuit board and the first flexible circuit board are bent at least once.

Abstract: A pixel arrangement structure, a display panel, a mask component, and an evaporation apparatus are provided. The pixel arrangement structure includes a plurality of sub-pixels arranged in a row direction and a column direction. The plurality of sub-pixels are divided into a plurality of rows of sub-pixel groups. Each of rows of sub-pixel groups include at least two rows of the sub-pixels, and include a plurality of repeating units arranged in sequence, and each of the repeating units includes at least two sub-pixel groups of different colors. Each of the sub-pixel groups includes at least two sub-pixels of a same color that are located in at least two rows and are adjacently arranged, and sub-pixels adjacent to each other and having different colors, which are located in sub-pixel groups of different colors, constitute one pixel.

Abstract: A light emitting device includes a window and a collimating component over a light emitting pixel. A light reflection performance of the light emitting pixel to an incoming ambient light is configured by the window to be appeared to have at least two regions, wherein one region of the at least two regions has a smaller transmittance to the incoming ambient light than the other, the light emitting pixel includes a plurality of sub-pixels separated with a space, and the space is smaller than a resolution of a human eye.

Abstract: The present disclosure provides a light emitting device. The light emitting device includes a substrate, an array of light emitting units over the substrate, and an array of bumps. Each of the bumps is disposed between two of the light emitting units. Each of the light emitting units includes a first electrode including a bottom surface on the substrate, a top surface opposite to the bottom surface, and a sidewall between the bottom surface and the top surface. Each of the light emitting units includes a first organic layer on the first electrode and a second organic layer on the first organic layer. The first organic layer at least partially covers the sidewall. A method for manufacturing a light emitting device is also provided.

Abstract: The present disclosure relates to an array substrate, a display panel, and a display device. In an embodiment, an array substrate is provided that comprises: a substrate; and a pixel defining layer disposed on the substrate, the pixel defining layer including a plurality of openings and a partition portion for separating the plurality of openings from each other, wherein the partition portion has a first recess.

Abstract: The present disclosure provides an organic light emitting display substrate and a method for manufacturing the same. The organic light emitting display substrate includes a substrate, and a drive transistor and an organic light emitting diode disposed on the substrate. In a direction away from the substrate, the organic light emitting diode successively includes: a first reflective electrode, an organic light emitting layer, and a second reflective electrode. A drain of the drive transistor is electrically coupled to the first reflective electrode. The organic light emitting display substrate further includes a light guide layer. One side surface of the light guide layer is the light incident surface. The light incident surface is disposed opposite to the light outgoing surface of the organic light emitting diode so that the light emitted from the light outgoing surface enters the light guide layer.

Abstract: The present disclosure provides a display substrate, which includes a base substrate and a light emitting element layer, which is on a side of the base substrate and includes a pixel defining layer and a plurality of light emitting elements. The pixel defining layer includes a plurality of pixel openings and a plurality of light transmission holes, and the plurality of light emitting elements are in the plurality of pixel openings, respectively. Each of the plurality of light transmission holes penetrates through the pixel defining layer in a thickness direction of the pixel defining layer. Portions of the pixel defining layer not provided with the plurality of pixel openings or the plurality of light transmission holes are opaque light shields, and a portion of the display substrate overlapping each of the plurality of light transmission holes in the thickness direction is light transmissive.

Abstract: An organic light-emitting display apparatus includes a substrate; thin film transistors; a protective layer that includes a plurality of concave-convex units disposed in a pixel area; an organic light-emitting device disposed on the protective layer; and an encapsulation unit that covers the organic light-emitting device. Each of the concave-convex units protrudes from a surface of the protective layer. The organic light-emitting device includes a pixel electrode, an emission layer, and an opposite layer sequentially stacked on the concave-convex unit, and a distance between the pixel electrode and the opposite electrode is determined by 5%?(a/b)?18%, wherein ‘a’ is a vertical distance with respect to the surface of the protective layer between the pixel electrode and the opposite electrode and ‘b’ is a minimum distance between the pixel electrode and the opposite electrode.

Abstract: A display device and manufacturing method thereof with a high level of reliability is provided without increasing the number of manufacturing processes. The display device includes a first conductor, a first insulation layer including a first contact hole exposing a part of the first conductor, a second insulation layer including a second contact hole exposing at least a part of the first contact hole and a part of a surface of the first insulation layer, a pixel electrode overlapping a part of the second contact hole and electrically connected to the first conductor, and a third insulation layer contacting the first insulation layer via the second contact hole.

Abstract: The present disclosure is directed to an organic light emitting diode display device includes a substrate having an emitting area and a non-emitting area; an overcoating layer on a first surface of the substrate and including a plurality of convex portions and a plurality of concave portions, at least one of the plurality of convex portions including a bottom surface portion, a top surface portion and a side surface portion between the bottom and top surface portions; a light emitting diode on the overcoating layer; and a cholesteric liquid crystal layer at a transmission direction of a light emitted from the light emitting diode.

Abstract: An array substrate comprises a substrate including a displaying area and a connecting layout area disposed on the periphery of the displaying area, a plurality of thin film transistors, a plurality of sub-pixels and a plurality of signal lines disposed on the displaying area. The sub-pixels are electrically coupled to the plurality of thin film transistors respectively, the thin film transistors are electrically coupled to the plurality of signal lines respectively, and a plurality of input interfaces of the plurality of signal lines are disposed on the connecting layout area. Further, a driving module is disposed on the connecting layout area and the driving module includes a plurality of output interfaces. Moreover, a plurality of connecting lines are disposed between the plurality of input interfaces and the plurality of output interfaces and configured to electrically couple the plurality of input interfaces and the plurality of output interfaces respectively.

Abstract: A display device includes a substrate, a semiconductor layer on the substrate, a first insulating layer on the semiconductor layer, a first conductive layer on the semiconductor layer, a second insulating layer on the first conductive layer, a first contact hole penetrating the first insulating layer and the second insulating layer, a second conductive layer on the second insulating layer, connected to the semiconductor layer through the first contact hole, and including a hydrogen barrier material, and a third insulating layer on the second conductive layer.

Abstract: An OLED device and a method of preparing the same are provided, the OLED device including: a substrate; a first source electrode on the substrate, the first source electrode having a first side surface; a first insulating layer on the first source electrode, the first insulating layer having a second side surface intersecting with an upper surface of the first source electrode and the first side surface of the first source electrode, with at least one of an angle between the first side surface and the upper surface of the substrate and an angle between the second side surface and the upper surface of the substrate being an acute angle; an active layer on the substrate, the active layer covering the first side surface and the second side surface; a gate insulating layer on the active layer; an anode on the gate insulating layer; a light emitting functional layer on the anode; and a cathode on the light emitting functional layer, the cathode including a first drain region covering the first insulating layer and

Abstract: An organic light emitting diode (“OLED”) display device includes a substrate having a display region including a light emitting region and a peripheral region, and a pad region located in one side of the display region, a plurality of light emitting structures on the substrate in the light emitting region, and a plurality of fan-out wirings including a low fan-out wiring in the peripheral region on the substrate, a middle fan-out wiring on the low fan-out wiring, the middle fan-out wiring overlapping at least a portion of the low fan-out wiring, and an upper fan-out wiring on the middle fan-out wiring, the upper fan-out wiring overlapping at least a portion of the low fan-out wiring.

Abstract: The present disclosure provides an organic light-emitting display panel and device. The organic light-emitting display panel includes pixel units; gate lines; and data lines intersecting with and insulated from the gate lines. None of the pixel units is provided within the hollow area, and the pixel units are provided in a periphery of the hollow area. The display area includes a full display area and a half display area, and the full display area includes first to fifth display regions. The first display region, the hollow area and the second display region are sequentially arranged along a first direction. The half display area, the hollow area, and the third display region are sequentially arranged along a second direction. A number of pixel units per unit area in the full display area is greater than a number of pixel units per unit area in the half display area.

Abstract: An manufacturing method of a display device may include the following steps: forming a transistor on a substrate; forming an insulating layer on the transistor; forming a conductive layer including silver on the insulating layer; forming a photosensitive member on the conductive layer; forming an electrode of a light-emitting element by etching the conductive layer; performing plasma treatment on a structure that comprises the electrode, the plasma treatment using a gas including a halogen; and removing a product that is resulted from the plasma treatment.

Abstract: A display panel includes a substrate including a first non-display area surrounding a transmission area, a display area on an outer portion of the first non-display area, and a second non-display area surrounding the display area, driving thin film transistors and display elements in the display area, a first power supply line in the second non-display area and extending in a first direction, first driving voltage lines and second driving voltage lines extending in a second direction intersecting with the first direction and spaced apart from each other with the transmission area therebetween, and a power bus line connected to the second driving voltage lines in the first non-display area or second non-display area, the power bus line extending in the first direction. A length of the power bus line in the first direction is less than a length of the first power supply line in the first direction.

Abstract: Provided is a display device. The display device includes: one or more pixels placed in an active area and a pixel circuit associated with the pixels; and a power supply line placed in an inactive area outside the active area and connected to the pixel circuit. At least one side of the power supply line may be covered with an overcoating layer. The overcoating layer includes a first portion adjacent to the side of the power supply line and a second portion which is farther from the power supply line than the first portion. The first portion has a smaller thickness than the second portion. The first portion may be about half the thickness of the second portion.

Abstract: A tiling display device includes a plurality of display panel modules, each including: a display panel including a display area and a non-display area; a form support member bonded to the bottom surface of the display panel and supporting the form of the display panel; a fixing member attached to the bottom surface of the form support member; and a case top placed around the fixing member, for attaching to the fixing member, wherein at least one side of each display panel module overlaps a neighboring display panel module, and the surfaces of the display panel modules lie in the same line.

Abstract: A semiconductor device includes a lower electrode on a substrate, a dielectric layer structure on the lower electrode and including hafnium oxide having a tetragonal crystal phase, a template layer on the dielectric layer structure and including niobium oxide (NbOx, 0.5?x?2.5), and an upper electrode structure including a first upper electrode and a second upper electrode on the template layer.

Abstract: A method for fabricating a double-sided capacitor is disclosed, which includes: etching trenches having depths not reaching an intermediate insulating layer and trench structures having depths exceeding the intermediate insulating layer on both sides of a silicon-on-insulator (SOI) substrate; and sequentially depositing an insulating dielectric film and a conductive material on surfaces of the trenches and the trenches, then removing insulating material at a bottom of the trenches and the trenches are filled with the conductive material to form conductive channels. The upper conductive channel of the SOI substrate is insulated from an upper layer and is electrically connected to a lower layer; and the lower conductive channel is insulated from the lower layer and is electrically connected to the upper layer.

Abstract: A semiconductor apparatus includes a power semiconductor device, a resin film and a sealing insulating material. The power semiconductor device includes: a first electrode covering a first region on one main surface of the semiconductor substrate; a second electrode formed on the other main surface of the semiconductor substrate; a guard ring formed in a second region outer than the first region; and a non-conductive inorganic film located in the second region and covering the guard ring. The resin film overlaps the guard ring in a plan view, and the resin film on the non-conductive inorganic film has a thickness of 35 ?m or more. The resin film is a film of a single layer, and the resin film has an outermost edge in the form of a downwardly spreading fillet. The outermost edge of the resin film is inner than an outermost edge of the semiconductor substrate.

Abstract: The present disclosure relates to a semiconductor device, and more particularly, to a junctionless/accumulation mode transistor with dynamic control and method of manufacturing. The circuit includes a channel region and a threshold voltage control on at least one side of the channel region, the threshold voltage control being configured to provide dynamic control of a voltage threshold, leakage current, and breakdown voltage of the circuit, wherein the threshold voltage control is a different dopant or material of a source region and a drain region of the circuit.

Abstract: Provided is a semiconductor device comprising: a semiconductor substrate; an active section provided in the semiconductor substrate; an edge termination structure section provided between the active section and an outer peripheral edge of the semiconductor substrate on an upper surface of the semiconductor substrate; and an end lifetime control unit that is provided in the semiconductor substrate in the edge termination structure section and is continuous in a range facing at least two or more diode sections arranged in the first direction, wherein the active section includes: a transistor section and the diode sections alternately arranged with the transistor section in a predetermined first direction on the upper surface of the semiconductor substrate.

Abstract: The present disclosure describes a fabrication method that prevents divots during the formation of isolation regions in integrated circuit fabrication. In some embodiments, the method of forming the isolation regions includes depositing a protective layer over a semiconductor layer; patterning the protective layer to expose areas of the semiconductor layer; depositing an oxide on the exposed areas the semiconductor layer and between portions of the patterned protective layer; etching a portion of the patterned protective layer to expose the semiconductor layer; etching the exposed semiconductor layer to form isolation openings in the semiconductor layer; and filling the isolation openings with a dielectric to form the isolation regions.

Abstract: A silicon-on-insulator (SOI) substrate includes a semiconductor substrate and a multi-layered polycrystalline silicon structure. The multi-layered polycrystalline silicon structure is disposed over the semiconductor substrate. The multi-layered polycrystalline silicon structure includes a plurality of doped polycrystalline silicon layers stacked over one another, and an oxide layer between each adjacent pair of doped polycrystalline silicon layers. A number of the doped polycrystalline silicon layer is ranging from 2 to 6.

Abstract: A semiconductor device includes a source region, a drain region, a core channel region, and a barrier layer. The core channel region is between the source region and the drain region, The barrier layer is between the core channel region and the drain region, The barrier layer is a graded doped barrier layer.

Abstract: Fin-like field effect transistors (FinFETs) having high mobility strained channels and methods of fabrication thereof are disclosed herein. An exemplary method includes forming a first silicon fin in a first type FinFET device region and a second silicon fin in a second type FinFET device region. First epitaxial source/drain features and second epitaxial source/drain features are formed respectively over first source/drain regions of the first silicon fin second source/drain regions of the second silicon fin. A gate replacement process is performed to form a gate structure over a first channel region of the first silicon fin and a second channel region of the second silicon fin. During the gate replacement process, a masking layer covers the second channel region of the second silicon fin when a silicon germanium channel capping layer is formed over the first channel region of the first silicon fin.