Abstract: A heterostructure semiconductor device includes first and second active areas, each electrically isolated from one another, and each including first and second active layers with an electrical charge disposed therebetween. A power transistor is formed in the first active area, and an integrated gate resistor is formed in the second active area. A gate array laterally extends over the first active area of the power transistor. First and second ohmic contacts are respectively disposed at first and second lateral ends of the integrated gate resistor, the first and second ohmic contacts are electrically connected to the second portion of the second active layer, the second ohmic contact also being electrically connected to the gate array. A gate bus is electrically connected to the first ohmic contact.

Abstract: A metal-insulator-metal (MIM) capacitor structure includes source and drain regions formed within a semiconductor substrate, a first conducting layer formed over the source and drain regions, and a dielectric layer formed over the first conducting layer. The MIM capacitor structure further includes a second conducting layer formed over the dielectric layer, and a sidewall dielectric formed adjacent the first conducting layer and the dielectric layer. An electric field is created indirectly through the sidewall dielectric to an adjacent field effect transistor (FET) channel in the semiconductor substrate.

Abstract: An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.

Abstract: A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first and second regions; an isolation structure located in the isolation region, where the isolation structure comprises a first isolation ring having a first doping type, and a second isolation ring having a second doping type, where the first isolation ring is configured to absorb first carriers flowing from the first region to the second region, and where the second isolation ring is configured to absorb second carriers flowing from the second region to the first region; and a lateral blocking component in the isolation structure, where the lateral blocking component is configured to block a lateral flow of the first and second carriers, in order to increase a flow path of the first and second carriers in the semiconductor substrate.

Abstract: A semiconductor structure can include: a semiconductor substrate having a first region, a second region, and an isolation region disposed between the first region and the second region; an isolation component located in the isolation region; and where the isolation component is configured to recombine first carriers flowing from the first region toward the second region, and to extract second carriers flowing from the second region toward the first region.

Abstract: Provided is a semiconductor device comprising a semiconductor substrate that includes a transistor region; an emitter electrode that is provided on the semiconductor substrate; a first dummy trench portion that is provided on the transistor region of the semiconductor substrate and includes a dummy conducting portion that is electrically connected to the emitter electrode; and a first contact portion that is a partial region of the transistor region, provided between an end portion of a long portion of the first dummy trench portion and an end portion of the semiconductor substrate, and electrically connects the emitter electrode and a semiconductor region with a first conductivity type provided in the transistor region.

Abstract: Disclosed herein are structures and methods for large integrated circuit (IC) dies, as well as related assemblies and devices. For example, in some embodiments, an IC die may include: a first subvolume including first electrical structures, wherein the first electrical structures include devices in a first portion of a device layer of the IC die; a second subvolume including second electrical structures, wherein the second electrical structures include devices in a second portion of the device layer of the IC die; and a third subvolume including electrical pathways between the first subvolume and the second subvolume; wherein the IC die has an area greater than 750 square millimeters.

Abstract: Various embodiments of the present application are directed towards an integrated circuit (IC) in which a bootstrap metal-oxide-semiconductor (MOS) device is integrated with a high voltage metal-oxide-semiconductor (HVMOS) device and a high voltage junction termination (HVJT) device. In some embodiments, a drift well is in the semiconductor substrate. The drift well has a first doping type and has a ring-shaped top layout. A first switching device is on the drift well. A second switching device is on the semiconductor substrate, at an indent in a sidewall the drift well. A peripheral well is in the semiconductor substrate and has a second doping type opposite the first doping type. The peripheral well surrounds the drift well, the first switching device, and the second switching device, and further separates the second switching device from the drift well and the first switching device.

Abstract: A trimmable resistor circuit and a method for operating the trimmable resistor circuit are provided. The trimmable resistor circuit includes first sources/drains and first gate structures alternatively arranged in a first row, second sources/drains and second gate structures alternatively arranged in a second row, third sources/drains and third gate structures alternatively arranged in a third row, first resistors disposed between the first row and the second row, and second resistors disposed between the second row and the third row. In the method for operating the trimmable resistor circuit, the first gate structures in the first row and the third gate structures in the third row are turned on. Then, the second gate structures in the second row are turned on/off according to a predetermined resistance value.

Abstract: A semiconductor device has a first fin, a second fin, an isolation structure between the first fin and the second fin, a dielectric stage in the isolation structure, and a helmet layer over the dielectric stage. A top surface of the helmet layer is higher than a top surface of the isolation structure.

Abstract: A semiconductor device includes first and second transistors each having a high-k metal gate disposed over a respective channel region of the transistors. The semiconductor device further includes first and second dielectric features in physical contact with an end of the respective high-k metal gates. The first and second transistors are of a same conductivity type. The two high-k metal gates have a same number of material layers. The first transistor's threshold voltage is different from the second transistor's threshold voltage, and at least one of following is true: the two high-k metal gates have different widths, the first and second dielectric features have different distances from respective channel regions of the two transistors, and the first and second dielectric features have different dimensions.

Abstract: Semiconductor structures are provided. A first source and drain region of a first transistor is electrically connected to a first conductive line through a first contact and a first via over the first contact. A first gate electrode of the first transistor is electrically connected to a second conductive line through a second contact and a second via over the second contact. A second source and drain region of a second transistor is electrically connected to a third conductive line through a third contact and a third via over the third contact. A second gate electrode of the second transistor is electrically connected to a fourth conductive line of the metal layer directly through a fourth via. Projections of the second via and the first channel region are separated on the substrate, and projections of the fourth via and the second channel region are overlapped on the substrate.

Abstract: Semiconductor devices and methods of forming the same are provided. Semiconductor devices may include a substrate including first and second regions, first active fins extending in a first direction on the first region, second active fins extending parallel to the first active fins on the second region, and single diffusion break regions between two first active fins. Single diffusion break regions may be spaced apart from each other in the first direction. The semiconductor devices may also include a lower diffusion break region between two second active fins and extending in a second direction that is different from the first direction and upper diffusion break regions on the lower diffusion break region. The upper diffusion break regions may be spaced apart from each other in the first direction, and each of the upper diffusion break regions may overlap the lower diffusion break region.

Abstract: A method of forming a semiconductor device includes providing a fin extruding from a substrate, the fin having first epitaxial layers alternating with second epitaxial layers, the first epitaxial layers including a first semiconductor material, the second epitaxial layers including a second semiconductor material different from the first semiconductor material; etching sidewalls of at least one of the second epitaxial layers in a channel region of the fin, such that a width of the at least one of the second epitaxial layers in the channel region after etching is smaller than a width of the first epitaxial layers contacting the at least one of the second epitaxial layers; and forming a gate stack over of the fin, the gate stack engaging both the first epitaxial layers and the second epitaxial layers.

Abstract: A memory device and a method for manufacturing the memory device are provided. The memory device includes an interlayer insulating layer formed on a substrate, a conductive contact plug formed in the interlayer insulating layer, a conductive barrier structure formed on the conductive contact plug, and a capacitor structure formed on the conductive barrier structure. The area of the top surface of the conductive contact plug is smaller than the area of the bottom surface of the conductive barrier structure, and the top surface of the conductive contact plug is completely covered by the bottom surface of the conductive barrier structure.

Abstract: Semiconductor devices and fabrication methods are provided.

Abstract: Uniform layouts for SRAM and register file bit cells are described. In an example, an integrated circuit structure includes a six transistor (6T) static random access memory (SRAM) bit cell on a substrate. The 6T SRAM bit cell includes first and second active regions parallel along a first direction of the substrate. First, second, third and fourth gate lines are over the first and second active regions, the first, second, third and fourth gate lines parallel along a second direction of the substrate, the second direction perpendicular to the first direction.

Abstract: Provided is a method of forming a memory cell including a rectangular shaped via for at least one Vss node connection. In some embodiments, the rectangular shaped via has a length/width of greater than 1.5. The rectangular shaped via may be disposed on the Via0 and/or Via1 layer interfacing a first metal layer (e.g., M1). The memory cell may also include circular/square shaped vias having a length/width of between approximately 0.8 and 1.2. The circular/square shaped vias may be coplanar with the rectangular shaped vias.

Abstract: Provided are an electronic device and a method of manufacturing the same. The electronic device may include a first device provided on a first region of a substrate; and a second device provided on a second region of the substrate, wherein the first device may include a first domain layer including a ferroelectric domain and a first gate electrode on the first domain layer, and the second device may include a second domain layer including a ferroelectric domain and a second gate electrode on the second domain layer. The first domain layer and the second domain layer may have different characteristics from each other at a polarization change according to an electric field. At the polarization change according to the electric field, the first domain layer may have substantially a non-hysteretic behavior characteristic and the second domain layer may have a hysteretic behavior characteristic.

Abstract: A storage device according to the disclosure includes a first transistor and a second transistor each including a first diffusion layer, a second diffusion layer, and a gate, and that are each able to store a threshold state, a first signal line, a second signal line, a first switch transistor that is turned on and couples the first signal line and the first diffusion layer of the first transistor, a second switch transistor that is turned on and couples the second diffusion layer of the first transistor and the first diffusion layer of the second transistor, and a third switch transistor that is turned on and couples the second diffusion layer of the second transistor and the second signal line.

Abstract: A structure includes a word line, a bit line, and an anti-fuse cell. The anti-fuse cell includes a reading device, a programming device, and a dummy device. The reading device includes a first gate coupled to the first word line, a first source/drain region coupled to the bit line, and a second source/drain region. The first source/drain region and the second source/drain region are on opposite sides of the first gate. The programming device includes a second gate, a third source/drain region coupled to the second source/drain region, and a fourth source/drain region. The third source/drain region and the fourth source/drain region are on opposite sides of the second gate. The dummy device includes a third gate, a fifth source/drain region coupled to the fourth source/drain region, and a sixth source/drain region. The fifth source/drain region and the sixth source/drain region are on opposite sides of the third gate.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack and a conductive layer over a semiconductor substrate. The method includes forming a negative photoresist layer to cover the gate stack and a first portion of the conductive layer over the isolation structure and expose a second portion of the conductive layer. The method includes forming a mask layer over the negative photoresist layer and the conductive layer. The mask layer has trenches over the second portion of the conductive layer and an edge portion of the negative photoresist layer, and a thickness of the edge portion decreases in a direction away from the gate stack.

Abstract: Some embodiments include a transistor having a first electrically conductive gate portion along a first segment of a channel region and a second electrically conductive gate portion along a second segment of the channel region. The second electrically conductive gate portion is a different composition than the first electrically conductive gate portion. Some embodiments include a method of forming a semiconductor construction. First semiconductor material and metal-containing material are formed over a NAND string. An opening is formed through the metal-containing material and the first semiconductor material, and is lined with gate dielectric. Second semiconductor material is provided within the opening to form a channel region of a transistor. The transistor is a select device electrically coupled to the NAND string.

Abstract: Some embodiments include an integrated assembly with a semiconductor channel material having a boundary region where a more-heavily-doped region interfaces with a less-heavily-doped region. The more-heavily-doped region and the less-heavily-doped region have the same majority carriers. The integrated assembly includes a gating structure adjacent the semiconductor channel material and having a gating region and an interconnecting region of a common and continuous material. The gating region has a length extending along a segment of the more-heavily-doped region, a segment of the less-heavily-doped region, and the boundary region. The interconnecting region extends laterally outward from the gating region on a side opposite the semiconductor channel region, and is narrower than the length of the gating region. Some embodiments include methods of forming integrated assemblies.

Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is formed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is formed on the memory region and a dummy structure is formed on the isolation structure. A boundary sidewall spacer is formed covering the dummy structure. A protecting dielectric layer is formed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high ? etch residue during formation of the logic device structure with HKMG technology.

Abstract: Various embodiments of the present application are directed to an embedded memory boundary structure with a boundary sidewall spacer, and associated forming methods. In some embodiments, an isolation structure is disposed in a semiconductor substrate to separate a memory region from a logic region. A memory cell structure is disposed on the memory region and a cell boundary structure is formed on the isolation structure including a boundary sidewall spacer. A protecting dielectric layer is disposed on a top surface of the boundary sidewall spacer. The boundary sidewall spacer and the protecting dielectric layer provide a smooth boundary sidewall that is not subject to damage during formation of the logic device structure and, hence, is not subject to trapping high ? etch residue during formation of the logic device structure with HKMG technology.

Abstract: A memory device and manufacturing method thereof are provided. The memory device includes a pair of stacked structures, a charge storage layer, and a channel layer. The stacked structures are disposed on a substrate. Each stacked structure includes gate layers and insulating layers stacked alternately, and a cap layer on the gate layers and the insulating layers. The charge storage layer is disposed on sidewalls of the stacked structures facing each other. The channel layer covers the charge storage layer, and has a top portion, a body portion, and a bottom portion. The top portion covers sidewalls of the cap layers of the stacked structures. The bottom portion covers a portion of the substrate located between the stacked structures. The body portion is connected between the top and bottom portions. Dopant concentrations of the top and bottom portions are respectively greater than a dopant concentration of the body portion.

Abstract: A three-dimensional semiconductor device comprises a stack structure on a lower structure, a vertical channel structure passing through the stack structure, and a first vertical support structure passing through the stack structure and spaced apart from the vertical channel structure. The stack structure includes interlayer insulation layers and gate horizontal patterns, alternately stacked in a vertical direction perpendicular to an upper surface of the lower structure. The vertical channel structure and the first vertical support structure have different cross-sectional shapes. The vertical channel structure further includes a channel semiconductor layer. The vertical channel structure includes first and second vertical regions, and a width variation portion between the first and second vertical regions. The interlayer insulation layers include an intermediate interlayer insulation layer adjacent to the width variation portion.

Abstract: A semiconductor memory device includes a plurality of bit lines disposed over memory cells along a second direction intersecting with a first direction, and extending in the first direction; and a plurality of s first wirings and a plurality of second wirings alternately disposed along the second direction over the bit lines, and extending in the first direction while being bent into zigzag shapes.

Abstract: Embodiments of 3D memory devices and fabricating methods thereof are disclosed. The device comprises an array device semiconductor structure comprising an array interconnect layer disposed on the alternating conductor/dielectric stack and including a first interconnect structure. The device further comprises a peripheral device semiconductor structure comprising a peripheral interconnect layer disposed on a peripheral device and including a second interconnect structure. The device further comprises a pad embedded in the array device semiconductor structure or the peripheral interconnect layer, and a pad opening exposing a surface of the pad. The array interconnect layer is bonded with the peripheral interconnect layer, and the pad is electrically connected with the peripheral device through the first interconnect structure or the second interconnect structure.

Abstract: A semiconductor memory device includes gate lines and wiring lines which are stacked over a substrate. The gate lines are stacked over first and second cell array regions of a substrate which are disposed in a second direction crossing with a first direction, and are passed through by channel structures. The wiring lines are stacked over an interval region of the substrate which is disposed between the first and second cell array regions and over first coupling regions of the substrate which are disposed at both sides of the first and second cell array regions and the interval region in the first direction. Each of the wiring lines includes a line portion which traverses the interval region in the first direction and extended portions which are disposed over the first coupling regions. A width of the extended portions is larger than a width of the line portion.

Abstract: A vertical memory device includes a substrate having a peripheral circuit structure, first gate patterns having first gate pad regions stacked vertically from the substrate, vertical channel structures penetrating the first gate patterns, first gate contact structures each extending vertically to a corresponding first gate pad region, mold patterns stacked vertically from the substrate, the mold patterns each being positioned at the same height from the substrate with a corresponding gate pattern, peripheral contact structures penetrating the mold patterns to be connected to the peripheral circuit structure, a first block separation structure disposed between the first gate contact structures and the peripheral contact structures, and a first peripheral circuit connection wiring extending across the first block separation structure to connect one of the first gate contact structures to one of the peripheral contact structures.

Abstract: A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches which laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction, and memory stack structures arranged in rows extending along the first horizontal direction. Each row of memory stack structures is located on a respective sidewall of the line trenches. Each of the memory stack structures includes a vertical semiconductor channel, a tunneling dielectric contacting the vertical semiconductor channel, a charge storage layer contacting the tunneling dielectric, and a composite blocking dielectric. The composite blocking dielectric includes a first dipole-containing blocking dielectric layer stack, a homogeneous blocking dielectric layer, and a second dipole-containing blocking dielectric layer stack.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and word lines located over a substrate, memory stack structures extending through the alternating stack and containing a respective vertical semiconductor channel and a respective memory film, drain select gate electrodes located over the alternating stack, extending along a first horizontal direction, and laterally spaced apart along a second horizontal direction, and a dielectric cap layer located between adjacent drain select gate electrodes. An air gap is located between adjacent drain select gate electrodes in the dielectric cap layer.

Abstract: Embodiments of 3D memory devices with a structurally-reinforced semiconductor plug and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack is formed on a substrate. The dielectric stack includes a plurality of interleaved dielectric layers and sacrificial layers. An opening extending vertically through the dielectric stack is formed. A shallow recess is formed by removing a part of a sacrificial layer abutting a sidewall of the opening. The sacrificial layer is at a lower portion of the dielectric stack. A semiconductor plug is formed at a lower portion of the opening. A part of the semiconductor plug protrudes into the shallow recess. A channel structure is formed above and in contact with the semiconductor plug in the opening. A memory stack including a plurality of conductor/dielectric layer pairs is formed by replacing, with a plurality of conductor layers, the sacrificial layers in the dielectric stack.

Abstract: Embodiments of three-dimensional memory device architectures and fabrication methods therefore are disclosed. In an example, the memory device includes a substrate having a first layer stack on it. The first layer stack includes alternating conductor and insulator layers. A second layer stack is disposed over the first layer stack where the second layer stack also includes alternating conductor and insulator layers. One or more vertical structures extend through the first layers stack. A conductive material is disposed on a top surface of the one or more vertical structures. One or more second vertical structures extend through the second layer stack and through a portion of the conductive material.

Abstract: A semiconductor wafer according to the present embodiment includes a plurality of semiconductor chip regions and a division region. The plurality of semiconductor chip regions have a semiconductor element. The division region is provided between the semiconductor chip regions adjacent to each other. A first stacked body is provided on the division region. The first stacked body is configured with a plurality of first material films and a plurality of second material films alternately stacked.

Abstract: A semiconductor device includes a gate stack arranged on a channel region of a semiconductor layer and a semiconductor layer arranged on an insulator layer. A crystalline source/drain region is arranged in a cavity in the insulator layer, and a spacer is arranged adjacent to the gate stack, the spacer arranged over the source/drain region. A second insulator layer is arranged on the spacer and the gate stack, and a conductive contact is arranged in the source/drain region.

Abstract: Provided is an active matrix substrate (100A) including: a gate metal layer (15) that has a two-layer structure composed of a Cu layer (15b) and a Ti layer (15a); a first insulating layer (16) on the gate metal layer (15); a source metal layer (18) that is formed on the first insulating layer (16) and has a two-layer structure composed of a Cu layer (18b) and a Ti layer (18a); a second insulating layer (19) on the source metal layer (18); a conductive layer (25) that is formed on the second insulating layer (19), and is in contact with the gate metal layer (15) within a first opening (16a1) formed in the first insulating layer (16) and is in contact with the source metal layer (18) within a second opening (19a2) formed in the second insulating layer (19); and a first transparent conductive layer (21) that is formed on the conductive layer (25) and includes any of a pixel electrode, a common electrode and an auxiliary capacitor electrode.

Abstract: A pixel structure includes a scan line, a data line, a reference voltage line, a first transistor, a second transistor, a third transistor, a first pixel electrode and a second pixel electrode. The reference voltage line is separated from the data line and intersected with the scan line. A first electrode of the second transistor, a second electrode of the second transistor and a first electrode of the third transistor have straight line portions overlapped with a second semiconductor pattern of the second transistor and a third semiconductor pattern of the third transistor. Both ends of each of the straight line portions are located outside a normal projection region of a first semiconductor pattern of the first transistor, a normal projection region of the second semiconductor pattern of the second transistor and a normal projection region of the third semiconductor pattern of the third transistor.

Abstract: Provided are an array substrate, a manufacturing method therefor, a display panel and a display device. The array substrate includes: a photosensitive member and a thin film transistor that are located on a base substrate, the photosensitive member including a photosensitive layer; the thin film transistor is located at a side of the photosensitive member that is far from the base substrate. In the described array substrate, the photosensitive member is formed first, and then the thin film transistor is formed on the photosensitive member, which prevents the element hydrogen from influencing the thin film transistor when forming the photosensitive member, while source and drain layer patterns of the thin film transistor may be formed by means of one-time pattern processing, thus simplifying the manufacturing process.

Abstract: In one embodiment, an integrated circuit cell includes a first circuit component and a second circuit component. The first circuit component includes fin field-effect transistors (finFETs) formed in a high fin portion of the integrated circuit cell, the high fin portion of the integrated circuit including a plurality of fin structures arranged in rows. The second circuit component that includes finFETs formed in a less fin portion of the integrated circuit cell, the less fin portion of the integrated circuit including a lesser number of fin structures than the high fin portion of the integrated circuit cell.

Abstract: An aperture ratio of a semiconductor device is improved. A driver circuit and a pixel are provided over one substrate, and a first thin film transistor in the driver circuit and a second thin film transistor in the pixel each include a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide semiconductor layer over the gate insulating layer, source and drain electrode layers over the oxide semiconductor layer, and an oxide insulating layer in contact with part of the oxide semiconductor layer over the gate insulating layer, the oxide semiconductor layer, and the source and drain electrode layers. The gate electrode layer, the gate insulating layer, the oxide semiconductor layer, the source and drain electrode layers, and the oxide insulating layer of the second thin film transistor each have a light-transmitting property.

Abstract: A wiring film capable of being patterned by a single etching process and has strong adhesion force to a resin substrate, and a semiconductor element and a display device that uses the wiring film, are disclosed. Since a base film that is in contact with a resin substrate is a copper thin film containing, at a predetermined ratio, aluminum as a main additive metal and silicon, titanium or nickel as a secondary additive metal, and has strong adhesion force to resins, wiring films (a gate electrode layer) do not separate from the resin substrate. Also, since the base film and a low resistance film contain a large amount of copper, the base film and the low resistance film may be etched together by means of an etchant or an etching gas by which copper is etched, therefore, the wiring films are able to be patterned by a single etching process.

Abstract: Various embodiments of the present application are directed towards image sensors including composite backside illuminated (CBSI) structures to enhance performance. In some embodiments, a first trench isolation structure extends into a backside of a substrate to a first depth and comprises a pair of first trench isolation segments. A photodetector is in the substrate, between and bordering the first trench isolation segments. A second trench isolation structure is between the first trench isolation segments and extends into the backside of the substrate to a second depth less than the first depth. The second trench isolation structure comprises a pair of second trench isolation segments. An absorption enhancement structure overlies the photodetector, between the second trench isolation segments, and is recessed into the backside of the semiconductor substrate. The absorption enhancement structure and the second trench isolation structure collectively define a CBSI structure.

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of pixel regions is disposed within a substrate and respectively comprising a photodiode. The photodiode comprises a doped layer with a first doping type and an adjoining region of the substrate with a second doping type that is different than the first doping type. A boundary deep trench isolation (BDTI) structure is disposed between adjacent pixel regions. A multiple deep trench isolation (MDTI) structure overlies the doped layer of the photodiode. The MDTI structure comprises a stack of dielectric layers lining sidewalls of a MDTI trench. A plurality of color filters is disposed at the back-side of the substrate corresponding to the respective photodiode of the plurality of pixel regions and overlying the MDTI structure.

Abstract: The present disclosure relates to a CMOS image sensor having a multiple deep trench isolation (MDTI) structure, and an associated method of formation. In some embodiments, a plurality of photodiodes is formed from a front-side of a substrate. A plurality of boundary deep trench isolation (BDTI) trenches having a first depth and a plurality of multiple deep trench isolation (MDTI) trenches having a second depth are formed from a back-side of the substrate. A stack of dielectric layers is formed in the BDTI trenches and the MDTI trenches. A plurality of color filters is formed overlying the stack of dielectric layers corresponding to the plurality of photodiodes.

Abstract: An image sensor includes a substrate including a light-receiving region and a light-shielding region, a device isolation pattern in the substrate of the light-receiving region to define active pixels, and a device isolation region in the substrate of the light-shielding region to define reference pixels. An isolation technique of the device isolation pattern is different from that of the device isolation region.

Abstract: Disclosed is an image sensor comprising a first substrate including a plurality of pixels, a photoelectric conversion region in the first substrate at each of the pixels, a first capacitor on the first substrate, and a shield structure spaced apart from and surrounding the first capacitor.

Abstract: The present disclosure relates to a CMOS image sensor, and an associated method of formation. In some embodiments, the CMOS image sensor comprises a floating diffusion region disposed at one side of a transfer gate within a substrate and a photo detecting column disposed at the other side of the transfer gate opposing to the floating diffusion region within the substrate. The photo detecting column comprises a doped sensing layer with a doping type opposite to that of the substrate. The photo detecting column and the substrate are in contact with each other at a junction interface comprising one or more recessed portions. By forming the junction interface with recessed portions, the junction interface is enlarged compared to a previous p-n junction interface without recessed portions, and thus a full well capacity of the photodiode structure is improved.