Abstract: Various embodiments of the present disclosure are directed towards a ferroelectric memory device. The ferroelectric memory device includes a pair of source/drain regions disposed in a semiconductor substrate. A gate dielectric is disposed over the semiconductor substrate and between the source/drain regions. A first conductive structure is disposed on the gate dielectric. A ferroelectric structure is disposed on the first conductive structure. A second conductive structure is disposed on the ferroelectric structure, where both the first conductive structure and the second conductive structure have an overall electronegativity that is greater than or equal to an overall electronegativity of the ferroelectric structure.

Abstract: A semiconductor device includes a memory circuit and a logic circuit. The memory circuit includes a word line, a bit line, a common line and a memory transistor having a gate coupled to the word line, a drain coupled to the bit line and a source coupled to the common line. The logic circuit includes a field effect transistor (FET) having a gate, a drain and a source. The memory transistor has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a first insulating layer and a first ferroelectric (FE) material layer. The FET has a gate electrode layer formed on a gate dielectric layer, and the gate dielectric layer includes a second insulating layer and a second FE material layer.

Abstract: Described is an apparatus which comprises: a gate comprising a metal; a first layer adjacent to the gate, the first layer comprising a dielectric material; a second layer adjacent to the first layer, the second layer comprising a second material; a third layer adjacent to the second layer, the third layer comprising a third material including an amorphous metal oxide; a fourth layer adjacent to the third layer, the fourth layer comprising a fourth material, wherein the fourth and second materials are different than the third material; a source partially adjacent to the fourth layer; and a drain partially adjacent to the fourth layer.

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.

Abstract: Embodiments of the invention are directed to a method that includes forming a nanosheet stack over a substrate. The nanosheet stack includes a first channel nanosheet having a first end region, a second end region, and a central region positioned between the first end region and the second end region. The first end region, the second end region, and the central region each includes a first type of semiconductor material, wherein, when the first type of semiconductor material is at a first temperature, the first type of semiconductor material has a first diffusion coefficient for a dopant. The central region is converted to a second type of semiconductor material, wherein, when the second type of semiconductor material is at the first temperature, the second type of semiconductor material has a second diffusion coefficient for the dopant.

Abstract: A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

Abstract: [Problem] Provided is a semiconductor device that is allowed to withstand a higher voltage while having a more efficient occupancy area.

Abstract: A light source package structure is provided. The light source package structure includes a substrate, an upper electrode layer, a light emitting unit, a photodiode, a surrounding wall, a light permeable element, and a coating layer. The substrate includes a first surface and a second surface that is opposite to the first surface. The upper electrode layer is disposed on the first surface of the substrate. The light emitting unit and the photodiode both are disposed on the upper electrode layer. The surrounding wall is disposed on the first surface and is arranged to surround the light emitting unit and the photodiode. The light permeable element is disposed on the surrounding wall. The coating layer is disposed inside of the surrounding wall and is coated on a part of the first surface and a part of the upper electrode layer.

Abstract: A light filter structure is provided. The light filter structure includes a substrate having a plurality of photoelectric conversion elements. The light filter structure also includes a dielectric-stacking layer disposed on the substrate. The light filter structure further includes a flattening layer disposed on the dielectric-stacking layer. The dielectric-stacking layer has a wedge portion and a flattening portion adjacent to the wedge portion, the wedge portion has a continuously or non-continuously varied thickness, and the flattening portion has a substantially constant thickness.

Abstract: In an illuminance sensor, a slow axis of a first quarter-wave plate has a relation of +45° or ?45° in regard to a polarization direction of a first linear polarization plate; a relation of a slow axis of a first portion of a second quarter-wave plate in regard to a polarization direction of a second linear polarization plate is the same with relation of the slow axis of the first quarter-wave plate in regard to the polarization direction of the first linear polarization plate, that is, +45° or ?45°; and a relation of a slow axis of a second portion of the second quarter plate in regard to the polarization direction of the second linear polarization plate is ?45° or +45° that is opposite in sign to the relation of the slow axis of the first quarter-plate in regard to the polarization direction of the first linear polarization plate.

Abstract: A semiconductor light-receiving element includes a substrate; a light-receiving mesa portion, formed on top of the substrate, including a first semiconductor layer of a first conductivity type, an absorption layer, and a second semiconductor layer of a second conductivity type; a light-receiving portion electrode, formed above the light-receiving mesa portion, connected to the first semiconductor layer; a pad electrode formed on top of the substrate; and a bridge electrode, placed so that an insulating gap is interposed between the bridge electrode and the second semiconductor layer, configured to connect the light-receiving portion electrode and the pad electrode on top of the substrate, the bridge electrode being formed in a layer separate from layers of the light-receiving portion electrode and the pad electrode.

Abstract: A solid state imaging apparatus includes an insulation structure formed of an insulation substance penetrating through at least a silicon layer at a light receiving surface side, the insulation structure having a forward tapered shape where a top diameter at an upper portion of the light receiving surface side of the silicon layer is greater than a bottom diameter at a bottom portion of the silicon layer. Also, there are provided a method of producing the solid state imaging apparatus and an electronic device including the solid state imaging apparatus.

Abstract: The present invention pertains to photodetectors based on colloidal quantum dot films. An ultrathin layer of metal oxide deposited at the heterojunction interface by atomic layer deposition (ALD) results in quantum dot infrared photodetectors with increased photocurrent, decreased dark current, and world-record specific detectivity of >2×1012 Jones for 2000-2550 nm at room temperature and zero applied bias. This detectivity is an order of magnitude higher than the detectivity of commercial detectors and better than any previously-published nanomaterial. In addition to record sensitivity, the devices of the present invention have large linear dynamic range (>120 dB) and good speed (39 kHz). The device fabrication is amenable to making detector arrays at the wafer scale. It has been shown that the thin metal oxide interlayer passivates interfacial defect states, which results in the lower dark current and improved photocurrent at zero bias.

Abstract: A space-grade solar array includes relatively small cells with integrated wiring embedded into or incorporated directly onto a printed circuit board. The integrated wiring provides an interface for solar cells having back side electrical contacts. The single side contacts enable the use of pick and place (PnP) technology in manufacturing the space-grade solar array. The solar cell is easily and efficiently packaged and electrically interconnected with other solar cells on a solar panel such as by using PnP process. The back side contacts are matched from a size and positioning standpoint to corresponding contacts on the printed circuit board.

Abstract: A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.

Abstract: Disclosed is a solar cell module, which comprises: a plurality of solar cells; a light transmitting element disposed on the light receiving side of the plurality of solar cells; a front encapsulant layer between the plurality of solar cells and the light transmitting element; a plurality of tabbing ribbons disposed on the light receiving surfaces of the plurality of solar cells for connecting the plurality of solar cells; and a light redirecting film disposed upon the on-the-cell portion of at least one said tabbing ribbon; the light redirecting film comprises an optical structure layer facing the light transmitting element, for reflecting light toward the interface between the light transmitting element and the air, which light is subsequently totally internally reflected back to the surfaces of the solar cells, wherein the thickness of the light redirecting film is between 20 ?m and 115 ?m, and the gram weight of the front encapsulant layer is between 400 g/m2 and 500 g/m2.

Abstract: A method of emitting photons at a desired wavelength, including: providing a material having a first region of high absorption of radiation at a first set of wavelength of radiation, contiguous with a second region of low absorption of radiation at a shorter set of wavelengths, and a third region of high emission at a further shorter set of wavelengths; applying energy to the material at the first region, such that most of an effective black body radiation of said material at a temperature of the material would fall within the second region and be configured to transfer energy to said third region and not overlap with the first region; and emitting energy from the material at the third region, powered by said applying energy.

Abstract: The present invention provides a solar cell module, which comprises: a back panel, a rear package layer, a plurality of mutually spaced solar cells, a front package layer, and a light-transmissive element, which are successively disposed along a thickness direction of the solar cell module. The solar cell module further comprises at least one light redirecting film, each light redirecting film comprising an optical structure layer. The light redirecting film is disposed on a surface, opposite to the side where the solar cells are located, of the rear package layer; the position of the light redirecting film corresponds to a region between the solar cells. The optical structure layer faces the rear package layer, such that the optical structure layer reflects the light towards an interface between the light-transmissive element and the air; and the light is then totally internally reflected to light-facing surfaces of the solar cells.

Abstract: Method and system for wavelength thermophotovoltaic (WTPV) power generation. In one embodiment, the system comprises a refractory waveguide that collects broadband infrared light generated by a heat source; a filter that filters the collected broadband infrared light to generate narrow-band infrared light; and a thermophotovoltaic (TPV) converter, thermally de-coupled from the heat source, that receives the narrow-band infrared light and converts the received narrow-band infrared light to electrical power.

Abstract: In one example embodiment, a PCBA, an optoelectronic module, an electrical coupling, and/or a high speed interconnect may include a first contact pad, a second contact pad adjacent to and spaced apart from the first contact pad, a first wire coupled to the first contact pad via a first ball bump, and a second wire coupled to the second contact pad via a double ball bump.

Abstract: The present disclosure relates to methods and apparatus for structuring a semiconductor substrate. In one embodiment, a method of substrate structuring includes applying a resist layer to a substrate optionally disposed on a carrier. The resist layer is patterned using ultraviolet radiation or laser ablation. The patterned portions of the resist layer are then transferred onto the substrate by micro-blasting to form desired features in the substrate while unexposed or un-ablated portions of the resist layer shield the rest of the substrate. The substrate is then exposed to an etch process and a de-bonding process to remove the resist layer and release the carrier.

Abstract: A template for growing Group III-nitride semiconductor layers, a Group III-nitride semiconductor light emitting device and methods of manufacturing the same are provided. The template for growing Group III-nitride semiconductor layers includes a growth substrate having a first plane, a second plane opposite to the first plane and a groove extending inwards the growth substrate from the first plane, an insert for heat dissipation placed and secured in the groove, and a nucleation layer formed on a partially removed portion of the first plane.

Abstract: An optoelectronic semiconductor component is specified which comprises a semiconductor layer sequence having a first and a second semiconductor layer of a first conductivity type, an active layer designed for generating electromagnetic radiation, a first electrical terminal layer and a second electrical terminal layer laterally spaced therefrom which electrically contacts the second semiconductor layer, and a first contact zone of a second conductivity type which adjoins the first electrical terminal layer and is electrically conductively connected to the first electrical terminal layer. And at least one functional region formed between the first and second terminal layers, in which a second contact zone of a second conductivity type and at least one shielding zone of a second conductivity type is formed. Furthermore, a method for producing the optoelectronic semiconductor component is specified.

Abstract: Provided are a method of manufacturing a display device and a source substrate structure. The method of manufacturing the display device includes holding a light-emitting element on a source substrate that passes laser light of a certain wavelength therethrough, the holding being performed by a release layer between the source substrate and the light-emitting element, forming an adhesive layer on a driving substrate on which a driving substrate-side electrode is formed, moving the light-emitting element to a surface of the adhesive layer on the driving substrate from the source substrate by irradiating laser light of the certain wavelength to the release layer through the source substrate, and adhering the moved light-emitting element to the driving substrate by using the adhesive layer, and the release layer comprises a resin material with a thickness that is greater than or equal to 0.1 ?m and is less than or equal to 0.5 ?m.

Abstract: A method of manufacturing a micro light emitting diode (LED) display and a transfer apparatus are provided. The method of manufacturing a micro LED display includes: identifying a repairing micro LED, from among a plurality of second micro LEDs, on a second substrate based on a first position of a defective micro LED, from among a plurality of first micro LEDs, on a first substrate; removing the defective micro LED from the first substrate; matching the first position on the first substrate from which the defective micro LED has been removed to a second position of the repairing micro LED on the second substrate; and transferring the repairing micro LED from the second position on the second substrate to the first position on the first substrate from which the defective micro LED has been removed, by using a laser transfer method.

Abstract: Disclosed herein are techniques for bonding components of LEDs. According to certain embodiments, a device includes a first component having a semiconductor layer stack including an n-side semiconductor layer, an active light emitting layer, and a p-side semiconductor layer. A plurality of mesa shapes are formed within the n-side semiconductor layer, the active light emitting layer, and the p-side semiconductor layer. The semiconductor layer stack comprises a III-V semiconductor material. The device also includes a second component having a passive or an active matrix integrated circuit within a Si layer. A first dielectric material of the first component is bonded to a second dielectric material of the second component, first contacts of the first component are aligned with and bonded to second contacts of the second component, and a run-out between the first contacts and the second contacts is less than 200 nm.

Abstract: The nitride semiconductor light-emitting element comprises a light-emitting element structure portion having a plurality of nitride semiconductor layers including at least an n-type layer, an active layer and a p-type layer. The active layer has a quantum well structure comprising at least one well layer composed of a GaN-based semiconductor. In the well layer, the shortest distance between a first surface on the n-type layer side and a second surface on the p-type layer side varies in an orthogonal plane to the layering direction of the nitride semiconductor layers, and the peak emission wavelength of light emitted from the light-emitting element structure portion is shorter than 354 nm.

Abstract: Disclosed herein are techniques for bonding components of LEDs. According to certain embodiments, a micro-LED includes a first component having a semiconductor layer stack including an n-side semiconductor layer, an active light emitting layer, and a p-side semiconductor layer. The semiconductor layer stack includes a III-V semiconductor material. The micro-LED also includes a second component having a passive or an active matrix integrated circuit within a Si layer. A first dielectric material of the first component is bonded to a second dielectric material of the second component, first contacts of the first component are aligned with and bonded to second contacts of the second component, a surface recombination velocity (SRV) of the micro-LED is less than or equal to 3E4 cm/s, and an e-h diffusion of the micro-LED is less than or equal to 20 cm2/s.

Abstract: A red light emitting diode including an epitaxial stacked layer, a first and a second electrodes and a first and a second electrode pads is provided. The epitaxial stacked layer includes a first-type and a second-type semiconductor layers and a light emitting layer. A main light emitting wavelength of the light emitting layer falls in a red light range. The epitaxial stacked layer has a first side adjacent to the first semiconductor layer and a second side adjacent to the second semiconductor layer. The first and the second electrodes are respectively electrically connected to the first-type and the second-type semiconductor layers, and respectively located to the first and the second sides. The first and a second electrode pads are respectively disposed on the first and the second electrodes and respectively electrically connected to the first and the second electrodes. The first and the second electrode pads are located at the first side of the epitaxial stacked layer.

Abstract: A semiconductor light-emitting device includes a substrate; a first semiconductor layer and a second semiconductor layer formed on the substrate, wherein the first semiconductor layer includes a first exposed portion and a second portion; a plurality of first trenches formed on the substrate and including a surface composed by the first exposed portion; a second trench formed on the substrate and including a surface composed by the second exposed portion at a periphery region of the semiconductor light-emitting device, wherein each of the plurality of first trenches is branched from the second trench; and a patterned metal layer formed on the second semiconductor layer and including a first metal region and a second metal region, and portions of the second metal region are formed in the plurality of first trenches and the second trench to electrically connect to the first exposed portion and the second exposed portion.

Abstract: A micro device includes an epitaxial structure, an insulating layer, and a light-transmissive layer. The epitaxial structure has a top surface and a bottom surface opposite to each other and a peripheral surface connected to the top surface and the bottom surface. The insulating layer covers the peripheral surface and the bottom surface of the epitaxial structure and exposes a portion of the peripheral surface. The light-transmissive layer covers the top surface of the epitaxial structure and is extended over at least a portion of the portion of the peripheral surface.

Abstract: This specification discloses lighting device the includes a combination of a royal-blue and blue pump LEDs with a mixture of phosphors to provide light with a high melanopic content and maximize an m/p ratio while maintaining high color fidelity, and a tunable lighting system including the lighting device.

Abstract: A multilayer ceramic converter with stratified scattering is disclosed. In an embodiment a ceramic wavelength converter assembly having a layered structure includes a phosphor layer, an upper barrier layer, and a lower barrier layer, wherein the phosphor layer is at least partially disposed between the upper barrier layer and the lower barrier layer.

Abstract: A light emitting device includes a light emitting element, a light guide member, a reflecting member, a wavelength conversion member. The light emitting element has a light emitting surface and lateral surfaces. The light guiding member is provided on at least a portion of the lateral surfaces of the light emitting element. The reflecting member is provided on the lateral surface of the light emitting element with the light guiding member interposed therebetween. The wavelength conversion member is provided on the light emitting surface of the light emitting element, the light guiding member and the reflecting member. The wavelength conversion member is provided with a recess between an outer lateral surface of the wavelength conversion member and the light guiding member. The reflecting member is provided in the recess.

Abstract: A light-emitting device includes: a substrate; at least one light-emitting element on or above the substrate, the at least one light-emitting element having an upper surface serving as a light-emitting surface of the at least one light-emitting element; a light-transmissive member that is plate-shaped and has a lower surface that faces the upper surface of the at least one light-emitting element; and a covering member that covers a lateral surface of the at least one light-emitting element and a lateral surface of the light-transmissive member.

Abstract: The present disclosure provides an ultra-high color rendering white light-emitting device including a semiconductor LED chip that emits a violet wavelength range of light with an emission peak at 380 nm to 430 nm, and a phosphor layer distributed in a transparent resin layer that emits light when excited by an excitation wavelength of the violet LED chip, wherein the phosphor layer includes a first phosphor having an emission peak at 450-470 nm, a second phosphor having an emission peak at 510-550 nm, a third phosphor having an emission peak at 550-590 nm, a fourth phosphor having an emission peak at 630-660 nm, and a fifth phosphor having an emission peak at 660-730 nm, and the ultra-high color rendering white light-emitting device has Ra that is equal to or higher than 98 and less than 100.

Abstract: A method for molding a display module includes forming a cavity using a die plate of a first die and a plurality of side surface dies; filling the cavity with a coating material; fixing the display module to a second die using a coupling body disposed on a second surface of the display module, opposite of a first surface of the display module disposed with a plurality of LEDs; soaking the display module in the coating material filled in the cavity; curing the coating material; and separating the cured coating material of the display module from the die plate.

Abstract: An optoelectronic device and a method of producing an optoelectronic device are disclosed. In an embodiment an optoelectronic device includes components including an active layer stack, a housing and electrical contacts and at least one protective layer on a surface of at least one of the components, wherein the at least one protective layer includes a cross-linked material with a three-dimensional polysiloxane-based network.

Abstract: A light emitting diode package is disclosed. The light emitting diode package includes a light emitting diode chip emitting light and a light transmissive member. The light transmissive member covers at least an upper surface of the light emitting diode chip and includes a light transmissive resin and reinforcing fillers. The reinforcing fillers have at least two side surfaces having different lengths and are dispersed in the light transmissive resin.

Abstract: A lens for distribution of light predominantly toward a preferential side from a light emitter having an emitter axis. The lens has a faceted output region, a smooth output surface and at least one reflective surface which reflects light through total-internal-reflection (TIR) toward the faceted output region. The faceted output region is formed by pairs of transverse surfaces each surface of which redirects the received light to provide a composite illuminance pattern. The lens may further have faceted input surfaces at least partially defining a light-input cavity about the emitter axis. The faceted input region are formed by pairs of transverse surfaces each surface of which redirects the received light.

Abstract: An embodiment provides a semiconductor device package and a light emitting device comprising same, the semiconductor device package comprising: a body including a first cavity; and a semiconductor device disposed within the first cavity, wherein: the first cavity includes a first surface inclined such that the area of the cavity gradually increases as going away from the semiconductor device, and a plurality of second surfaces perpendicular to the upper surface of the semiconductor device; the body includes a first outer surface and a third outer surface that are opposite to each other, a second outer surface and a fourth surface that are opposite to each other, a first corner portion disposed in a region where the first and second outer surfaces meet each other, a second corner portion disposed in a region where the second and third outer surfaces meet each other, a third corner portion disposed in a region where the third and fourth outer surfaces meet each other, and a fourth corner portion disposed in a r

Abstract: Disclosed herein are techniques for bonding components of LEDs. According to certain embodiments, a method includes performing p-side processing of a first component. The p-side processing is performed from a direction adjacent to a surface of a p-side semiconductor layer of the first component that is opposite to an active light emitting layer of the first component. The method also includes aligning first contacts of the first component with second contacts of the second component, and subsequently performing hybrid bonding of the first component to the second component by performing dielectric bonding of a first dielectric material of the first component with a second dielectric material of the second component at a first temperature, and subsequently performing metal bonding of the first contacts of the first component with the second contacts of the second component by annealing the first contacts and the second contacts at a second temperature.

Abstract: A method for manufacturing a light emitting device includes preparing a light transmissive member block including a first light transmissive member block having a plate like shape and including a resin containing at least one phosphor and a second light transmissive member block including a material harder than a material of the first light transmissive member block. Grooves are formed on an upper face of the second light transmissive member block. The light transmissive member block is divided at the grooves to obtain a plurality of light transmissive members each having a first light transmissive member and a second light transmissive member. A lower face of the first light transmissive member and an upper face of a light emitting element are bonded together such that a lower face perimeter of the first light transmissive member is located outside of an upper face perimeter of the light emitting element.

Abstract: An optoelectronic component includes a first optoelectronic semiconductor chip configured to emit infrared light; a second optoelectronic semiconductor chip configured to emit visible light; a reflector body including a top side and an underside, wherein the reflector body includes a cavity opened toward the top side, a wall of the cavity constitutes a reflector, and the first optoelectronic semiconductor chip is arranged at a bottom of the cavity, an optical lens arranged at the top side of the reflector body, and an optical waveguide extending through the reflector body from the underside to the top side, wherein the reflector body is arranged above the second optoelectronic semiconductor chip such that light emitted by the second optoelectronic semiconductor chip passes into the optical waveguide at the underside of the reflector body, and light may emerge from the optical waveguide at the top side of the reflector body.

Abstract: An electronic device is provided in the present disclosure. The electronic device includes a substrate and a light emitting diode. The light emitting diode is bonded to the substrate through a solder alloy. The solder alloy includes tin and a metal element M, and the metal element M is one of the indium and bismuth. The atomic percentage of tin in the sum of tin and the metal element M ranges from 60% to 90% in the solder alloy.

Abstract: Disclosed herein are techniques for bonding components of LEDs. According to certain embodiments, a device includes a first component and a second component. The first component includes a semiconductor layer stack having an n-side semiconductor layer, an active light emitting layer, and a p-side semiconductor layer. The semiconductor layer stack includes a III-V semiconductor material. The second component includes a passive or an active matrix integrated circuit within a Si layer. A first dielectric material of the first component is bonded to a second dielectric material of the second component. First contacts of the first component are aligned with and bonded to second contacts of the second component. The first contacts of the first component form a first pattern within the first dielectric material of the first component, and the second contacts of the second component form a second pattern within the second dielectric material of the second component.

Abstract: Disclosed is a semiconductor device package comprising: first insulation layers disposed between first wiring lines and second wiring lines; a plurality of first pads electrically connected to the first wiring lines, respectively; and a plurality of second pads electrically connected to the second wiring lines, respectively, wherein the line having the longest length extended in a first direction, among the plurality of first wiring lines, has an area of a region, which is overlapped with an electrically connected semiconductor structure, that is larger than that of the line having the shortest extended length.

Abstract: A thermoelectric module includes: unit thermoelectric materials including N-type thermoelectric materials and P-type thermoelectric materials and arranged on one surface of a first substrate; first electrodes each electrically connected to one end of a respective one of the N-type thermoelectric materials or to one end of a respective one of the P-type thermoelectric materials; second electrodes each disposed to be spaced apart from the other end of the respective one of the N-type thermoelectric materials and the other end of the respective one of the P-type thermoelectric materials by a predetermined gap; and a second substrate supporting the second electrodes, in which each of the second electrodes is electrically connected to the second end of the respective one of the N-type thermoelectric materials and the second end of the respective one of the P-type thermoelectric materials when a pressing force is applied to the second substrate.

Abstract: A device includes a first substrate formed of a first material that exhibits a threshold level of thermal conductivity. The threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, the device also includes a second substrate disposed in a recess of the first substrate, the second substrate formed of a second material that exhibits a second threshold level of thermal conductivity. The second threshold level of thermal conductivity is achieved at a cryogenic temperature range in which a quantum circuit operates. In an embodiment, at least one qubit is disposed on the second substrate. In an embodiment, the device also includes a transmission line configured to carry a microwave signal between the first substrate and the second substrate.

Abstract: Provided is a piezoelectric film including an AlN crystal, and a first element and a second element doped to the AlN crystal. The first element is an element having an ionic radius larger than an ionic radius of Al. The second element is an element having an ionic radius smaller than the ionic radius of Al. Also provided are piezoelectric film laminated body including an underlayer and a piezoelectric film including ScAlN, and a method of manufacturing the same. The underlayer has a crystal lattice having six-fold symmetry or three-fold symmetry. Also provided are a piezoelectric film including ScAlN having a laminated structure of a hexagonal crystal and a cubic crystal, and a method of manufacturing the same. The cubic crystal is doped with an element other than trivalent element.