Patents Issued in February 1, 2024
  • Publication number: 20240038548
    Abstract: The present disclosure provides a method of preparing active areas. The method includes the operations of: receiving a substrate having an oxide layer, a nitride layer, and a silicon layer thereon; forming a patterned photoresist layer on the silicon layer; depositing a mask layer to cover a contour of the patterned photoresist layer; coating a carbon layer on the mask layer; etching the carbon layer, the mask layer, and the silicon layer to expose a top surface of the nitride layer; forming a plurality of opens in the oxide layer to expose a top surface of the substrate; and growing an epitaxial layer from the top surface of the substrate in the plurality of opens to form the active areas.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 1, 2024
    Inventor: YING-CHENG CHUANG
  • Publication number: 20240038549
    Abstract: A method of manufacturing a semiconductor package includes forming a plurality of conductive patterns on a substrate, forming a photoresist film over the substrate to cover the plurality of conductive patterns, forming a photoresist pattern from the photoresist film by a photolithography process using a photomask that includes a transparent area, a light-shielding area, and a semi-transparent area transmitting only a portion of light incident thereon, wherein the photoresist pattern includes a via hole, which exposes one conductive pattern, and a recessed portion, which has a lower surface exposing a portion of the photoresist pattern, forming a conductive post in the via hole, and removing the photoresist pattern by using a photoresist stripping composition.
    Type: Application
    Filed: March 24, 2023
    Publication date: February 1, 2024
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jakyoung GU, Minsoo KIM, Jihye SHIM, Kyoungok JUNG
  • Publication number: 20240038550
    Abstract: The present disclosure discloses a manufacturing method of an electronic device. A seed layer is formed on a substrate. After patterning the seed layer to form a plurality of sub-seed layers and a plurality of conductive lines, a metal layer is formed on a plurality of the sub-seed layers. The sub-seed layers include a first sub-seed layer and a second sub-seed layer, and the first sub-seed layer and the second sub-seed layer are separated from each other.
    Type: Application
    Filed: October 20, 2022
    Publication date: February 1, 2024
    Applicant: InnoLux Corporation
    Inventors: Chin-Lung TING, Cheng-Chi WANG, Yu-Jen CHANG, Ju-Li WANG
  • Publication number: 20240038551
    Abstract: A coating composition for wafer protection and a method of manufacturing a semiconductor package, the coating composition includes a solvent; about 1 weight percent (wt %) to about 40 wt % of a water-soluble polymer; and about 0.01 wt % to about 30 wt % of a nano light-emitting filler.
    Type: Application
    Filed: July 25, 2023
    Publication date: February 1, 2024
    Inventors: Woojung PARK, Mihyae PARK
  • Publication number: 20240038552
    Abstract: The present application discloses a wet clean apparatus for a single wafer, comprising: a baffle arranged on the periphery of the wafer bearing platform. The anti-splash structure comprises: a first vertical plate, wherein a length direction thereof is perpendicular to the surface of the wafer; a first opening transversely passing through the first vertical plate, wherein the first opening is arranged on a movement track of the etchant shaken off from the surface of the wafer; and a second transverse plate, wherein a first end thereof is fixedly arranged on the outer side surface of the first vertical plate, the top surface of the second transverse plate is horizontal and is lower than or flush with the bottom surface of the first opening, and the etchant passing through the first opening flows on the top surface of the second transverse plate and is decelerated.
    Type: Application
    Filed: March 21, 2023
    Publication date: February 1, 2024
    Applicant: Shanghai Huali Integrated Circuit Corporation
    Inventor: Wenqian XIE
  • Publication number: 20240038553
    Abstract: Semiconductor devices (e.g., GAA device structures) and processing methods and cluster tools for forming GAA device structures are described. The cluster tools for forming GAA device structures comprise a first etch chamber, a second etch chamber, and a third etch chamber. Each of the first etch chamber and the second etch chamber independently comprises a single-wafer chamber or an immersion chamber. One or more of the first etch chamber or the second etch chamber may be a wet etch chamber. In some embodiments, at least one of the first etch chamber, the second etch chamber, and the third etch chamber is a dry etch chamber. The cluster tool described herein advantageously reduces the number of cleaning processes, the total time between cleaning and processing operations, variations in time between processing and variation in sidewall loss compared to conventional cluster tools.
    Type: Application
    Filed: July 25, 2023
    Publication date: February 1, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Benjamin Colombeau, Balasubramanian Pranatharthiharan, Lequn Liu, Brian K. Kirkpatrick
  • Publication number: 20240038554
    Abstract: The EFEM comprises: a transfer chamber in which a transfer robot is disposed, a first fan that forms a downward air flow in the transfer chamber, a gas return space that circulates the gas flowing downward in the transfer chamber above the first fan, a box that communicates with the transfer chamber and is provided with a gas outlet, and a connecting and disconnecting means configured to switch connection and disconnection of the box to and from the transport chamber. A circulation path in which gas circulates is formed by the transfer chamber, the gas return space, and the box. When the transfer chamber and the box are separated by the connecting and disconnecting means, a shortened circulation path is formed in which the gas circulates without passing through the box.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicant: SINFONIA TECHNOLOGY CO., LTD.
    Inventors: Toshihiro Kawai, Takashi Shigeta, Munekazu Komiya, Yasushi Taniyama
  • Publication number: 20240038555
    Abstract: A system of processing a substrate includes substrate-processing chambers; target components of temperature control disposed in the respective substrate-processing chambers; a chiller to supply a first temperature-controlling medium with a first flow rate and a second temperature-controlling medium with a second flow rate into the target components; flow controllers connected to the respective target components, each flow controller being configured to independently control a ratio of the first flow rate to the second flow rate to be fed into the corresponding target component from the chiller.
    Type: Application
    Filed: October 3, 2023
    Publication date: February 1, 2024
    Inventors: Haruka Kaneko, Takehiko Arita, Hayato Sakai
  • Publication number: 20240038556
    Abstract: Methods for mitigating warpage on stacked wafers are provided herein. In one example, a method for mitigating warpage on stacked wafers includes depositing a first warpage compensating layer on a backside of a first wafer, stacking an active side of the first wafer on an active side of a second wafer to form a wafer stack having circuitry of the first wafer electrically connected to circuitry of the second wafer, and removing the first warpage compensating layer from the backside of the first wafer prior dicing the wafer stack.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Inventors: Myongseob KIM, Henley LIU, Cheang-whang CHANG
  • Publication number: 20240038557
    Abstract: Methods and apparatus for processing a substrate is provided herein. For example, the method comprises prior to processing a substrate, obtaining a first measurement at a first point along a surface of the substrate, in a process chamber processing the substrate in a presence of an electric field, subsequent to processing the substrate, obtaining a second measurement at the first point along the surface of the substrate, and determining whether substrate warpage occurred based upon analysis of the first measurement and the second measurement.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Yaoying ZHONG, Siew Kit HOI
  • Publication number: 20240038558
    Abstract: Methods and systems for determining information for a specimen are provided. One method includes generating a sampling plan for only out of specification detection of a characteristic of specimens in a metrology process. The method also includes generating output for the specimens by performing the metrology process on the specimens with the generated sampling plan. In addition, the method includes determining the characteristic of the specimen based on the generated output and detecting if the characteristic of one or more of the specimens is out of specification based on the determined characteristic of the specimens. The embodiments described herein are particularly suitable for overlay metrology with substantially sparse sampling plans configured for only out of specification detection of the overlay.
    Type: Application
    Filed: July 16, 2023
    Publication date: February 1, 2024
    Inventors: Fatima Anis, Irina Brinster
  • Publication number: 20240038559
    Abstract: A load port and a multi-use carrier are provided. The load port includes a carrying board, two gas-inlet nozzles disposed on the carrying board, and two gas-outlet nozzles disposed on the carrying board. Each of the two gas-inlet nozzles has a shared gas-inlet channel. Each of the two gas-outlet nozzles has a first gas-outlet channel and a second gas-outlet channel that is spaced apart from the first gas-outlet channel. The shared gas-inlet channels of the two gas-inlet nozzles are selectively cooperated with the first gas-outlet channels of the two gas-outlet nozzles so as to be jointly configured to spatially communicate with a first wafer cassette. The shared gas-inlet channels of the two gas-inlet nozzles are selectively cooperated with the second gas-outlet channels of the two gas-outlet nozzles so as to be jointly configured to spatially communicate with a second wafer cassette.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventor: YI-JUN GU
  • Publication number: 20240038560
    Abstract: A wafer boat according to an aspect of the present invention includes: at least one plate on which a plurality of wafers are loaded; and a plurality of pin pairs that are arranged along a first direction from the at least one plate and respectively support corresponding wafers among the plurality of wafers.
    Type: Application
    Filed: January 5, 2022
    Publication date: February 1, 2024
    Applicant: HANWHA SOLUTIONS CORPORATION
    Inventor: Kyoungsup SHIN
  • Publication number: 20240038561
    Abstract: A substrate storage container includes a container body configured to store a substrate, a lid that closes the opening of the container body, a retainer that is attached to the lid, and a substrate support portion formed in the retainer. The substrate support portion has an arc shape in a cross-sectional view from the top-to-bottom direction perpendicular to the closing direction of the lid. The substrate support portion includes a pair of left and right substrate support portions configured to hold the substrate together with the container body to retain the substrate.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Inventors: Osamu Ogawa, Seiya Nakarai
  • Publication number: 20240038562
    Abstract: A gas-inlet module and a gas-inlet nozzle are provided. The gas-inlet has a first gas-inlet channel and a second gas-inlet channel. The first gas-inlet channel has a first end opening, the second gas-inlet channel has a second end opening, and a distance between a center point of the first end opening and a center point of the second end opening is defined as an offset distance. A value defined by an inner radius of the first end opening or an inner radius of the second end opening divided by the offset distance is within a range from 1/7 to 5/7.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventor: YI-JUN GU
  • Publication number: 20240038563
    Abstract: A substrate transfer device includes a housing accommodating a carrier for storing a substrate, a carrier lifter moving the carrier in a vertical direction relative to an upper surface of the housing, a vertical stabilization unit connected to a lower part of the carrier lifter and reducing a vertical vibration of the carrier, a rotation stabilization unit connected to a lower part of the vertical stabilization unit and reducing rotation of the carrier, and a carrier holder connected to a lower part of the rotation stabilization unit. The carrier holder holds the carrier. The vertical stabilization unit includes an upper plate connected to the carrier lifter, a lower plate connected to the rotation stabilization unit, and a buffer disposed between the upper plate and the lower plate. The buffer contracts or relaxes to reduce the vertical vibration of the carrier.
    Type: Application
    Filed: April 25, 2023
    Publication date: February 1, 2024
    Inventors: Jun Kyu LEE, Hongjin KIM, Jeongjae BANG
  • Publication number: 20240038564
    Abstract: An apparatus for executing a direct transfer of a semiconductor device die from a first substrate to a second substrate. The apparatus includes a first substrate conveyance mechanism movable in two axes. A micro-adjustment mechanism is coupled with the first substrate conveyance mechanism and is configured to hold the first substrate and to make positional adjustments on a scale smaller than positional adjustments caused by the first substrate conveyance mechanism. The micro-adjustment mechanism includes a micro-adjustment actuator having a distal end and a first substrate holder frame that is movable via contact with the distal end of the micro-adjustment actuator. A second frame is configured to secure the second substrate such that a transfer surface is disposed facing the semiconductor device die disposed on a surface of the first substrate. A transfer mechanism is configured to press the semiconductor device die into contact with the transfer surface of the substrate.
    Type: Application
    Filed: August 14, 2023
    Publication date: February 1, 2024
    Inventors: Andrew Huska, Justin Wendt, Luke Dupin, Cody Peterson
  • Publication number: 20240038565
    Abstract: A centering device has three or more contact members each having a contact surface capable of contacting an end face of a substrate supported by a substrate support. These contact members are arranged to surround the substrate support in a horizontal plane with the contact surfaces facing an end face of the substrate. These contact members move toward the substrate in the mutually different directions to sandwich the substrate. Each contact surface is finished such that a contactable region formed to intersect the horizontal plane has a linear shape or a curved shape having a center of curvature located on the substrate side and having the radius of curvature larger than the radius of the substrate and is longer than an arc formed by cutting out the circumference of the substrate by the cut.
    Type: Application
    Filed: June 23, 2023
    Publication date: February 1, 2024
    Inventors: Itsuki KAJINO, Shoyo Minami
  • Publication number: 20240038566
    Abstract: A substrate processing apparatus is provided. The substrate processing apparatus includes: a chuck member; a ceramic puck disposed on the chuck member; a focus ring disposed to surround the ceramic puck; an insulating layer disposed below the focus ring to surround the chuck member; and two electrodes formed in the insulating layer, wherein a distance between the two electrodes is adjustable to form a variable capacitance.
    Type: Application
    Filed: December 26, 2022
    Publication date: February 1, 2024
    Inventors: Jong Gun LEE, Hyung Joon Kim
  • Publication number: 20240038567
    Abstract: A member for a semiconductor manufacturing apparatus, includes: a ceramic plate that has a ceramic plate through hole; an electroconductive base plate that has a base plate through hole and that is disposed on a lower surface side of the ceramic plate; an insulating sleeve which is inserted into the base plate through hole and of which an outer peripheral surface is adhered to an inner peripheral surface of the base plate through hole via an adhesion layer; and a sleeve through hole that passes through the insulating sleeve in the up-down direction and that communicates with the ceramic plate through hole. The insulating sleeve has a tool engaging portion that is engageable with an external tool, and upon being engaged with the external tool, the tool engaging portion transmits rotation torque of the external tool to the insulating sleeve.
    Type: Application
    Filed: February 16, 2023
    Publication date: February 1, 2024
    Applicant: NGK Insulators, Ltd.
    Inventors: Seiya INOUE, Tatsuya KUNO, Natsuki HIRATA, Kenji YONEMOTO
  • Publication number: 20240038568
    Abstract: A semiconductor substrate processing apparatus includes a vacuum chamber having a processing zone in which a semiconductor substrate may be processed, a process gas source in fluid communication with the vacuum chamber for supplying a process gas into the vacuum chamber, a showerhead module through which process gas from the process gas source is supplied to the processing zone of the vacuum chamber, and a substrate pedestal module.
    Type: Application
    Filed: October 5, 2023
    Publication date: February 1, 2024
    Inventor: Troy Alan GOMM
  • Publication number: 20240038569
    Abstract: A micro device, a micro device alignment apparatus, and an alignment method using the same are proposed. In a micro device that has to be aligned with at least any one surface of front and rear surfaces of the micro device when mounted on a substrate and simultaneously be aligned with any one direction of the micro device when mounted on the substrate, there is provided the micro device, the micro device alignment apparatus, and the alignment method using the same so that surface alignment and direction alignment are simultaneously performed for a plurality of micro devices that is not aligned with at least any one surface of the front and rear surfaces and simultaneously is not aligned with any one direction.
    Type: Application
    Filed: December 8, 2021
    Publication date: February 1, 2024
    Applicant: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo AHN, Seung Ho PARK, Jeong Hyuk LEE
  • Publication number: 20240038570
    Abstract: A stamp for micro-transfer printing includes a support having a support surface and posts disposed on the support surface. Each post has a proximal end in contact with the support and a distal end extending away from the support. The post has a post surface on the distal end. The post surface is a structured surface comprising spatially separated ridges that extend in a ridge direction entirely across the post surface and can be operable to form multiple delamination fronts when a first side of a micro-device is in contact with the post surface, a second side of the micro-device is in contact with a target surface of a target substrate, and the support is moved in a horizontal direction parallel to the target substrate surface. The post surface or ridges can be rectangular or non-rectangular with opposing edges having different lengths.
    Type: Application
    Filed: October 10, 2023
    Publication date: February 1, 2024
    Applicant: X-Celeprint Limited
    Inventors: Ken G. Purchase, Ronald S. Cok
  • Publication number: 20240038571
    Abstract: At least one embodiment, a vacuum chuck includes a moisture gate structure that allows for moisture to escape to reduce an amount of warpage in a workpiece when present on the vacuum chuck. The moisture gate structure includes a base portion that extends laterally outward from a central vacuum portion of the vacuum chuck, and a plurality of protrusions are spaced apart from the central vacuum portion and extend outward from the base portion. End surfaces of the plurality of protrusions contact a backside surface of the workpiece (e.g., a wafer on a carrier) when the workpiece is present on the vacuum chuck. The vacuum chuck may further include one or more guide portions that act as guides such that the workpiece remains properly aligned and within position when present on the vacuum chuck.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Po-Yo SU, Young-Wei LIN, Yu Liang HUANG, Chia-Ching LEE, Chi-Chun PENG, Chen Liang CHANG, Kuo Hui CHANG
  • Publication number: 20240038572
    Abstract: Aspects of the present disclosure relate to a pick-and-place apparatus that is configured to cause components to be placed on a substrate in a number of passes, and during each pass, components among a plurality of components are placed on the substrate in a respective placement pattern among a collection of interleaved placement patterns.
    Type: Application
    Filed: July 21, 2023
    Publication date: February 1, 2024
    Applicant: NEXPERIA B.V.
    Inventors: Steven Verstoep, Niels de Koning, Tim Ellenbroek
  • Publication number: 20240038573
    Abstract: A wafer processing apparatus includes a rotating chuck rotatably installed on a driver, a vacuum chuck which is disposed on the rotating chuck and on which a wafer is seated, a chuck module installed in the rotating chuck to fix the wafer to the vacuum chuck, and a moving module configured to move the vacuum chuck or the chuck module to increase a gap between adjacent dies of the wafer.
    Type: Application
    Filed: October 10, 2023
    Publication date: February 1, 2024
    Applicant: ZEUS CO., LTD.
    Inventors: Woon Kong, Ji Hoon SONG, Ung Jo MOON, Ji Ho PARK, Won Seok CHOI
  • Publication number: 20240038574
    Abstract: A transfer system includes first and second optical energy sources operable to provide a respective first and second optical energy at respective first and second wavelengths. A chiplet has a bonding feature configured to interface with a corresponding bonding feature of a target substrate. At least one of the bonding features absorb at the first wavelength such that applying the first optical energy bonds the chiplet to the target substrate or removes a bond between the chiplet and the target substrate. The system includes a transfer layer formed of a thermally switchable material that undergoes a phase change when heated. An optical absorber absorbs at the second wavelength such that applying the second optical energy heats a region of the transfer layer at a location of the chiplet when removing the chiplets from a source substrate during the transfer operation.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Christopher L. Chua, Ching-Fuh Lin, Zhihong Yang
  • Publication number: 20240038575
    Abstract: Embodiments described herein relate to a susceptor kit. The susceptor kit includes a susceptor support plate including a plurality of susceptor lift pin holes and a plurality of susceptor support holes, a plurality of susceptor supports recessed within the plurality of susceptor support holes and coupled to the susceptor support plate, and a lift pin assembly. The plurality of susceptor supports receive a plurality of susceptor support pins. The support body supports the support pin link in a spaced apart relation to the susceptor support plate. The lift pin assembly is received in the plurality of susceptor lift pin holes. The lift pin assembly includes a lift pin cap and a susceptor lift pin comprising a susceptor stop plate. The susceptor support plate stop is receivable within the susceptor lift pin holes.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Inventors: Zhepeng CONG, Ashur J. ATANOS, Nimrod SMITH, Richard O. COLLINS
  • Publication number: 20240038576
    Abstract: Described herein is a technique capable of forming a film on a substrate with good uniformity. According to one aspect of the technique of the present disclosure, there is provided a method of manufacturing a semiconductor device including: processing a substrate by performing a cycle a predetermined number of times, the cycle comprising: (a) supplying a source gas; (b) discharging at least the source gas; (c) supplying a reactive gas; and (d) discharging at least the reactive gas. The substrate is kept stationary while each cycle is performed, and a rotation angle of rotating the substrate is calculated based on the predetermined number of times after each cycle is completed.
    Type: Application
    Filed: October 13, 2023
    Publication date: February 1, 2024
    Inventor: Daigi KAMIMURA
  • Publication number: 20240038577
    Abstract: Methods, systems, and devices for isolation regions within a memory die are described. During fabrication, memory pillars may be formed through a stack of material in a plurality regions of a memory die. In some cases, a first plurality of trenches extending in a first direction and a second plurality of trenches extending in a second direction may be formed through the stack of material (e.g., interposed between the plurality of regions). Additionally or alternatively, first voids may be formed via the first plurality of trenches, and a dielectric material may be deposited in the first voids and the first plurality of trenches, forming first isolation regions. Then, second voids may be formed via the second plurality of trenches, and a dielectric material may be deposited in the second voids and the second plurality of trenches, forming second isolation regions.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: Raja Kumar Varma Manthena, Yoshiaki Fukuzumi
  • Publication number: 20240038578
    Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. An insulating structure is directly adjacent sidewalls of the lower fin portion of the fin. A first gate electrode is over the upper fin portion and over a first portion of the insulating structure. A second gate electrode is over the upper fin portion and over a second portion of the insulating structure. A first dielectric spacer is along a sidewall of the first gate electrode. A second dielectric spacer is along a sidewall of the second gate electrode, the second dielectric spacer continuous with the first dielectric spacer over a third portion of the insulating structure between the first gate electrode and the second gate electrode.
    Type: Application
    Filed: October 4, 2023
    Publication date: February 1, 2024
    Inventors: Heidi M. MEYER, Ahmet TURA, Byron HO, Subhash JOSHI, Michael L. HATTENDORF, Christopher P. AUTH
  • Publication number: 20240038579
    Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, as well as a buried layer, a deep trench structure and a shallow trench isolation structure, the semiconductor surface layer over the semiconductor substrate and having a top surface, the buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, the deep trench structure including a trench that extends through the semiconductor surface layer and into the buried layer, a dielectric liner on a sidewall of the trench from the semiconductor surface layer to the buried layer, and polysilicon that extends on the dielectric liner and fills the trench to the side of the semiconductor surface layer, the shallow trench isolation structure extends into the semiconductor surface layer, and the shallow trench isolation structure in contact with the deep trench structure.
    Type: Application
    Filed: July 31, 2022
    Publication date: February 1, 2024
    Inventors: Asad Haider, Hao Yang, Guruvayurappan Mathur, Alexei Sadovnikov, Abbas Ali, Umamaheswari Aghoram
  • Publication number: 20240038580
    Abstract: An electronic device includes a semiconductor substrate and a semiconductor surface layer having a first conductivity type, the semiconductor surface layer over the semiconductor substrate and having a top surface, a buried layer having an opposite second conductivity type between the semiconductor surface layer and the semiconductor substrate, a dielectric isolation layer that extends over and into the semiconductor surface layer, a deep trench structure that extends through the dielectric isolation layer into the semiconductor surface layer, and a silicide blocking layer on a top surface of the deep trench structure.
    Type: Application
    Filed: July 31, 2022
    Publication date: February 1, 2024
    Inventors: Hao Yang, Asad Haider, Guruvayurappan Mathur, Abbas Ali, Alexei Sadovnikov, Umamaheswari Aghoram
  • Publication number: 20240038581
    Abstract: A SOI wafer is formed by forming a hole array on a surface of a wafer including a semiconductor material, forming a membrane-cavity structure by annealing process on the wafer, forming a buried oxide layer on an inside of the cavity and an outer oxide layer on an outside of the membrane, and forming a device layer by removing the outer oxide layer.
    Type: Application
    Filed: July 17, 2023
    Publication date: February 1, 2024
    Applicant: Korea Advanced Institute of Science and Technology
    Inventor: Jungchul LEE
  • Publication number: 20240038582
    Abstract: The present disclosure relates to a fabricating procedure of a radio frequency device, in which a precursor wafer including active layers, SiGe layers, and a silicon handle substrate is firstly provided. Each active layer is formed from doped epitaxial silicon and underneath a corresponding SiGe layer. The silicon handle substrate is over each SiGe layer. Next, the silicon handle substrate is removed completely, and the SiGe layer is removed completely. An etch passivation film is then formed over each active layer. Herein, removing each SiGe layer and forming the etch passivation film over each active layer utilizes a same reactive chemistry combination, which reacts differently to the SiGe layer and the active layer. The reactive chemistry combination is capable of producing a variable performance, which is an etching performance of the SiGe layer or a forming performance of the etch passivation film over the active layer.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Inventors: Krishna Chetry, Ganesan Radhakrishnan
  • Publication number: 20240038583
    Abstract: A semiconductor device includes a stack structure including conductive patterns spaced apart from each other, a channel structure penetrating the stack structure, and a slit insulating layer penetrating the stack structure. Air gaps are defined between the conductive patterns. The slit insulating layer includes a first interposition part covering a sidewall of one of the conductive patterns and a second interposition part covering one of the air gaps from the side. A smallest width of the second interposition part is smaller than a smallest width of the first interposition part.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Applicant: SK hynix Inc.
    Inventors: In Ku KANG, Sung Hyun YOON
  • Publication number: 20240038584
    Abstract: A method for manufacturing a semiconductor device. A photolithographic coating, including a first film, a photolithographic film, and a second film, is formed on the to-be-connected structure. Refractive indexes of the first film and the second film are smaller than 1. The photolithographic coating is exposed to a light having a first wavelength, to image the to-be-connected structure to a first region of the photolithographic film. The photolithographic coating is exposed to a light having a second wavelength through a mask, to image the mask to a second region of the photolithographic film. A region in which the first region and the second region overlap serves as a connection region corresponding to the to-be-connected structure, and thereby self-alignment between a layer of the to-be-connected structure and a layer where a contact hole is arranged is implemented.
    Type: Application
    Filed: November 12, 2021
    Publication date: February 1, 2024
    Inventors: Libin Zhang, Yayi Wei, Zhen Song
  • Publication number: 20240038585
    Abstract: The present disclosure provides a method for preparing metal lines with a high aspect ratio including two photolithography stages. According to the design of the method of the present disclosure, first metal lines with high aspect ratio are formed in a dielectric layer, which provides a mechanical support to the first metal lines, thereby preventing the first metal lines from collapsing or deforming. Because of a significant reduction or elimination of collapse or deformation phenomenon in the semiconductor structure, a problem associated with short circuits due to direct contact between the semiconductor components is mitigated, and reliability of the semiconductor structures is enhanced. As a result, a yield of the semiconductor structure is increased.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Inventor: CHIH-WEI HUANG
  • Publication number: 20240038586
    Abstract: A semiconductor structure includes a base structure, a plurality of electrically conductive features disposed on the base structure, and an isolation structure disposed on the base structure. The base structure includes a substrate. The electrically conductive features are spaced apart from each other. The isolation structure includes a first inter-metal dielectric feature extending horizontally to interconnect the electrically conductive features, a first air gap layer disposed in the isolation structure and around the electrically conductive features, and a first sustaining feature extending horizontally to interconnect the electrically conductive features and disposed between the first inter-metal dielectric feature and the first air gap layer. Methods for manufacturing the semiconductor structure are also disclosed.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kai-Fang CHENG, Hsiao-Kang CHANG
  • Publication number: 20240038587
    Abstract: A semiconductor substrate includes a plurality of transistors. A first structure is disposed over a first side of the semiconductor substrate. The first structure contains a plurality of first metallization components. A carrier substrate is disposed over the first structure. The first structure is located between the carrier substrate and the semiconductor substrate. One or more openings extend through the carrier substrate and expose one or more regions of the first structure to the first side. A second structure is disposed over a second side of the semiconductor substrate opposite the first side. The second structure contains a plurality of second metallization components.
    Type: Application
    Filed: March 30, 2023
    Publication date: February 1, 2024
    Inventors: Kao-Chih Liu, Wenmin Hsu, Hsuan Jung Chiu, Yu-Ting Lin, Chia Hong Lin
  • Publication number: 20240038588
    Abstract: A method of forming a microelectronic device comprises forming interlayer dielectric material over a base structure comprising semiconductive structures separated from one another by insulative structures. Sacrificial line structures separated from one another by trenches are formed over the interlayer dielectric material. The sacrificial line structures horizontally overlap some of the semiconductive structures, and the trenches horizontally overlap some other of the semiconductive structures. Plug structures are formed within horizontal areas of the trenches and extend through the interlayer dielectric material and into the some other of the semiconductive structures. The sacrificial line structures are replaced with additional trenches. Conductive contact structures are formed within horizontal areas of the additional trenches and extend through the interlayer dielectric material and into the some of the semiconductive structures.
    Type: Application
    Filed: July 27, 2022
    Publication date: February 1, 2024
    Inventors: Terrence B. McDaniel, Vinay Nair, Russell A. Benson, Christopher W. Petz, Si-Woo Lee, Silvia Borsari, Ping Chieh Chiang, Luca Fumagalli
  • Publication number: 20240038589
    Abstract: A method for forming a superconducting interconnect structure, comprising: providing a substrate, forming a superconductive layer, forming a layer of a first dielectric material, removing parts of the layer of the first dielectric material and of the superconductive layer so as to form a pattern comprising a first set of line structures comprising: a first set of superconductive line structures, and a first set of line structures made of the first dielectric material, forming a second dielectric material between the line structures of the first set, forming a layer formed of a third dielectric material, providing a patterned mask, transferring the pattern into the first dielectric material and into the layer formed of the third dielectric material, so as to form the at least one via hole, removing the patterned mask, and forming a superconductive material layer so as to form at least one via.
    Type: Application
    Filed: July 29, 2022
    Publication date: February 1, 2024
    Inventors: Anna Yurievna HERR, Quentin Paul HERR, Zsolt TOKEI, Anshul GUPTA
  • Publication number: 20240038590
    Abstract: A semiconductor device includes a semiconductor substrate having a quadrangular shape when viewed from above and having a front surface, a rear surface opposite to the front surface, and four side surfaces connecting the front surface and the rear surface. Each of the side surfaces has a step section in which a plurality of protruding portions and a plurality of recessed portions alternately and repeatedly appear along a direction in which a peripheral edge of the front surface of the semiconductor substrate extends.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Inventors: MASASHI UECHA, YUJI NAGUMO, MASARU OKUDA, MASATAKE NAGAYA, MITSURU KITAICHI, AKIRA MORI, NAOYA KIYAMA, MASAKAZU TAKEDA
  • Publication number: 20240038591
    Abstract: A lift-off method includes joining a transfer substrate to a face side of an optical device layer of an optical device wafer with a joining member interposed therebetween, thereby making up a composite substrate, applying a pulsed laser beam having a wavelength transmittable through the epitaxy substrate and absorbable by a buffer layer, from a reverse side of the epitaxy substrate of the optical device wafer, thereby breaking the buffer layer, and an optical device layer transferring step of peeling off the epitaxy substrate from the optical device layer and transferring the optical device layer to the transfer substrate. The optical device layer transferring step includes the step of applying a bending moment to an area of the composite substrate that includes an outer peripheral portion thereof while holding an area of the composite substrate that includes a central portion thereof.
    Type: Application
    Filed: July 26, 2023
    Publication date: February 1, 2024
    Inventors: Masato TERAJIMA, Junya MIMURA, Tasuku KOYANAGI, Hiroshi MORIKAZU, Yuki SUTO
  • Publication number: 20240038592
    Abstract: Non-planar I/O and logic semiconductor devices having different workfunctions on common substrates and methods of fabricating non-planar I/O and logic semiconductor devices having different workfunctions on common substrates are described. For example, a semiconductor structure includes a first semiconductor device disposed above a substrate. The first semiconductor device has a conductivity type and includes a gate electrode having a first workfunction. The semiconductor structure also includes a second semiconductor device disposed above the substrate. The second semiconductor device has the conductivity type and includes a gate electrode having a second, different, workfunction.
    Type: Application
    Filed: October 11, 2023
    Publication date: February 1, 2024
    Inventors: Roman W. OLAC-VAW, Walid M. HAFEZ, Chia-Hong JAN, Pei-Chi LIU
  • Publication number: 20240038593
    Abstract: A method includes forming first and second fins disposed on a substrate, forming a gate structure over the first and second fins, epitaxially growing a first source/drain (S/D) feature on the first fin and a second S/D feature on the second fin, depositing a dielectric layer covering the first and second S/D features, etching the dielectric layer to form a trench exposing the first and second S/D features, forming a metal structure in the trench and extending from the first S/D feature to the second S/D feature, performing a cut metal process to form an opening dividing the metal structure into a first segment over the first S/D feature and a second segment over the second S/D feature, and depositing an isolation feature in the opening. The isolation feature separates the first segment from the second segment.
    Type: Application
    Filed: June 13, 2023
    Publication date: February 1, 2024
    Inventors: Chung-Hao Cai, Chia-Hsien Yao, Yen-Jun Huang, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20240038594
    Abstract: FinFET devices and processes to prevent fin or gate collapse (e.g., flopover) in finFET devices are provided. The method includes forming a first set of trenches in a semiconductor material and filling the first set of trenches with insulator material. The method further includes forming a second set of trenches in the semiconductor material, alternating with the first set of trenches that are filled. The second set of trenches form semiconductor structures which have a dimension of fin structures. The method further includes filling the second set of trenches with insulator material. The method further includes recessing the insulator material within the first set of trenches and the second set of trenches to form the fin structures.
    Type: Application
    Filed: February 28, 2023
    Publication date: February 1, 2024
    Inventors: Veeraraghavan S. Basker, Kangguo Cheng, Theodorus E. Standaert, Junli Wang
  • Publication number: 20240038595
    Abstract: A method for manufacturing a semiconductor device is provided. The method includes forming a first transistor over a substrate, wherein the first transistor comprises a first source/drain feature; depositing an interlayer dielectric layer around the first transistor; etching an opening in the interlayer dielectric layer to expose the first source/drain feature; conformably depositing a semimetal layer over the interlayer dielectric layer, wherein the semimetal layer has a first portion in the opening in the interlayer dielectric layer and a second portion over a top surface of the interlayer dielectric layer; and forming a source/drain contact in the opening in the interlayer dielectric layer.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuan-Kan HU, Jhih-Rong HUANG, Yi-Bo LIAO, Shuen-Shin LIANG, Min-Chiang CHUANG, Sung-Li WANG, Wei-Yen WOON, Szuya LIAO
  • Publication number: 20240038596
    Abstract: An apparatus and method for efficiently increasing semiconductor chip functionality in a particular area. A semiconductor fabrication process (or process) grows a silicon substrate layer, and forms multiple p-type and n-type transistors along a front side surface of the silicon substrate layer. The process flips the silicon substrate layer and removes silicon substrate leaving a particular thickness of the silicon substrate layer. The process forms multiple p-type and n-type transistors along the back side surface of the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the back side surface to particular signals. The process forms through silicon vias (TSVs) that traverse through the silicon substrate layer. The process again flips the silicon substrate layer, and forms metal layers that connect terminals of the transistors formed along the front side surface to particular signals.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Inventors: Chandra Sekhar Mandalapu, Rahul Agarwal, Rajasekaran Swaminathan, Richard T. Schultz
  • Publication number: 20240038597
    Abstract: A method and a system for detecting a semiconductor device are provided. The method comprises obtaining an image of the semiconductor device, evaluating a feature of the image, detecting a defect of the semiconductor device based on the feature, extracting a defect information for the defect, calculating a defect die ratio (DDR) in response to the defect and analyzing a relation between the DDR and the defect information.
    Type: Application
    Filed: July 28, 2022
    Publication date: February 1, 2024
    Inventors: FAN HU, WEN-CHUAN TAI, HSIANG-FU CHEN, I-CHIEH HUANG, TZU-CHIEH WEI, KANG-YI LIEN