Abstract: The present invention provides a bonding apparatus for bonding, to a first member including a first bonding surface on which a first pattern is provided, a second member including a second bonding surface on which a second pattern is provided, comprising: a first image capturing device configured to capture an image of the first bonding surface; a second image capturing device configured to capture an image of the second bonding surface; and a controller configured to control a bonding process of aligning the first member and the second member based on a position of the first pattern obtained from the captured image by the first image capturing device and a position of the second pattern obtained from the captured image by the second image capturing device, and bonding the second member to the first member.

Abstract: Semiconductor devices and corresponding methods of manufacturing the same are disclosed. For example, a semiconductor device includes a first semiconductor substrate and a second semiconductor substrate. A first portion of a test structure is disposed over the first substrate and a second portion of the test structure is disposed over the second substrate. The test structure includes intentionally offset portions. The performance characteristics of the intestinally offset portions are measured to detect an alignment of the first portion of the test structure and a second portion of the test structure.

Abstract: A measuring method and device based on the second harmonic for the whole area measurement of a wafer comprises three modes: a fixed-point measurement, a scanning measurement, and a combination of the fixed-point measurement and the scanning measurement. The scanning measurement solution measures the entire wafer under the premise of ensuring high measurement efficiency, obtain the position, size and relative density distribution of electrical defects, and achieve locating and checking of abnormal points on the wafer. A new formula system is provided for describing the second harmonic signal, so that the actual measurement results and the theoretical model are unified under the three modes of the fixed-point measurement, the scanning measurement, and the combination of fixed-point measurement and scanning measurement, so that the second harmonic metrology technology is no longer only a qualitative analysis method, but also a quantitative analysis method.

Abstract: An electronic device manufacturing system including a substrate-holder configured to secure a substrate during processing and a controller, operatively coupled to the substrate-holder. The controller is configured to apply, to an electrode of the substrate-holder, a first voltage. The controller is further configured to determine a first impedance value between the substrate-holder and the substrate. The controller is further configured to determine a delta value between the first impedance value and a predetermined second impedance value, and determine whether the delta value satisfies a threshold criterion. Responsive to the delta value failing to satisfy the threshold criterion, the controller is further configured to apply a second voltage to the substrate, wherein the second voltage is greater than the first voltage.

Abstract: An I/O sensor including: a programmable delay line; a delayed sampling device having the following inputs: (a) a data signal that also serves as an input to a reference clocked receiver that is configured to sample the data signal received from an interconnect lane between two integrated circuits (ICs) of a multi-IC module, and (b) a delayed clock signal received from the programmable delay line, wherein the delayed clock signal is a delayed version of a clock signal that clocks the reference clocked receiver; a comparison circuits configured to compare a data signal output of the delayed sampling device and a data signal output of the reference clocked receiver; and a controller configured, based on a comparison result of the comparison circuit and on the amount of delay that caused it, to estimate a quality of connectivity between the two ICs over the interconnect lane.

Abstract: A semiconductor chip including a guard ring that surrounds edges of a semiconductor substrate, an internal circuit structure that is formed on the semiconductor substrate and that includes a memory cell array region and a peripheral circuit region, and a crack detection circuit that is located between the guard ring and the internal circuit structure and that detects whether a crack occurs. The semiconductor chip further includes first to fourth chamfer regions having different shapes and sizes depending on the position of a pad or the design arrangement of the internal circuit structure.

Abstract: A semiconductor chip has a top metal layer with a passivation over an outer surface and including a first region and a second region. The passivation is fully removed from the first region and a contact layer for electrical wafer sorting probes is formed over the first region having the passivation fully removed therefrom. The passivation is initially only partly removed from the second region to protect the top met layer. Later, a remaining portion of the passivation is fully removed at the second region. Then, top metal layer at the second region provides a growth region for growing electrically conductive material over the second region.

Abstract: A testline structure of a semiconductor device includes a substrate layer, a frontside insulating layer atop the substrate layer, a backside insulating layer under the substrate layer, and a probe pad structure vertically extending through the frontside insulating layer, the substrate layer, and the backside insulating layer. The probe pad structure includes a frontside probe pad in the frontside insulating layer and a backside probe pad in the backside insulating layer.

Abstract: In one example, a semiconductor device comprises a substrate comprising a conductive structure, an electronic component over a top side of the substrate and electrically coupled with the conductive structure, a lid structure over the substrate and over the electronic component, and a vertical interconnect in the lid structure extending to a top surface of the lid structure and electrically coupled with the conductive structure. Other examples and related methods are also disclosed herein.

Abstract: An integrated circuit package includes a cavity within which a circuit device is contained. At least one through hole is provided in at least one wall of the cavity. The at least one through hole includes at least one first portion flaring towards the cavity with a frustoconical shape, for example.

Abstract: Semiconductor packages with cavities and methods of making such semiconductor packages are described. The semiconductor package includes a semiconductor die including an interface region where various components configured to interact with an environment surrounding the package can be located. Such components include a humidity sensor, a temperature sensor, a light emitting diode, a solid-state laser, a photodiode, or the like. The semiconductor package includes an opening above the interface region to facilitate proper and adequate operations of the components. The semiconductor package also includes a polymer structure surrounding the interface region, thereby forming the opening. The polymer structure has an uneven inner sidewall profile formed by multiple layers of a polymer material.

Abstract: In some examples, a semiconductor package comprises a semiconductor die; an operational component on an active surface of the semiconductor die; and a cover coupled to the active surface of the semiconductor die and covering the operational component. The cover comprises a monolithic structure including a vertical portion and a horizontal portion. A hollow area is between the cover and the operational component. The package also includes a mold compound covering the semiconductor die and the cover.

Abstract: A method of manufacturing a semiconductor package with an one or more dice present within a transparent resin, which may be an epoxy-based transparent resin or a silicone-based transparent resin, includes coupling the one or more dice to respective surfaces of a plurality of base portions of a panel substrate. Each one of the respective surfaces is between ones of a plurality of walls of the panel substrate that protrude from the respective surfaces of the panel substrate. A plurality of wirebonds may be formed to provide electrical pathways between the one or more dice and conductive structures of the panel substrate accessible at the respective surfaces of the panel substrate. A transparent resin may be formed to fill recesses or cavities between ones of the plurality of walls, and the panel substrate may then be singulated along the plurality of walls.

Abstract: An electrical circuit body includes a power semiconductor element joined to one face of a conductor plate, a sheet member including an insulating layer joined to the other face of the conductor plate, a sealing member integrally sealing the sheet member, the conductor plate, and the power semiconductor element in a state where a face, of the sheet member, opposite to a face joined to the conductor plate is exposed, and a cooling member bonded to the opposite face of the sheet member via a heat conduction member, wherein the sealing member has a recess along an outer edge of the sheet member on a surface where the sheet member is exposed, the recess being located outside the sheet member.

Abstract: A package is disclosed. In one example, the package includes a first main face for mounting a heat sink and an opposing second main face for being mounted on a mounting base. The package comprises a carrier, an electronic component mounted at the carrier, and an encapsulant encapsulating at least part of the electronic component and at least part of the carrier. Electrically insulating material covers electrically conductive material of the carrier at said first main face. The encapsulant comprises at least one step at the first main face.

Abstract: Novel tools and techniques are provided for implementing edge seal for bonded stacks of different size semiconductor devices. In various embodiments, a semiconductor device is provided that includes a composite structure and a sealant material. The composite structure includes two or more semiconductor devices that form a stacked configuration with one semiconductor device being disposed on or over each of one or more other semiconductor devices (of different size compared with that of the one semiconductor device) and with interface components of the one semiconductor device being bonded with corresponding interface components to each of the one or more other semiconductor devices in the stacked configuration. The sealant material is disposed along one or more surface portions of the composite structure to cover a region including at least portions of side surfaces of the composite structure that extend to cover at least each interface portion between stacked semiconductor devices.

Abstract: A semiconductor package structure includes a substrate, a dummy conductive mesh structure, an interposer, an underfill material, and a semiconductor die. The substrate includes a wiring structure in dielectric layers. The dummy conductive mesh structure is embedded in the substrate and is spaced apart from the wiring structure by the dielectric layers. The interposer is disposed over the substrate. The underfill material extends between the substrate and the interposer and over the dummy conductive mesh structure. The semiconductor die is disposed over the interposer and is electrically coupled to the wiring structure through the interposer.

Abstract: A package, and method for building the package is disclosed. The package includes a substrate having a first surface. The package further includes a die having opposing first and second surfaces, and a lateral surface, with the second surface of the die coupled to the first surface of the substrate. The package further includes a stiffener element having a first surface and a lateral surface, with the first surface of the stiffener element coupled to the first surface of the substrate. The package further includes molding material disposed on the first surface of the substrate and the lateral surface of the die. The coefficient of thermal expansion (CTE) value of the molding material is greater than a CTE value of the die. The first molding surface of the molding material is coplanar with the first surface of the die.

Abstract: Disclosed are a semiconductor package and a manufacturing method of a semiconductor package. In one embodiment, the semiconductor package includes an interposer substrate, a plurality of semiconductor dies, a first encapsulant, at least one heat dissipation element and a second encapsulant. The plurality of semiconductor dies are disposed on the interposer substrate. The first encapsulant is disposed on the interposer substrate and surrounds the plurality of semiconductor dies. The at least one heat dissipation element is disposed on the plurality of semiconductor dies. The second encapsulant is disposed on the first encapsulant and surrounds the at least one heat dissipation element.

Abstract: A package structure includes a substrate, a semiconductor package disposed over the substrate, a first lid structure disposed over the substrate, and a second lid structure disposed over the semiconductor package and the first lid structure. The first lid structure includes an opening exposing a region of the semiconductor package. A thermal interface material is disposed between the second lid structure and the semiconductor package, and a phase change adhesive is disposed between the second lid structure and the first lid structure.

Abstract: A semiconductor module includes a semiconductor element having a first side in contact with a first substrate in a planar manner, and a second side which faces away from the first side and contacts a metallic heat sink in a planar manner. The heat sink is in thermally conductive connection with the semiconductor element and connected to the second substrate in an electrically conductive manner. The heat sink includes a main body for planar contacting of the semiconductor element and a fin arranged in a recess of the second substrate. The second substrate is connected in an electrically conductive manner to the main body which has a circumferential contact surface around the fin to establish a material-bonded connection with a substrate metallization of the second substrate. The circumferential contact surface is arranged on a side of the main body facing away from the semiconductor element.

Abstract: An electronic device includes an embedded die frame having a cavity and a routing structure, a semiconductor die in the cavity with a gallium nitride layer on the routing structure, and a heat spreader having a thermally conductive insulator layer and a metal plate, the thermally conductive insulator layer having a first side that faces the embedded die frame and an opposite second side that faces away from the embedded die frame, with a portion of the first side of the thermally conductive insulator layer extending over a side of a silicon substrate of the semiconductor die, and the metal plate on the second side of the thermally conductive insulator layer.

Abstract: A pin fin placement assembly utilized to form pin fins in a thermal dissipating feature is provided. The pin fin placement assembly may place the pin fins on an IC die disposed in the IC package. The pin fin placement assembly may assist massively placing the pin fins with desired profiles and numbers on desired locations of the IC die. The plurality of pin fins is formed in a first plurality of apertures in the pin fin placement assembly. A thermal process is then performed to solder the plurality of pin fins on the IC die.

Abstract: Various embodiments of the teachings herein include an apparatus comprising: a component; a cooling element; and a connecting element arranged between the component and the cooling element to thermally couple the cooling element to the component. The connecting element comprises a porous connecting body including a metal material. Pores of the connecting body are at least in part filled with a filling material including a low-melting alloy or a fluorinated organic liquid.

Abstract: A heat radiation component radiates heat from a GPU that generates heat, and includes a mesh impregnated with a liquid metal, and two film bodies that cover both surfaces of the mesh and have sealed peripheries. An opening is formed in the film body. In the mesh, an exposed portion that is exposed through the opening abuts on a surface of a die of the GPU. In the mesh, the portion exposed through the opening is formed of two layers, a first layer and a second layer. In the mesh, an area of the exposed portion exposed through the opening is smaller than an area of the other portion.

Abstract: In an embodiment, a device includes a package component including an integrated circuit die and conductive connectors connected to the integrated circuit die, the conductive connectors disposed at a front-side of the package component. The device also includes a back-side metal layer on a back-side of the package component. The device also includes an indium thermal interface material on a back-side of the back-side metal layer. The device also includes a lid on a back-side of the indium thermal interface material. The device also includes a package substrate connected to the conductive connectors, the lid being adhered to the package substrate.

Abstract: Power electronics assemblies having embedded power electronics devices are disclosed. In one embodiment, a power electronics assembly includes a circuit board assembly that includes a substrate that is electrically insulating and a power electronics device assembly embedded in the substrate. The power electronics device assembly includes an S-cell that includes an inner graphite layer, a metal layer encasing the inner graphite layer, and a first surface of the metal layer comprising a recess provided within the first surface. The power electronics device assembly further includes a power electronics device disposed within the recess of the first surface.

Abstract: Power electronics device assemblies, circuit board assemblies, and power electronics assemblies are disclosed. In one embodiment, a power electronics device assembly includes an S-cell including a first metal layer, a first graphite layer bonded to the first metal layer, an electrically insulating layer bonded to the first graphite layer, a second graphite layer bonded to the electrically insulating layer and a second metal layer bonded to the second graphite layer, the second metal layer comprising a surface and a recess provided within the surface. The power electronics device assembly further includes a power electronics device disposed within the recess of the surface.

Abstract: A semiconductor package includes a first redistribution circuit structure, a semiconductor die, and an electrically conductive structure. The semiconductor die is disposed over and electrically coupled to the first redistribution circuit structure. The electrically conductive structure connects a non-active side of the semiconductor die to a conductive feature of the first redistribution circuit structure, where the semiconductor die is thermally couped to the first redistribution circuit structure through the electrically conductive structure, and the electrically conductive structure includes a structure of multi-layer with different materials.

Abstract: A method includes attaching a permeable plate to a metal lid, with the permeable plate including a metallic material, and dispensing a liquid-metal-comprising media to a first package component. The first package component is over and bonded to a second package component. The liquid-metal-comprising media includes a liquid metal therein. The method further includes attaching the metal lid to the second package component. During the attaching, the liquid-metal-comprising media migrates into the permeable plate to form a composite thermal interface material.

Abstract: To improve cooling capability, power conversion apparatus 1 that converts a direct current voltage into an alternating current voltage includes: first substrate 100 on which power conversion circuit 2 is mounted; second substrate 200 on which driving circuit 3 that drives power conversion circuit 2 is mounted; and shield plate 300 that is disposed between first substrate 100 and second substrate 200, and first substrate 100 is a metal substrate.

Abstract: There is disclosed by way of example a computing apparatus, having a packaged circuit with an exterior surface, a heat sink having a pedestal disposed to nearly contact the packaged circuit with a nominal clearance when the packaged circuit is assembled to the heat sink, and a first thermal interface material (TIM) and a second TIM disposed in layers between the packaged circuit and the pedestal, wherein the first TIM is non-flowable at operating temperatures of the packaged circuit, and the second TIM is flowable at the operating temperatures.

Abstract: A semiconductor module includes a first substrate, a second substrate having a closed, in particular continuous, hollow chamber structure, and a semiconductor element having a first side connected to the first substrate in a planar manner and a second side which faces away from the first side and is connected to the second substrate in a planar manner. A phase change material is arranged in the hollow chamber structure of the second substrate and in thermally conductive connection with the semiconductor element.

Abstract: A three-dimensional (3D) integrated circuit (IC) module and a method of fabricating the 3D IC module are disclosed. In the 3D IC module, a conductive hole for connection with an internal specified metal layer and a trench arranged to avoid the conductive hole are formed in a topmost substrate of a semiconductor structure. A first passivation layer spans over and covers the trench, the first passivation layer and the trench together delimit a heat exchange channel. During operation of 3D IC module, a heat dissipation medium may be caused to flow through the heat exchange channel to facilitate heat dissipation. Thus, the 3D IC module has enhanced heat dissipation ability and is substantially immune from the problems of excessive heat build-up and uneven heat dissipation. This helps optimize performance and reliability of the 3D IC module. The method can be used to make such a 3D IC module.

Abstract: A method includes disposing at least one power device between a first direct bonded metal (DBM) substrate and a second DMB substrate and thermally coupling a plurality of pipes to a top side of the first DBM substrate opposite a side of the first DBM substrate with the at least one power device. The plurality of pipes is configured to carry cooling fluids in thermal contact with the first DBM substrate.

Abstract: Embodiments herein provide for fluidic cooling assemblies embedded within a device package and related manufacturing methods. In one embodiment, the cooling assembly includes a cold plate body attached to a singulated device and a manifold lid attached to the cold plate body. The cold plate body has a first side adjacent to the singulated device and an opposite second side, and the manifold lid is attached to the second side. In some embodiments, the first side of the cold plate body and the backside of the singulated device each comprise a dielectric material surface, the cold plate body is attached to the singulated device by direct dielectric bonds formed between the dielectric material surfaces, the cold plate body, and the manifold lid define one or more cavities, and the one or more cavities form at least a portion of a fluid flow path from an inlet to an outlet of the manifold lid.

Abstract: A semiconductor device, includes: a substrate having a first region and a second region; a first device on the substrate, in the first region; a second device on the substrate, in the second region; a front side interconnection structure including a plurality of interconnection layers electrically connected to the first device and the second device, on a front side of the substrate; and a back side buried interconnection structure adjacently to a back side of the substrate opposing the front side. The back side buried interconnection structure includes a back side buried insulating layer in a trench recessed from a back side of the substrate toward the front side of the substrate, and a back side buried conductive layer in the back side buried insulating layer. The back side buried interconnection structure is located in the first region or the second region.

Abstract: A semiconductor device includes a semiconductor chip, a plurality of leads that each includes a lead body portion which has a mounting portion which includes an upper surface whereon a semiconductor chip is bonded, and a lead connecting portion for external connection which projects downward from a lower surface of the lead body portion, a first sealing resin that seals a space that is defined by each lead body portion and each lead connecting portion of the plurality of leads in a region below the upper surface of each lead body portion of the plurality of leads, and a second sealing resin that seals the semiconductor chip in a region above the upper surface of each lead body portion of the plurality of leads.

Abstract: A semiconductor die mounting substrate, such as a pre-molded leadframe, is provided with die pads, wherein each die pad has opposed first and second surfaces as well as tie bars projecting therefrom. Semiconductor dice are mounted at the first surface of the die pads. A molding encapsulation material surrounds the semiconductor dice mounted at the first surface of the die pads to produce semiconductor devices, with the semiconductor devices being mutually coupled via the tie bars. The tie bars are then cut transverse to their longitudinal direction at an intermediate singulation location to singulate the semiconductor devices into individual semiconductor devices. The tie bars have a hollowed-out portion with a channel-shaped cross-sectional profile at the intermediate singulation location. Easier-to-cut tie bars can be provided without impairing their stiffness in comparison with tie bars having full rectangular/square cross-sectional shapes.

Abstract: A clip structure for a packaged semiconductor device is provided. The packaged semiconductor device includes a first die portion and a second die portion being electrically isolated from the first die portion. The clip structure includes a first portion, a second portion and a gate wire bond. The first portion is electrically conductive, and the first portion is configured to integrally connect a source terminal with the first die portion. The second portion is electrically conductive and is electrically isolated from the first portion and is configured to connect to a gate terminal. The gate wire bond is configured to connect the second portion with the second die portion.

Abstract: A power electronics module, having a PCB having power semiconductors arranged on connecting regions of an uppermost layer of said PCB, wherein the PCB has a preset dimension to arrange a preset maximum number of power semiconductors thereon. A lead frame arranged above the power semiconductors provides three-dimensional power and control routing, and includes a drain-source connection to connect to a drain-source contact of the PCB, and a load-source connection opposite the drain-source connection via the power semiconductors that is formed from a plurality of subregions, each of which can be brought into electrical contact with the power semiconductors, and a gate- and kelvin-source terminal, which are arranged above the load-source connection and have been brought into electrical contact with the power semiconductors. At least one dummy chip consisting of an electrically nonconductive material is arranged on each of the connecting regions that are not populated by power semiconductors.

Abstract: A power electronics module, having a continuous DBC PCB having power semiconductors arranged on connecting regions of an uppermost layer of said DBC PCB and a lead frame arranged above the power semiconductors for three-dimensional power and control routing, wherein the lead frame has a drain-source connection, which can be brought into electrical contact with a drain-source contact of the PCB, and a load-source connection which is opposite the drain-source connection via the power semiconductors and which is formed from a plurality of subregions, each of which can be brought into electrical contact with one of the power semiconductors, and at least one gate-source terminal and at least one kelvin-source terminal, and a carrier element including an electrically insulating material on which conductor tracks are provided, wherein the carrier element is routed between the power semiconductors in a region between the load-source connection and the drain-source connection.

Abstract: This semiconductor device comprises a substrate, a first wiring part, a second wiring part, and a semiconductor element. The first wiring part includes a first through-electrode, first main-surface wiring, and a first wiring electrode. The second wiring section includes a second through-electrode, second main-surface wiring, and a second wiring electrode. An upper surface is depressed toward the interior of the first through-electrode. The first wiring electrode is joined to a first element electrode of the semiconductor element by a first joining member. The second wiring electrode is joined to a second element electrode of the semiconductor element by a second joining member. The first wiring electrode, which is formed on an upper surface of the first main-surface wiring, is larger than the second wiring electrode, which is formed on an upper surface of the second main-surface wiring, as seen from the thickness direction.

Abstract: Novel tools and techniques are provided for implementing a substrate with an elastomer layer. The substrate might include one or more interconnects and an elastomer layer comprising at least one conductor. In some instances, the at least one conductor of the elastomer layer couples to at least one of the one or more interconnects of the substrate. Additionally, the at least one conductor is configured to couple at least one of the one or more interconnects of the substrate to a circuit board.

Abstract: A semiconductor package includes a first redistribution substrate, a semiconductor chip provided on a top surface of the first redistribution substrate, a conductive structure provided on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip, a molding layer provided on the first redistribution substrate and covering a side surface of the semiconductor chip and a side surface of the conductive structure, and a second redistribution substrate on the molding layer and the conductive structure. The conductive structure includes a first conductive structure provided on the first redistribution substrate, and a second conductive structure provided on a top surface of the first conductive structure. The second redistribution substrate includes an insulating layer. At least a portion of a top surface of the second conductive structure directly contacts the insulating layer of the second redistribution substrate.

Abstract: A semiconductor device includes: an isolation circuit board; a semiconductor chip provided on one main surface of the isolation circuit board; a first external terminal having a main surface and including a first snubber connecting portion rising from the main surface of the first external terminal, the first external terminal being electrically connected to the semiconductor chip; a second external terminal placed adjacent to the first external terminal, having a main surface facing the same direction as the main surface of the first external terminal, and including a second snubber connecting portion rising from the main surface of the second external terminal, the second external terminal being electrically connected to the semiconductor chip; and a capacitor having one end connected to the first snubber connecting portion and the other end connected to the second snubber connecting portion

Abstract: A non-conductive encapsulation cover is mounted on a support face of a support substrate to delimit, with the support substrate, an internal housing. An integrated circuit chip is mounted to the support substrate within the internal housing. A metal pattern is mounted to an internal wall of the non-conductive encapsulation cover in a position facing the support face. At least two U-shaped metal wires are provided within the internal housing, located to a side of the integrated circuit chip, and fixed at one end to the metallic pattern and at another end to the support face.

Abstract: Novel tools and techniques are provided for implementing novel semiconductor package interconnection structure(s) between package substrate and PCB. In various embodiments, a semiconductor device comprises: a substrate; a plurality of posts; a plurality of solder anchor portions; and a plurality of solder balls. Each post is coupled at a proximal end to a conductive point on a layer of the substrate, and has a length extending along its axis between its proximal and distal ends and a width orthogonal to the length. Each solder anchor portion is coupled to the distal end of a corresponding post, and has a width that is larger than the width of a distal end of a pillar portion of the corresponding post. Each solder ball is disposed on and around a corresponding solder anchor portion, the solder balls and corresponding posts forming conductive interconnects between corresponding substrate conductive points and corresponding PCB contact points.

Abstract: Semiconductor device packages and methods of forming the same are discussed. In an embodiment, a device includes: a redistribution structure comprising an upper dielectric layer and an under-bump metallization; a buffer feature on the under-bump metallization and the upper dielectric layer, the buffer feature covering an edge of the under-bump metallization, the buffer feature bonded to the upper dielectric layer; a reflowable connector extending through the buffer feature, the reflowable connector coupled to the under-bump metallization; an interposer coupled to the reflowable connector; and an encapsulant around the interposer and the reflowable connector, the encapsulant different from the buffer feature.

Abstract: A semiconductor package includes a partitioned package substrate composed of substrate parts arranged in a side-by-side manner; an integrated circuit die mounted on a first surface of the partitioned package substrate; and solder balls mounted on a second surface of the partitioned package substrate opposite to the first surface.