Abstract: In various example embodiments, a system and method for determining a crowd response for a crowd are presented. One method is disclosed that includes receiving an audio signal that includes concurrent responses from two or more respondents, determining the concurrent responses from the audio signal without regard to the identity of the respondents, and generating a crowd based on the concurrent responses.

Abstract: Techniques for detecting certain acoustic events from audio data are described. A system may perform event aggregation for certain types of events before sending an output to a device representing the event is detected. The system may bypass the event aggregation process for certain types of events that the system may detect with a high level of confidence. In such cases, the system may send an output to the device when the event is detected. The system may be used to detect acoustic events representing presence of a person or other harmful circumstances (such as, fire, smoke, etc.) in a home, an office, a store, or other types of indoor settings.

Abstract: A hearing device includes: a first microphone and a second microphone for provision of a first microphone input signal and a second microphone input signal, respectively; a voice detector module configured to process the first microphone input signal and the second microphone input signal, the voice detector module configured to detect own-voice of a user of the hearing device; a processor configured to process the first microphone input signal and the second microphone input signal for provision of an electrical output signal based on the first microphone input signal and the second microphone input signal; and a receiver configured to convert the electrical output signal to an audio output signal; wherein the voice detector module is configured to notify a detection of the own-voice to the processor if at least two of a first voice criterion, a second voice criterion, and a third voice criterion are satisfied.

Abstract: An electronic apparatus including a processor configured to receive a first audio signal, obtain a second audio signal by relating noise to the received first audio signal, identify whether the second audio signal matches a second command obtained by relating the noise to a first command of first reference data, based on second reference data, obtained by relating the noise to the first reference data, and perform an operation based on identification in response to the identifying that the second audio signal matches the second command.

Abstract: According to one embodiment, a magnetic recording device includes a magnetic head and a controller. The magnetic head includes first and second magnetic poles, a magnetic element provided between the first and second magnetic poles, and first and second terminals. The controller is configured to perform a recording operation. In the recording operation, the controller is configured to supply a recording current to the coil while applying an element voltage not less than a first voltage and not more than a second voltage between the first terminal and the second terminal. A differential resistance of the magnetic element when a positive applied voltage applied between the first terminal and the second terminal is changed while the recording current is supplied to the coil becomes a first peak when the applied voltage is the first voltage.

Abstract: A tape reel according to an embodiment of the present technology includes: a cylindrical reel hub that includes an outer periphery portion, a tape being wound on the reel hub. The reel hub is formed of a material in which a deformation amount when a load of 300 N is applied radially inward to an axial center of the outer periphery portion is 0.3 mm or less and a water absorption rate is 0.1% or less.

Abstract: The present disclosure provides a video processing method and apparatus, an electronic device, and a computer-readable storage medium, the video processing method includes: receiving a to-be-processed video; displaying, on a display interface, a preview image of the to-be-processed video through a video preview region, displaying an editing track of the to-be-processed video through a track editing region, and displaying at least one processing function through a processing function navigation region; and when receiving a trigger operation for any processing function, displaying, in the video preview region, a preview image of a processed video obtained by processing the any processing function, and displaying, in the track editing region, an editing identifier corresponding to the any processing function. The editing identifier and the editing track of the to-be-processed video are superimposed and displayed in the track editing region.

Abstract: Various embodiments provide an apparatus, a method, and a computer program product. The apparatus includes at least one processor; and at least one non-transitory memory including computer program code; wherein the at least one memory and the computer program code are configured to, with the at least one processor, cause the apparatus at least to perform: define or utilize file format syntax elements to indicate samples comprising at least one of: one or more description documents, wherein the one or more description documents comprise 3 dimensional information; or one or more updates to at least one description document of the one or more description documents; and define or utilize the file format syntax elements to indicate a relationship between samples containing the one or more description document and update information to the samples.

Abstract: A STRAMR structure is disclosed. The STRAMR structure can include a spin torque oscillator (STO) device in a WG provided between the mail pole (MP) trailing side and a trailing shield. The STO device, includes: a flux guiding layer that has a negative spin polarization (nFGL) with a magnetization pointing substantially parallel to the WG field without the current bias and formed between a first spin polarization preserving layer (ppL1) and a second spin polarization preserving layer (ppL2); a positive spin polarization (pSP) layer that adjoins the TS bottom surface; a non-spin polarization preserving layer (pxL) contacting the MP trailing side; a first negative spin injection layer (nSIL1) between the ppL2 and a third spin polarization preserving layer (ppL3); and a second negative spin injection layer (nSIL2) between the ppL3 and the pxL, wherein the nFGL, nSIL1, and nSIL2 have a spin polarization that is negative.

Abstract: According to one embodiment, a magnetic recording device includes a magnetic recording medium group and a magnetic head group. The magnetic recording medium group includes a first magnetic recording medium, a plurality of second magnetic recording media, and a plurality of third magnetic recording media. The magnetic head group includes a first magnetic head, a plurality of second magnetic heads, and a plurality of third magnetic heads. The first magnetic head is configured to record data on the first magnetic recording medium by a first method. One of the plurality of second magnetic heads is configured to record data on one of the plurality of second magnetic recording media by a second method different from the first method. One of the plurality of third magnetic heads is configured to record data on one of the plurality of third magnetic recording media by the second method.

Abstract: A PZT microactuator such as for a hard disk drive has a restraining layer bonded on its side that is opposite the side on which the PZT is mounted. The restraining layer comprises a stiff and resilient material such as stainless steel. The restraining layer can cover most or all of the top of the PZT, with an electrical connection being made to the PZT where it is not covered by the restraining layer. The restraining layer reduces bending of the PZT as mounted and hence increases effective stroke length, or reverses the sign of the bending which increases the effective stroke length of the PZT even further. The restraining layer can be one or more active layers of PZT material that act in the opposite direction as the main PZT layer. The restraining layer(s) may be thinner than the main PZT layer.

Abstract: A magnetic head includes a first servo reading element pair, a second servo reading element pair, and a plurality of magnetic elements. The first servo reading element pair consists of a first servo reading element and a second servo reading element, the second servo reading element pair consists of a third servo reading element and a fourth servo reading element, the first servo reading element and the third servo reading element are disposed on one end side of the plurality of magnetic elements and read one servo band of the pair of servo bands, and the second servo reading element and the fourth servo reading element are disposed on the other end side of the plurality of magnetic elements and read the other servo band of the pair of servo bands.

Abstract: An object is to provide a magnetic recording medium having favorable crystal orientation characteristics and exhibiting a high SNR. The present technology provides a magnetic recording medium having a layer structure including a recording layer, a ground layer, and a base layer in this order, in which the ground layer includes a first ground layer on the recording layer side and a second ground layer on the base layer side, the first ground layer contains a nonmagnetic oxide, the first ground layer has a thickness of 2 nm or more and 10 nm or less, and the second ground layer has a thickness of 40 nm or more. Furthermore, the present technology also provides a magnetic recording cartridge including the magnetic recording medium.

Abstract: A radiation image reading device includes: a light scanning unit; a light detection unit. Each of a transmittance when the excitation light reflected from the surface of the recording medium is transmitted through the optical filter and a transmittance when the signal light emitted from the surface of the recording medium at an angle larger than a predetermined angle with respect to a direction perpendicular to the scan line within the detection surface is transmitted through the optical filter is smaller than a transmittance when the signal light emitted from the surface of the recording medium at an angle smaller than the predetermined angle with respect to a direction perpendicular to the scan line within the detection surface is transmitted through the optical filter.

Abstract: A semiconductor apparatus includes a nonvolatile memory cell array including a plurality of first memory cells and a plurality of second memory cells including a first memory element 11 and a second memory element 12 including a resistance-variable nonvolatile memory element and a first selection transistor electrically connected to the first memory element 11 and the second memory element 12, in which a plurality of first memory elements 11 and a plurality of second memory elements 12 are arranged in a two-dimensional matrix in a first direction and a second direction different from the first direction and on the same interlayer insulating layer, the first memory element 11 is larger than the second memory element 12, and the first memory element 11 and the second memory element 12 are disposed adjacent to each other along the second direction.

Abstract: A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ?2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.

Abstract: The present disclosure includes apparatuses, methods, and systems for unbalanced programmed data states in memory. An embodiment includes a memory having a group of memory cells, and circuitry configured to determine a quantity of the memory cells of the group to program to a first data state, wherein the determined quantity of memory cells is less than or greater than half of the memory cells of the group, program the determined quantity of the memory cells of the group to the first data state, and program a remaining quantity of the memory cells of the group to a second data state.

Abstract: Methods, systems, and devices for configurable input for an amplifier are described. In some examples, a circuit may be configured to operate based on a signal having a first voltage profile or a second voltage profile. For example, the first voltage profile may be associated with a range of voltages that are based on a temperature of an associated memory chip, and the second voltage profile may be associated with a voltage (or voltages) that are not associated with the temperature of the memory chip. The circuit may include one or more transistors and switches that are activated based on the voltage profile and a switch receiving a particular control signal. In some instances, the control signal may be received based on a value stored to one or more non-volatile memory elements.

Abstract: A memory device includes an array of memory cells and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit may be configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells. Inserting a switch device across the different power domains to achieve the same sequential wake-up path for the peripheral circuits connected to different power domains reduces peak current.

Abstract: An internal voltage generation circuit includes an enable control circuit configured to generate a final enable signal by limiting an activation time point of an enable signal to a point in time after a reset time, after the enable signal is inactivated. The internal voltage generation circuit also includes a start-up control circuit configured to perform a reset operation during the reset time and generate a start-up signal based on the final enable signal, a reference voltage generation circuit configured to generate a reference voltage based on the start-up signal, a current generation circuit configured to generate a reference current based on the reference voltage, and a voltage generation circuit configured to generate an internal voltage based on the reference current.

Abstract: The invention relates to DRAM with sustainable storage architecture. The DRAM comprises a first supplying voltage source generating a voltage level corresponding to signal ONE utilized in the DRAM chip, and a DRAM cell which includes an access transistor and a storage capacitor. Wherein a first voltage level is higher than the voltage level corresponding to signal ONE, and the first voltage level is generated by a first sustaining voltage generator. The first sustaining voltage generator is electrically coupled to the storage capacitor of the DRAM cell during a turning-off period of the access transistor of the DRAM cell. A clean up circuit is provided to mitigate the difference between the voltages of BL/BLB and the targeted reference voltage during the equalization period.

Abstract: An exemplary semiconductor device includes an internal clock circuit configured to intermittently enable and disable a clock signal while in a Maximum Power Savings Mode. The duty cycle of the enablement and disablement of the clock signal may be based on susceptibility to negative-bias temperature instability of a component of the semiconductor device. The clock signal may be enabled and disabled via a synchronizer.

Abstract: An integrated circuit includes: first and second pattern generation circuits generating first and second pattern signal for a sampling section; a first section control part generating a coarse section signal for a first section of the sampling section, according to the first pattern signal; a first filter part generating a first section extract signal by filtering the second pattern signal according to the coarse section signal; a second section control part generating a fine section signal for a second section of the sampling section, according to the first section extract signal; a second filter part generating a second section extract signal by filtering the second pattern signal according to the fine section signal; an output control circuit generating a sampling enable signal according to the first and second section extract signals; and a sampling circuit suitable for sampling an input signal according to the sampling enable signal.

Abstract: A memory structure includes a first memory array having bit lines; a second memory array having bit lines; a first sense amplifier connected to a first bit line of the first memory array and a first bit line of the second memory array; and a second sense amplifier connected to a second bit line of the first memory array and a second bit line of the second memory array. The second bit line of the first memory array is adjacent to the first bit line of the first memory array, and the second bit line of the second memory array is adjacent to the first bit line of the second memory array.

Abstract: A static random access memory (SRAM) has one or more arrays of memory cells, each array of memory cells activated in columns by a wordline. The activated column of memory cells asserts output data onto a plurality of bitlines coupled to output drivers. The SRAM includes a wordline controller generating a variable pulse width wordline which may be reduced sufficient to introduce memory read errors. Each of a high error rate, medium error rate, low error rate, and error-free rate is associated with a pulse width value generated by the wordline controller. A power consumption tradeoff exists between the wordline pulse width and consumed SRAM power. The wordline controller is thereby able to associate a wordline pulse width to an associated error rate for performing tasks which are insensitive to a high error rate or a medium error rate, which are specific to certain neural network training and inference using various NN data types.

Abstract: Various implementations described herein are directed to a device having memory with banks of bitcells with each bank having a bitcell array. The device may have header circuitry that powers-up a selected bank and powers-down unselected banks during a wake-up mode of operation. In some instances, only the selected bank of the memory is powered-up with the header circuitry during the wake-up mode of operation.

Abstract: A method of memory reset includes precharging bit lines of a memory array, asserting a signal at a reset node to remove the precharge voltage, and selecting write drivers associated with the bit lines associated with columns of the memory array that contain memory cells to be reset, with the assertion of the signal at the reset node also resulting in application of desired logic states to inputs of the selected write drivers to cause those selected write drivers to change a logic state of the bit lines associated with those write drivers. The method continues with asserting each word line associated with a row of the memory that contains memory cells to be reset to write desired logic states to all of the memory cells of the columns and rows of the memory to be reset during a single clock cycle, and then deasserting those word lines.

Abstract: A fin field-effect transistor (FinFET) based semiconductor memory array having a plurality of memory cells, each memory cell including a write transistor having a write wordline gate over a first fin connected to a write wordline gate contact, a write bitline contact in connection with the first fin, and a storage node contact in connection with the first fin, and a read transistor having a storage node gate over a second fin, the storage node gate connected to a storage node gate contact, the storage node gate contact connected to the storage node contact, a read wordline contact in connection with the second fin, and a read bitline contact in connection with the second fin, wherein the write wordline gate and the storage node gate are arranged in series to each other along an extension axis that coincides with an longitudinal axis of the write wordline gate and a longitudinal axis of the storage node gate.

Abstract: A resistive random-access memory (ReRAM) array with parallel reset and set programming and a method for programming is presented. The ReRAM array includes a plurality of ReRAM cells arranged in an array, wherein the array includes a plurality of rows and a plurality of columns, wherein at least two ReRAM cells of an array includes a word, wherein each ReRAM cell includes a select device having a control port, a first port, and a second port, and a resistive element; and a plurality of controllers, wherein the output of each of the plurality of controllers cause a reset programming or a set programming of the ReRAM cell in the column of the plurality of ReRAM cells that has the respective word line activated; such that the reset programming and the set programming occur in parallel.

Abstract: The present disclosure generally relates to multi-switch storage cells (MSSCs), three-dimensional MSSC arrays, and three-dimensional MSSC memory. Multi-switch storage cells include a cell select device, multiple resistive change elements, and an intracell wiring electrically connecting the multiple resistive change elements together and to the cell select device. MSSC arrays are designed (architected) and operated to prevent inter-cell (sneak path) currents between multi-switch storage cells, which prevents stored data disturb from adjacent cells and adjacent cell data pattern sensitivity. Additionally, READ and WRITE operations may be performed on one of the multiple resistive change elements in a multi-switch storage cell without disturbing the stored data in the remaining resistive change elements. However, controlled parasitic currents may flow in the remaining resistive change elements within the cell.

Abstract: The application provides a content addressable memory (CAM) cell, a CAM memory device and an operation method thereof, and a method for searching and comparing data. The CAM cell includes a first flash memory cell having a first terminal for receiving a first search voltage; and a second flash memory cell having a first terminal for receiving a second search voltage, a second terminal of the first flash memory cell electrically connected to a second terminal of the second flash memory cell, wherein the first flash memory cell and the second flash memory cell are serially connected; and a storage data of the CAM cell is based on a combination of a plurality of threshold voltages of the first flash memory cell and the second flash memory cell.

Abstract: A semiconductor storage device includes a memory cell array including a plurality of word line groups and a plurality of blocks corresponding to the plurality of word line groups. Each of word line groups includes a plurality of word lines and each of the blocks includes a plurality of memory cells. The plurality of memory cells of each block are connected to the respective word lines of a corresponding one of the word line groups. The semiconductor storage device includes a row decoder including a plurality of word line group decoders corresponding to the plurality of word line groups, respectively. Each of the plurality of word line group decoders is configured to drive a word line independent from a word line driven in another of the word line groups, when all of the plurality of word line groups are activated in parallel.

Abstract: Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Abstract: Provided herein is a memory device that may include a plurality of memory cells coupled to a plurality of bit lines and a common source line. The memory device may also include a control circuit configured to control a peripheral circuit to perform a program operation that includes two or more program steps on selected memory cells of a selected word line. The peripheral circuit may be configured to perform a first program step of the two or more program steps on the selected memory cells, then perform a detrap operation that applies a detrap voltage to the plurality of bit lines and the common source line for a predefined time, and thereafter perform a second program step of the two or more program steps on the selected memory cells.

Abstract: Exemplary methods, apparatuses, and systems including a programming manager for controlling writing data bits to a memory device. The programming manager receives a first set of data bits for programming to memory. The programming manager writes a first subset of data bits to a first wordline during a first pass of programming. The programming manager writes a second subset of data bits of the first set of data bits to a buffer. The programming manager receives a second set of data bits for programming. The programming manager writes the second subset of data bits of the first set of data bits to the first wordline during a second pass of programming to increase a bit density of memory cells in the first wordline in response to receiving the second set of data bits.

Abstract: A memory, a programming method, and a memory system are provided. The programming method includes programming a selected memory cell string according to a programming sequence; applying, when programming a memory cell in the selected memory cell string that is coupled to a selected non-edge word line in a plurality of word lines, a first pass voltage to edge word lines in the plurality of word lines; and applying a second pass voltage to a non-edge word line adjacent to the edge word lines. The edge word lines are at least one word line in the plurality of word lines adjacent to the source line or to the bit line; the non-edge word lines are word lines in the plurality of word lines other than the edge word lines; and the selected non-edge word line is not adjacent to the edge word lines.

Abstract: A memory device includes a memory array comprising memory cells and control logic. The control logic performs operations including: causing a first erase pulse to be applied to a memory line of the memory array to perform an erase operation, the memory line being a conductive line coupled to a string of the memory cells; suspending the erase operation in response to receipt of a suspend command during a ramping period of the first erase pulse; recording a suspend voltage level of the first erase pulse when suspended; causing the erase operation to be resumed in response to an erase resume command; selectively modifying a pulse width of a flattop period of a second erase pulse based on the suspend voltage level; and causing the second erase pulse to be applied to the memory line during a resume of the erase operation.

Abstract: A processing device in a memory system connects a first data block of the memory device to a second data block of the memory device to generate a combined data block comprising a first plurality of sub-blocks of the first data block and a second plurality of sub-blocks of the second data block, wherein the connecting includes: for each wordline of a first plurality of wordlines of the first data block, creating a wordline connection short between the respective wordline of the first data block and a corresponding wordline of a second plurality of wordlines of the second data block, wherein the first plurality of wordlines and the second plurality of wordlines comprise data wordlines; and driving a first data wordline of the first data block and a second wordline of the second data block using a single string driver of the memory device.

Abstract: Disclosed is a physical unclonable function generator circuit and testing method.

Abstract: Provided herein may be a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory cells that are coupled to a plurality of word lines, a peripheral circuit configured to perform a read operation by applying a read voltage to a selected word line, among the plurality of word lines, and applying a first pass voltage to target word lines, wherein the target word lines are adjacent to the selected word line, among unselected word lines other than the selected word line, and a control logic configured to decrease the read voltage based on a read voltage variation and to decrease the first pass voltage based on a pass voltage variation when the read voltage decreases, wherein the pass voltage variation is less than the read voltage variation.

Abstract: A nonvolatile semiconductor memory device according to one embodiment of the present invention includes: a memory cell array and a control circuit. The control circuit executes a first reading operation and a second reading operation. The first reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between a control gate electrode and source of the selected memory cell to a first value. The second reading operation is an operation of reading a threshold voltage set in the selected memory cell by setting a voltage between the control gate electrode and source of the selected memory cell to a second value lower than the first value. When executing the second reading operation, the control circuit keeps a voltage of the control gate electrode of the selected memory cell to 0 or a positive value.

Abstract: A data storage device including, in one implementation, a number of memory die packages disposed on a substrate within the data storage device. Each memory die package has a die density that includes one or more memory dies. The die density of each memory die package is configured to provide an even thermal distribution across the number of memory die packages. The respective die densities of two memory of the die packages are different from each other.

Abstract: A multi time program device with a power switch and a non-volatile memory implementing the power switch for multi time program is provided. The device performs a program operation or an erase operation of a non-volatile memory cell in a non-volatile memory device.

Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

Abstract: A semiconductor memory device includes a memory cell array circuit and a driving force adjustment circuit. The memory cell array circuit includes a plurality of memory cells. The driving force adjustment circuit adjusts driving forces of a plurality of respective verify pass voltages based on whether or not the plurality of memory cells are programmed.

Abstract: A storage device includes: a memory device including a plurality of memory cells, the memory device performing a read operation of reading data stored in selected memory cells among the plurality of memory cells; and a memory controller for receiving a read request from a host, and controlling the memory device to perform the read operation corresponding to the read request. The memory controller includes a read voltage inferrer for, when the read operation is completed, receiving read information on the read operation from the memory device, performing a read quality evaluation operation of evaluating the read operation based on the read information, and performing a read voltage inference operation of inferring a secondary read level corresponding to the read information according to a result of the performing the read quality evaluation operation.

Abstract: An operating method of a memory system includes storing normal data to a first storage area of a non-volatile memory in a first program mode among multiple program modes defined according to a number of bits stored in each memory cell; storing dummy data in the first storage area in at least one of the multiple program modes including the first program mode; and copying the normal data from the first storage area to a second storage area of the non-volatile memory based on dummy data stored in the first program mode.

Abstract: A processing system includes an error detection circuit configured to receive data bits and ECC bits, calculate further ECC bits as a function of the data bits, and generate a syndrome by comparing the calculated ECC bits with the received ECC bits. When the syndrome corresponds to one of N+K single bit-flip reference syndromes, the error detection circuit asserts a first error signal, and asserts one bit of a bit-flip signature corresponding to a single bit-flip error indicated by the respective single bit-flip reference syndrome.

Abstract: According to one embodiment, a non-volatile memory includes a plurality of groups and a memory controller configured to execute a first operation. Each of the plurality of groups includes a plurality of cell units. Each of the plurality of cell units includes a plurality of memory cells. The first operation includes: based on a first correction amount associated with a target group, reading data from the target group; and updating the first correction amount to a second correction amount based on the data. The memory controller is configured to: select a first group as the target group; and when a condition is satisfied, select a second group as the target group after performing the first operation related to the first group.