Characterized By Specified Crystallography Or Arrangement Of Substrate (e.g., Wafer Cassette, Miller Index) Patents (Class 117/101)
  • Patent number: 11004963
    Abstract: An embodiment relates to a method of manufacturing an insulated gate bipolar transistor in a semiconductor body. A first field stop zone portion of a first conductivity type is formed on a semiconductor substrate. A second field stop zone portion of the first conductivity type is formed on the first field stop zone portion. A drift zone of the first conductivity type is formed on the second field stop zone portion. A doping concentration in the drift zone is smaller than 1013 cm?3 along a vertical extension of more than 30% of a thickness of the semiconductor body upon completion of the insulated gate bipolar transistor.
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: May 11, 2021
    Assignee: Infineon Technologies AG
    Inventors: Oana Julia Spulber, Matthias Kuenle, Wolfgang Roesner, Christian Philipp Sandow, Christoph Weiss
  • Patent number: 10988857
    Abstract: A SiC single crystal growth apparatus of an embodiment includes a seed crystal installation part in which a seed crystal is installable at a position thereof which faces a raw material; a guide member which extends from a periphery of the seed crystal installation part toward the raw material and guides crystal growth performed inside the guide member; and a heat-insulating material which is movable along an extension direction of the guide member on the outside of the guide member.
    Type: Grant
    Filed: April 19, 2019
    Date of Patent: April 27, 2021
    Assignee: SHOWA DENKO K.K.
    Inventors: Rimpei Kindaichi, Yoshishige Okuno, Tomohiro Shonai
  • Patent number: 10941480
    Abstract: A method to transfer a layer of harder thin film substrate onto a softer, flexible substrate. In particular, the present invention provides a method to deposit a layer of sapphire thin film on to a softer and flexible substrate e.g. PET, polymers, plastics, paper and fabrics. This combination provides the hardness of sapphire thin film to softer flexible substrates.
    Type: Grant
    Filed: August 9, 2018
    Date of Patent: March 9, 2021
    Assignee: HKBU R&D LICENSING LIMITED
    Inventors: Kok Wai Cheah, King Fai Li, Hoi Lam Tam, Guixin Li, Wing Yui Lam, Yu Wai Chan
  • Patent number: 10930543
    Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.
    Type: Grant
    Filed: August 23, 2018
    Date of Patent: February 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Anhthu Ngo, Zuoming Zhu, Balasubramanian Ramachandran, Paul Brillhart, Edric Tong, Anzhong Chang, Kin Pong Lo, Kartik Shah, Schubert S. Chu, Zhepeng Cong, James Francis Mack, Nyi O. Myo, Kevin Joseph Bautista, Xuebin Li, Yi-Chiau Huang, Zhiyuan Ye
  • Patent number: 10903103
    Abstract: A front opening unified pod (FOUP) includes a container, a plurality of wafer slots, at least one inlet pipe, and at least one outlet pipe. The wafer slots, the inlet pipe, and the outlet pipe are disposed in the container. The inlet pipe has a plurality of exhale openings arranged along the inlet pipe. The outlet pipe has a plurality of inhale openings arranged along the outlet pipe.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: January 26, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shih-Fan Kuan
  • Patent number: 10851473
    Abstract: A method of producing silicon carbide is disclosed. The method comprises the steps of providing a sublimation furnace comprising a furnace shell, at least one heating element positioned outside the furnace shell, and a hot zone positioned inside the furnace shell surrounded by insulation. The hot zone comprises a crucible with a silicon carbide precursor positioned in the lower region and a silicon carbide seed positioned in the upper region. The hot zone is heated to sublimate the silicon carbide precursor, forming silicon carbide on the bottom surface of the silicon carbide seed. Also disclosed is the sublimation furnace to produce the silicon carbide as well as the resulting silicon carbide material.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: December 1, 2020
    Assignee: GTAT Corporation
    Inventors: Roman V. Drachev, Parthasarathy Santhanaraghavan, Andriy M. Andrukhiv, David S. Lyttle
  • Patent number: 10847342
    Abstract: A reference sample (41) has a step/terrace structure made of monocrystalline SiC and a surface of each terrace has first or second stack orientation. In the reference sample (41), contrast as difference in lightness and darkness between an image of a terrace with a surface directly under which the first stack orientation lies and an image of a terrace with a surface directly under which the second stack orientation lies changes according to an incident electron angle which is an angle that an electron beam emitted from a scanning electron microscope forms with a perpendicular to the terrace surface. Even when a SiC substrate has an off angle (e.g., from 1° to 8°), using an inclined support base (20a) capable of correcting the off angle enables sharp contrast that reflects difference between the first and second stack orientations directly under the surface to be obtained irrespective of the off angle.
    Type: Grant
    Filed: May 20, 2020
    Date of Patent: November 24, 2020
    Assignee: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Koji Ashida
  • Patent number: 10801126
    Abstract: A method of producing silicon carbide is disclosed. The method comprises the steps of providing a sublimation furnace comprising a furnace shell, at least one heating element positioned outside the furnace shell, and a hot zone positioned inside the furnace shell surrounded by insulation. The hot zone comprises a crucible with a silicon carbide precursor positioned in the lower region and a silicon carbide seed positioned in the upper region. The hot zone is heated to sublimate the silicon carbide precursor, forming silicon carbide on the bottom surface of the silicon carbide seed. Also disclosed is the sublimation furnace to produce the silicon carbide as well as the resulting silicon carbide material.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: October 13, 2020
    Assignee: GTAT Corporation
    Inventors: Roman V. Drachev, Parthasarathy Santhanaraghavan, Andriy M. Andrukhiv, David S. Lyttle
  • Patent number: 10793971
    Abstract: A method of producing silicon carbide is disclosed. The method comprises the steps of providing a sublimation furnace comprising a furnace shell, at least one heating element positioned outside the furnace shell, and a hot zone positioned inside the furnace shell surrounded by insulation. The hot zone comprises a crucible with a silicon carbide precursor positioned in the lower region and a silicon carbide seed positioned in the upper region. The hot zone is heated to sublimate the silicon carbide precursor, forming silicon carbide on the bottom surface of the silicon carbide seed. Also disclosed is the sublimation furnace to produce the silicon carbide as well as the resulting silicon carbide material.
    Type: Grant
    Filed: September 5, 2014
    Date of Patent: October 6, 2020
    Assignee: GTAT Corporation
    Inventors: Roman V. Drachev, Andriy M. Andrukhiv, David S. Lyttle, Parthasarathy Santhanaraghavan
  • Patent number: 10790177
    Abstract: The present disclosure provides systems and methods for monitoring an environment of a front opening universal pod (FOUP). The systems and methods may include one or more environmental sensors disposed within the FOUP, configured to measure environmental parameters of the environment of the FOUP and a FOUP configured to hold one or more wafers. The systems and methods may also include a wireless transmitter in communication with the environmental sensor, which may be disposed within the FOUP and configured to transmit the measured environmental parameters from the environmental sensor.
    Type: Grant
    Filed: February 27, 2018
    Date of Patent: September 29, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po Shun Lin, Zhi Long Huang, Kung Chieh Cheng
  • Patent number: 10738377
    Abstract: There is provided a method for manufacturing graphene. The method includes an adsorption step of causing six-membered ring structures of carbon atoms to be adsorbed to a surface of a substrate; and an irradiation step of irradiating the surface of the substrate with a beam of a molecule containing carbon atoms.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: August 11, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takashi Matsumoto
  • Patent number: 10699873
    Abstract: A reference sample (41) has a step/terrace structure made of monocrystalline SiC and a surface of each terrace has first or second stack orientation. In the reference sample (41), contrast as difference in lightness and darkness between an image of a terrace with a surface directly under which the first stack orientation lies and an image of a terrace with a surface directly under which the second stack orientation lies changes according to an incident electron angle which is an angle that an electron beam emitted from a scanning electron microscope forms with a perpendicular to the terrace surface. Even when a SiC substrate has an off angle (e.g., from 1° to 8°), using an inclined support base (20a) capable of correcting the off angle enables sharp contrast that reflects difference between the first and second stack orientations directly under the surface to be obtained irrespective of the off angle.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: June 30, 2020
    Assignee: KWANSEI GAKUIN EDUCATIONAL FOUNDATION
    Inventors: Tadaaki Kaneko, Koji Ashida
  • Patent number: 10686050
    Abstract: In a method of manufacturing a semiconductor device, a single crystal oxide layer is formed over a substrate. After the single crystal oxide layer is formed, an isolation structure to define an active region is formed. A gate structure is formed over the single crystal oxide layer in the active region. A source/drain structure is formed.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Georgios Vellianitis
  • Patent number: 10665748
    Abstract: A light-emitting diode includes from bottom to up: a substrate, a first-conductive type semiconductor layer, a super lattice, a multi-quantum well layer and a second-conductive type semiconductor layer. At least one layer of granular medium layer is inserted in the super lattice. The granular medium layer is used for forming V pits with different widths and depths in the super lattice. The multi-quantum well layer fills up the V pits and is over the top surface of the super lattice. The number of micro-particle generations, positions and densities can be adjusted by introducing granular medium layers and controlling the number of layers, position and growth conditions during super lattice growth process, to ensure V pits of different depths and densities. This can change hole injection effect, effectively improve hole injection efficiency and distribution uniformity in all quantum wells, thus improving LED light-emitting efficiency.
    Type: Grant
    Filed: December 20, 2017
    Date of Patent: May 26, 2020
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jie Zhang, Xiangxu Feng, Chengxiao Du, Jianming Liu, Chen-ke Hsu
  • Patent number: 10622516
    Abstract: An epitaxial structure and a method for making the same are provided. The epitaxial structure includes a substrate, an epitaxial layer and a carbon nanotube layer. The epitaxial layer is located on the substrate. The carbon nanotube layer is located in the epitaxial layer. The method includes following. A substrate having an epitaxial growth surface is provided. A carbon nanotube layer is suspended above the epitaxial growth surface. An epitaxial layer is epitaxially grown from the epitaxial growth surface to enclose the carbon nanotube layer therein. The epitaxial layer is a substantially homogenous material from the substrate.
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 14, 2020
    Assignees: Tsinghua University, HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: Yang Wei, Shou-Shan Fan
  • Patent number: 10615007
    Abstract: A gas distribution plate for a plasma reactor has a dielectric front plate and a dielectric back plate bonded together, with gas injection orifices extending through the front plate and gas supply channels in the surface of front plate facing the back plate. The back plate is joined to a heat reflective plate, or the back plate itself is formed of a heat reflective material, such as Beryllium Oxide.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: April 7, 2020
    Assignee: Applied Materials, Inc.
    Inventors: Michael W. Stowell, Qiwei Liang
  • Patent number: 10564351
    Abstract: A semi-finished product having a substrate with a first side and an opposite second side is provided, wherein at least one diamond layer is arranged on the first side, wherein the diamond layer comprises monocrystalline diamond and the substrate comprises a material different from the diamond layer. A method for producing such a semi-finished product is provided and an integrated optical component may be produced from the semi-finished product.
    Type: Grant
    Filed: March 5, 2018
    Date of Patent: February 18, 2020
    Assignee: FRAUNHOFER-GESELLSCHAFT ZUR FÖRDERUNG DER ANGEWANDTEN FORSCHUNG E.V.
    Inventors: Christoph E. Nebel, Christian Giese
  • Patent number: 10546746
    Abstract: A process of growing a barrier layer made of AlGaN on a GaN channel layer is disclosed. The process includes steps of, growing the GaN channel layer, growing the AlGaN barrier layer, and growing a cap layer made of GaN. The growth temperature of the AlGaN barrier layer monotonically lowers from the initial temperature, which may be equal to the growth temperature for the GaN channel layer, to the finish temperature that is lower than the initial temperature and may be substantially equal to the growth temperature of the GaN cap layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: January 28, 2020
    Assignee: SUMITOMO ELECTRIC DEVICE INNOVATIONS, INC.
    Inventor: Hajime Matsuda
  • Patent number: 10516080
    Abstract: There is provided a semiconductor device (101), including: a first semiconductor layer (25) having a main surface that is a growth surface in a lamination direction and a first side surface (251) disposed at a first angle; and a second semiconductor layer (24) adjacent the first semiconductor layer (25) having a second side surface (241) extending from the first side surface (251) of the first semiconductor layer (25) at a second angle different from the first angle.
    Type: Grant
    Filed: May 21, 2015
    Date of Patent: December 24, 2019
    Assignee: Sony Semiconductor Solutions Corporation
    Inventor: Hiroyuki Okuyama
  • Patent number: 10468551
    Abstract: Some aspects for the invention include a method and a structure including a light-emitting device disposed over a second crystalline semiconductor material formed over a semiconductor substrate comprising a first crystalline material.
    Type: Grant
    Filed: May 28, 2013
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jizhong Li, Anthony J. Lochtefeld
  • Patent number: 10444742
    Abstract: According to an embodiment, a material recommendation apparatus includes an extractor, a creator, a matcher and a recommender. The extractor extracts information about a substance as a candidate for a material for an industrial product, a property of the substance, and a report time of the property from an electronic document. The creator creates, for each substance, time series data in which the property is associated with the report time. The matcher matches the time series data with a pattern. The recommender recommends, as the material, a substance corresponding to time series data that matches the pattern.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 15, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ryohei Orihara, Yuichi Miyamura, Ayana Yamamoto, Masayuki Okamoto
  • Patent number: 10364498
    Abstract: According to one embodiment, a gas supply pipe has a first gas pipe configured to blow a gas which has flowed from an inflow opening via first gas blow holes arranged along a longitudinal direction, and a second gas pipe provided in parallel with the first gas pipe. The second gas pipe has second gas blow holes arranged along the longitudinal direction, and allows the gas to flow in a direction opposite to the first gas pipe.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: July 30, 2019
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takahiro Terada, Takuya Matsuda, Kaori Deura, Masayuki Tanaka, Aya Watase
  • Patent number: 10358741
    Abstract: Provided is an inexpensive seed material for liquid phase epitaxial growth of silicon carbide. A seed material 12 for liquid phase epitaxial growth of a monocrystalline silicon carbide includes a surface layer containing a polycrystalline silicon carbide with a 3C crystal polymorph. Upon X-ray diffraction of the surface layer thereof, a first-order diffraction peak corresponding to a (111) crystal plane is observed as a diffraction peak corresponding to the polycrystalline silicon carbide with a 3C crystal polymorph but no other first-order diffraction peak having a diffraction intensity of 10% or more of the diffraction intensity of the first-order diffraction peak corresponding to the (111) crystal plane is observed.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: July 23, 2019
    Assignee: TOYO TANSO CO., LTD.
    Inventors: Satoshi Torimi, Satoru Nogami, Tsuyoshi Matsumoto
  • Patent number: 10351955
    Abstract: A semiconductor substrate processing apparatus for processing semiconductor substrates includes showerhead module delivering process gas through a faceplate having gas passages therethrough from the process gas source to a processing zone of the processing apparatus wherein individual semiconductor substrates are processed. The showerhead module comprises a gas delivery conduit in fluid communication with a cavity at a lower end thereof, a baffle arrangement in the gas delivery conduit and the cavity, and a blocker plate in the cavity disposed below the baffle arrangement. The baffle arrangement comprises baffles which divide process gas flowing through the gas delivery conduit into center, inner annular, and outer annular flow streams.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: July 16, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Arun Keshavamurthy, Bart van Schravendijk, David Cohen
  • Patent number: 10323323
    Abstract: A gas delivery system includes a first valve including an inlet that communicates with a first gas source. A first inlet of a second valve communicates with an outlet of the first valve and a second inlet of the second valve communicates with a second gas source. An inlet of a third valve communicates with a third gas source. A connector includes a first gas channel and a cylinder defining a second gas channel. The cylinder and the first gas channel collectively define a flow channel between an outer surface of the cylinder and an inner surface of the first gas channel. The flow channel communicates with the outlet of the third valve and the first end of the second gas channel. A third gas channel communicates with the second gas channel, with the outlet of the second valve and with a gas distribution device of a processing chamber.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: June 18, 2019
    Assignee: LAM RESEARCH CORPORATION
    Inventors: Ramesh Chandrasekharan, Jennifer O'Loughlin, Saangrut Sangplung, Shankar Swaminathan, Frank Pasquale, Chloe Baldasseroni, Adrien LaVoie
  • Patent number: 10260165
    Abstract: There is provided a method for manufacturing a nitride crystal substrate, including: arranging a plurality of seed crystal substrates made of a nitride crystal in a planar appearance, so that their main surfaces are parallel to each other and their lateral surfaces are in contact with each other; growing a first crystal film using a vapor-phase growth method on a surface of the plurality of seed crystal substrates arranged in the planar appearance, and preparing a combined substrate formed by combining the adjacent seed crystal substrates each other by the first crystal film; growing a second crystal film using a liquid-phase growth method on a main surface of the combined substrate so as to be embedded in a groove that exists at a combined part of the seed crystal substrates, and preparing a substrate for crystal growth having a smoothened main surface; and growing a third crystal film using the vapor-phase growth method, on the smoothed main surface of the substrate for crystal growth.
    Type: Grant
    Filed: January 4, 2017
    Date of Patent: April 16, 2019
    Assignees: Osaka University, Sciocs Company Limited, Sumitomo Chemical Company, Limited
    Inventors: Yusuke Mori, Masashi Yoshimura, Mamoru Imade, Masayuki Imanishi, Masatomo Shibata, Takehiro Yoshida
  • Patent number: 10249767
    Abstract: A Ga2O3-based semiconductor element includes an undoped ?-Ga2O3 single crystal film disposed on a surface of a ?-Ga2O3 substrate, a source electrode and a drain electrode disposed on a same side of the undoped ?-Ga2O3 single crystal film, a gate electrode disposed on the undoped ?-Ga2O3 single crystal film between the source electrode and the drain electrode, and a region formed in the undoped ?-Ga2O3 single crystal film under the source electrode and the drain electrode and including a controlled dopant concentration.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: April 2, 2019
    Assignees: TAMURA CORPORATION, NATIONAL INSTITUTE OF INFORMATION AND COMMUNICATION TECHNOLOGY
    Inventors: Kohei Sasaki, Masataka Higashiwaki
  • Patent number: 10186635
    Abstract: A method of forming a vertical III-nitride based light emitting diode structure 5 and a vertical III-nitride based light emitting diode structure can be provided. The method comprises forming a III-nitride based light emitting structure on a silicon-oninsulator (SOI) substrate; forming a metal-based electrode structure on the III-nitride based light emitting structure; and removing the SOI substrate by a layer transfer process such that the metal-based electrode structure functions as a metal-based 10 substrate of the light emitting structure.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: January 22, 2019
    Assignee: AGENCY FOR SCIENCE TECHNOLOGY AND RESEARCH
    Inventors: Tripathy Sudhiranjan, Lin Vivian Kaixin, Teo Siew Lang, Dolmanan Surani Bin
  • Patent number: 10181515
    Abstract: Provided is a semiconductor device according to an embodiment including an i-type or first-conductivity-type first diamond semiconductor layer having a first side surface, a second-conductivity-type second diamond semiconductor layer provided on the first diamond semiconductor layer and having a second side surface, a third diamond semiconductor layer being in contact with the first side surface and the second side surface, the third diamond semiconductor containing nitrogen, a first electrode electrically connected to the first diamond semiconductor layer, and a second electrode electrically connected to the second diamond semiconductor layer.
    Type: Grant
    Filed: February 17, 2017
    Date of Patent: January 15, 2019
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Suzuki, Tadashi Sakai
  • Patent number: 10176991
    Abstract: High-quality, single-crystalline silicon-germanium (Si(1-x)Gex) having a high germanium content is provided. Layers of the high-quality, single-crystalline silicon-germanium can be grown to high sub-critical thicknesses and then released from their growth substrates to provide Si(1-x)Gex films without lattice mismatch-induced misfit dislocations or a mosaic distribution of crystallographic orientations.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: January 8, 2019
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Max G. Lagally, Thomas Francis Kuech, Yingxin Guan, Shelley A. Scott, Abhishek Bhat, Xiaorui Cui
  • Patent number: 10138397
    Abstract: The present invention relates to a single-crystal silicon-carbide substrate provided with a principal surface having an atomic step-and-terrace structure containing atomic steps and terraces derived from a crystal structure, in which the atomic step-and-terrace structure has a proportion of an average line roughness of a front edge portion of the atomic step to a height of the atomic step being 20% or less.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: November 27, 2018
    Assignee: AGC Inc.
    Inventors: Iori Yoshida, Satoshi Takemiya, Hiroyuki Tomonaga
  • Patent number: 10115501
    Abstract: This invention provides a substrate for a superconducting wire used for manufacturing a superconducting wire with excellent superconductivity and a method for manufacturing the same. Such substrate for a superconducting wire has crystal orientation of metals on the outermost layer, such as a c-axis orientation rate of 99% or higher and a ?? of 6 degrees or less, and a percentage of an area in which the crystal orientation is deviated by 6 degrees or more from the (001) [100] per unit area is 6% or less.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: October 30, 2018
    Assignees: Toyo Kohan Co., Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Teppei Kurokawa, Takashi Koshiro, Hironao Okayama
  • Patent number: 10100425
    Abstract: A large area nitride crystal, comprising gallium and nitrogen, with a non-polar or semi-polar large-area face, is disclosed, along with a method of manufacture. The crystal is useful as a substrate for a light emitting diode, a laser diode, a transistor, a photodetector, a solar cell, or for photoelectrochemical water splitting for hydrogen generation.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: October 16, 2018
    Assignee: SLT TECHNOLOGIES, INC.
    Inventors: Mark P. D'Evelyn, James S. Speck
  • Patent number: 10074536
    Abstract: Lattice-mismatched materials having configurations that trap defects within sidewall-containing structures.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Anthony J. Lochtefeld
  • Patent number: 10072335
    Abstract: A method of coating a metallic object with a substantially invisible protective coating, wherein the coating comprises a first layer, a second layer, and a third layer, each layer comprising a metal oxide or a nitride. The method comprises placing the object in an atomic layer deposition (ALD) reactor; depositing a first layer comprising a metal oxide or a nitride on a surface of the object by ALD; depositing a second layer comprising a metal oxide or a nitride on the first layer by ALD; and depositing a third layer comprising a metal oxide or a nitride on the second layer by ALD, thereby forming the protective coating on the object.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: September 11, 2018
    Assignees: University of Maryland, College Park, Trustees of the Walters Art Gallery, Inc.
    Inventors: Amy Elizabeth Marquardt, Eric Breitung, Raymond J. Phaneuf, Glenn Gates, Terry Weisser
  • Patent number: 10066312
    Abstract: A method for producing a mono-crystalline sheet includes providing at least two aperture elements forming a gap in between; providing a molten alloy including silicon in the gap; providing a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; providing a silicon nucleation crystal in the vicinity of the molten alloy; and bringing in contact said silicon nucleation crystal and the molten alloy. A device for producing a mono-crystalline sheet includes at least two aperture elements at a predetermined distance from each other, thereby forming a gap, and being adapted to be heated for holding a molten alloy including silicon by surface tension in the gap between the aperture elements; a precursor gas supply supplies a gaseous precursor medium comprising silicon in the vicinity of the molten alloy; and a positioning device for holding and moving a nucleation crystal in the vicinity of the molten alloy.
    Type: Grant
    Filed: September 12, 2016
    Date of Patent: September 4, 2018
    Assignee: International Business Machines Corporation
    Inventors: Mikael T. Bjoerk, Heike E. Riel, Heinz Schmid
  • Patent number: 10062598
    Abstract: In one embodiment, a susceptor for thermal processing is provided. The susceptor includes an outer rim surrounding and coupled to an inner dish, the outer rim having an inner edge and an outer edge. The susceptor further includes one or more structures for reducing a contacting surface area between a substrate and the susceptor when the substrate is supported by the susceptor. At least one of the one or more structures is coupled to the inner dish proximate the inner edge of the outer rim.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: August 28, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Anhthu Ngo, Zuoming Zhu, Balasubramanian Ramachandran, Paul Brillhart, Edric Tong, Anzhong Chang, Kin Pong Lo, Kartik Shah, Schubert S. Chu, Zhepeng Cong, James Francis Mack, Nyi O. Myo, Kevin Joseph Bautista, Xuebin Li, Yi-Chiau Huang, Zhiyuan Ye
  • Patent number: 10050166
    Abstract: A photovoltaic device including a single junction solar cell provided by an absorption layer of a type IV semiconductor material having a first conductivity, and an emitter layer of a type III-V semiconductor material having a second conductivity, wherein the type III-V semiconductor material has a thickness that is no greater than 50 nm.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: August 14, 2018
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoar-Tabari, Ali Khakifirooz, Devendra K. Sadana, Ghavam G. Shahidi, Davood Shahrjerdi
  • Patent number: 10044170
    Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.
    Type: Grant
    Filed: August 21, 2017
    Date of Patent: August 7, 2018
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring
  • Patent number: 10023974
    Abstract: A method of fabricating a composite semiconductor component comprising: (i) providing a bowed substrate comprising a wafer of synthetic diamond material having a thickness td, the bowed substrate being bowed by an amount B and comprising a convex face and a concave face; (ii) growing a layer of compound semiconductor material on the convex face of the bowed substrate via a chemical vapour deposition technique at a growth temperature T to form a bowed composite semiconductor component comprising the layer of compound semiconductor material of thickness tsc on the convex face of the bowed substrate, the compound semiconductor material having a higher average thermal expansion coefficient than the synthetic diamond material between the growth temperature T and room temperature providing a thermal expansion mismatch ?Tec; and (iii) cooling the bowed composite semiconductor component, wherein the layer of compound semiconductor material contracts more than the wafer of synthetic diamond material during cooling due
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: July 17, 2018
    Inventors: Timothy Mollart, Quanzhong Jiang, Michael John Edwards, Duncan Allsopp, Christopher Rhys Bowen, Wang Nang Wang
  • Patent number: 10002981
    Abstract: Solar cell structures including multiple sub-cells that incorporate different materials that may have different lattice constants. In some embodiments, solar cell devices include several photovoltaic junctions.
    Type: Grant
    Filed: November 29, 2012
    Date of Patent: June 19, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: James Fiorenza, Anthony J. Lochtefeld
  • Patent number: 9997458
    Abstract: Method for forming an interconnect structure, comprising the steps of: forming a recessed structure in a dielectric material on a substrate; at least partially filling said recessed structure with a metal chosen from the group consisting of copper, nickel and cobalt; introducing the substrate in a CVD reactor; bringing the substrate in the CVD reactor to a soak temperature and subsequently performing a soak treatment by supplying a germanium precursor gas to the CVD reactor at the soak temperature, thereby substantially completely converting the metal in the recessed structure to a germanide.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: June 12, 2018
    Assignee: IMEC vzw
    Inventors: Laure Elisa Carbonell, Antony Premkumar Peter, Marc Schaekers, Sven Van Elshocht, Zsolt Tokei
  • Patent number: 9957640
    Abstract: A single crystal diamond has a surface. In the single crystal diamond, a measurement region is defined in the surface, the measurement region includes a portion exhibiting a transmittance that is highest in the single crystal diamond and a portion exhibiting a transmittance that is lowest in the single crystal diamond, the measurement region has a plurality of square regions that are continuously arranged and each have a side having a length of 0.2 mm, and an average value of transmittances in each of the plurality of square regions is measured, wherein assuming that the average value of the transmittances in one square region is defined as T1 and the average value of the transmittances in another square region adjacent to the one square region is defined as T2, a relation of ((T1?T2)/((T1+T2)/2)×100)/0.2?20 (%/mm) is satisfied throughout the measurement region.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: May 1, 2018
    Assignees: Sumitomo Electric Industries, Ltd., Sumitomo Electric Hardmetal Corp.
    Inventors: Yoshiki Nishibayashi, Akihiko Ueda, Hitoshi Sumiya, Yutaka Kobayashi, Yuichiro Seki, Toshiya Takahashi
  • Patent number: 9947830
    Abstract: A patterned sapphire substrate has a first surface and a second surface opposite to each other; the connection zone between first protrusion portions has no C surface (i.e. (0001) surface); and the patterned sapphire substrate may have no C surface on the growth surface to reduce the threading dislocation density of the GaN epitaxial material on the sapphire substrate.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: April 17, 2018
    Assignee: XIAMEN SANAN OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Sheng-hsien Hsu, Gong Chen, Su-hui Lin, Yu-chieh Huang, Chen-ke Hsu
  • Patent number: 9899560
    Abstract: The present invention proposes a method to produce thin film CdTe solar cells having a pin-hole free and uniformly doped CdTe layer with a reduced layer thickness. The method according to the present invention is an efficient way to prevent shunting of the solar cells, to improve reliability and long-term stability of the solar cells and to provide a uniform doping of the CdTe layer. This is achieved by applying a sacrificial doping layer between a first CdTe layer having large grains and a second CdTe layer having small grains, which together form the CdTe layer of the solar cells. Furthermore it provides the possibility to eliminate the CdCl2 activation treatment step in case the sacrificial doping layer comprises a halogen.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: February 20, 2018
    Assignees: China Triumph International Engineering Co., Ltd., CTF Solar GmbH
    Inventors: Krishnakumar Velappan, Shou Peng
  • Patent number: 9881826
    Abstract: A buffer for use in semiconductor processing tools is disclosed. The buffer may be used to temporarily store wafers after processing operations are performed on those wafers. The buffer may include two side walls and a back wall interposed between the side walls. The side walls and the back wall may generally define an area within which the wafers may be stored in a stacked arrangement. Wafer support fins extending from the side walls and the back wall may extend into a wafer support region that overlaps with the edges of the wafers. Purge gas may be introduced in between each pair of wafers via purge gas ports located in one of the walls.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: January 30, 2018
    Assignee: Lam Research Corporation
    Inventors: Martin Robert Maraschin, Richard Howard Gould, Derek John Witkowicki
  • Patent number: 9853136
    Abstract: A directed epitaxial heterojunction bipolar transistor (HBT) structure is directly or indirectly formed on a GaAs substrate that is formed by a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, and includes a sub-collector layer, a collector, a base layer, an emitter layer, an emitter cap layer and an ohmic contact layer, which are sequentially formed on the substrate. A tunnel collector layer formed by InGaP or InGaAsP is provided between the collector layer and the base layer. Since an epitaxial process is performed on the substrate from a (100) face towards a (111)B face with an angle of inclination between 0.6° and 25°, indium and gallium contained in InGaP or InGaAsP are affected by the ordering effect such that InGaP or InGaAsP used in the emitter layer and/or the tunnel collector layer has a higher electron affinity or a smaller bandgap.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: December 26, 2017
    Assignee: VISUAL PHOTONICS EPITAXY CO., LTD.
    Inventors: Yu-Chung Chin, Chao-Hsing Huang, Min-Nan Tseng
  • Patent number: 9777402
    Abstract: A method of forming a layered OP material is provided, where the layered OP material comprises an OPGaAs template, and a layer of GaP on the OPGaAs template. The OPGaAs template comprises a patterned layer of GaAs having alternating features of inverted crystallographic polarity of GaAs. The patterned layer of GaAs comprises a first feature comprising a first crystallographic polarity form of GaAs having a first dimension, and a second feature comprising a second crystallographic polarity form of GaAs having a second dimension. The layer of GaP on the patterned layer of GaAs comprises alternating regions of inverted crystallographic polarity that generally correspond to their underlying first and second features of the patterned layer of GaAs. Additionally, each of the alternating regions of inverted crystallographic polarity of GaP are present at about 100 micron thickness or more.
    Type: Grant
    Filed: March 10, 2017
    Date of Patent: October 3, 2017
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: Vladimir L. Tassev, Rita D. Peterson
  • Patent number: 9780100
    Abstract: A method of forming a memory device that includes forming a sacrificial gate on a surface of a first source/drain region, and forming a channel opening through the sacrificial gate. The method may further include forming an epitaxial channel region is formed in the channel opening that is in situ doped to have an opposite conductivity type as the first of the source/drain region. A second source/drain region is formed on a portion of the epitaxial channel region opposite the portion of the epitaxial channel region that the first source/drain region is present on, wherein the second source/drain region has a same conductivity type as the conductivity type of the first source/drain region. A memory gate structure including a floating gate and a control gate is substituted for the sacrificial gate.
    Type: Grant
    Filed: September 23, 2016
    Date of Patent: October 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Pouya Hashemi, Tak H. Ning, Alexander Reznicek
  • Patent number: 9762032
    Abstract: In an example, the present invention provides a gallium and nitrogen containing multilayered structure, and related method. The structure has a plurality of gallium and nitrogen containing semiconductor substrates, each of the gallium and nitrogen containing semiconductor substrates (“substrates”) having a plurality of epitaxially grown layers overlaying a top-side of each of the substrates. The structure has an orientation of a reference crystal direction for each of the substrates. The structure has a first handle substrate coupled to each of the substrates such that each of the substrates is aligned to a spatial region configured in a selected direction of the first handle substrate, which has a larger spatial region than a sum of a total backside region of plurality of the substrates to be arranged in a tiled configuration overlying the first handle substrate. The reference crystal direction for each of the substrates is parallel to the spatial region in the selected direction within 10 degrees or less.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: September 12, 2017
    Assignee: Soraa Laser Diode, Inc.
    Inventors: Melvin McLaurin, Alexander Sztein, Po Shan Hsu, James W. Raring