Characterized By Specified Crystallography Or Arrangement Of Substrate (e.g., Wafer Cassette, Miller Index) Patents (Class 117/101)
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Patent number: 8258051Abstract: The present III-nitride crystal manufacturing method, a method of manufacturing a III-nitride crystal (20) having a major surface (20m) of plane orientation other than {0001}, designated by choice, includes: a step of slicing III-nitride bulk crystal (1) into a plurality of III-nitride crystal substrates (10p), (10q) having major surfaces (10pm), (10qm) of the designated plane orientation; a step of disposing the substrates (10p), (10q) adjoining each other sideways in such a way that the major surfaces (10pm), (10qm) of the substrates (10p), (10q) parallel each other and so that the [0001] directions in the substrates (10p), (10q) are oriented in the same way; and a step of growing III-nitride crystal (20) onto the major surfaces (10pm), (10qm) of the substrates (10p), (10q).Type: GrantFiled: May 17, 2009Date of Patent: September 4, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
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Patent number: 8226767Abstract: “Super-hetero-epitaxial” combinations comprise epitaxial growth of one material on a different material with different crystal structure. Compatible crystal structures may be identified using a “Tri-Unity” system. New bandgap engineering diagrams are provided for each class of combination, based on determination of hybrid lattice constants for the constituent materials in accordance with lattice-matching equations. Using known bandgap figures for previously tested materials, new materials with lattice constants that match desired substrates and have the desired bandgap properties may be formulated by reference to the diagrams and lattice matching equations. In one embodiment, this analysis makes it possible to formulate new super-hetero-epitaxial semiconductor systems, such as systems based on group IV alloys on c-plane LaF3; group IV alloys on c-plane langasite; Group III-V alloys on c-plane langasite; and group II-VI alloys on c-plane sapphire.Type: GrantFiled: October 20, 2008Date of Patent: July 24, 2012Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
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Patent number: 8221549Abstract: A silicon carbide single crystal wafer wherein a substrate is cut out at an OFF angle from a (0001) c plane of an ?-type silicon carbide single crystal of less than 2° and in an OFF direction in which a deviation from a (11-20) direction is less than 10°, the number of substantially triangular lamination defects exposed from a surface of a wafer which is epitaxial grown on the substrate is less than 4/cm2 over the entire surface of the wafer. The invention provides a producing method of a silicon carbide single crystal wafer capable of enhancing the utility ratio of the bulk silicon carbide single crystal, the element characteristics and the cleavage, as well as a silicon carbide single crystal wafer obtained by such a producing method.Type: GrantFiled: April 19, 2006Date of Patent: July 17, 2012Assignee: Bridgestone CorporationInventor: Takayuki Maruyama
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Patent number: 8221548Abstract: A process for producing a diamond thin-film includes forming a diamond crystal thin-film on a substrate and firing the diamond crystal thin-film at a sufficient temperature under high pressure under which a diamond is stable. A diamond single-crystal substrate having a diamond single-crystal thin-film formed thereon is placed in an ultra-high-pressure and high-temperature firing furnace to anneal the diamond single-crystal thin-film under the conditions of 1200° C. and 6 GPa.Type: GrantFiled: January 31, 2008Date of Patent: July 17, 2012Assignee: Nippon Telegraph and Telephone CorporationInventors: Makoto Kasu, Toshiki Makimoto, Kenji Ueda, Yoshiharu Yamauchi
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Patent number: 8216366Abstract: A cubic silicon carbide single crystal thin film is manufactured by a method. A sacrificial layer is formed on a surface of a substrate. A cubic semiconductor layer is formed on the sacrificial layer, the cubic semiconductor layer having at least a surface of cubic crystal structure. A cubic silicon carbide single crystal layer is formed on the cubic semiconductor layer. The sacrificial layer is etched away to release a multilayer structure of the cubic semiconductor layer and the 3C—SiC layer from the substrate. A cubic silicon carbide single crystal thin film of a multilayer structure includes an AlxGa1-xAs (0.6>x?0) layer and a cubic silicon carbide single crystal layer. A metal layer is formed on a substrate. The multilayer structure is bonded to the metal layer with the AlxGa1-xAs (0.6>x?0) in direct contact with the metal layer.Type: GrantFiled: April 27, 2010Date of Patent: July 10, 2012Assignee: Oki Data CorporationInventors: Mitsuhiko Ogihara, Masaaki Sakuta
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Patent number: 8197598Abstract: A method for making iron silicide nano-wires comprises the following steps. Firstly, providing a growing substrate and a growing device, the growing device comprising a heating apparatus and a reacting room. Secondly, placing the growing substrate and a quantity of iron powder into the reacting room. Thirdly, introducing a silicon-containing gas into the reacting room. Finally, heating the reacting room to a temperature of 600˜1200° C.Type: GrantFiled: November 6, 2008Date of Patent: June 12, 2012Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Hai-Lin Sun, Kai-Li Jiang, Qun-Qing Li, Shou-Shan Fan
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Publication number: 20120112320Abstract: A production process for a nitride semiconductor crystal, comprising growing a semiconductor layer on a seed substrate to obtain a nitride semiconductor crystal, wherein the seed substrate comprises a plurality of seed substrates made of the same material, at least one of the plurality of seed substrates differs in the off-angle from the other seed substrates, and a single semiconductor layer is grown by disposing the plurality of seed substrates in a semiconductor crystal production apparatus, such that when the single semiconductor layer is grown on the plurality of seed substrates, the off-angle distribution in the single semiconductor layer becomes smaller than the off-angle distribution in the plurality of seed substrates.Type: ApplicationFiled: December 1, 2011Publication date: May 10, 2012Applicant: MITSUBISHI CHEMICAL CORPORATIONInventors: Shuichi KUBO, Kenji Shimoyama, Kazumasa Kiyomi, Kenji Fujito, Yutaka Mikawa
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Publication number: 20120103250Abstract: There is provided an n type (100) oriented single crystal diamond semiconductor film into which phosphorous atoms have been doped and a method of producing the same. The n type (100) oriented single crystal diamond semiconductor film, characterized in that (100) oriented diamond is epitaxially grown on a substrate under such conditions that; the diamond substrate is (100) oriented diamond, a means for chemical vapor deposition provides hydrogen, hydrocarbon and a phosphorous compound in the plasma vapor phase, the ratio of phosphorous atoms to carbon atoms in the plasma vapor phase is no less than 0.1%, and the ratio of carbon atoms to hydrogen atoms is no less than 0.05%, and the method of producing the same.Type: ApplicationFiled: January 5, 2012Publication date: May 3, 2012Inventors: Hiromitsu KATO, Satoshi Yamasaki, Hideyo Ookushi, Shinichi Shikata
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Patent number: 8168000Abstract: A method of fabricating a III-nitride power semiconductor device which includes selective prevention of the growth of III-nitride semiconductor bodies to selected areas on a substrate in order to reduce stresses and prevent cracking.Type: GrantFiled: June 14, 2006Date of Patent: May 1, 2012Assignee: International Rectifier CorporationInventors: Mike Briere, Robert Beach
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Patent number: 8152919Abstract: An epitaxial silicon wafer is provided in which an epitaxial layer is grown on a silicon wafer having a plane inclined from a {110} plane of a silicon single crystal as a main surface. In the silicon wafer for growing the epitaxial layer thereon, an inclination angle azimuth of the {110} plane is in the range of 0 to 45 degrees as measured from a <100> orientation parallel to the {110} plane toward a <100> direction. With such an arrangement, LPDs of 100 nm or less can be measured from a {110} wafer that has a carrier mobility (including the hole and electron mobilities) higher than that of a {100} wafer. Also, surface roughness degradation in the {110} wafer can be suppressed. Also, the surface state of the {110} wafer can be measured. Further, a quality evaluation can be performed on the {110} wafer.Type: GrantFiled: June 20, 2011Date of Patent: April 10, 2012Assignee: Sumco CorporationInventors: Takayuki Dohi, Shinji Nakahara, Masaya Sakurai, Masato Sakai
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Patent number: 8147612Abstract: There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a gallium nitride crystal 79 at a growth temperature higher than 1,100° C. and equal to or lower than 1,300° C. so as to bury dislocation-concentrated regions or inverted-polarity regions 17a reduces dislocations inherited from the dislocation-concentrated regions or inverted regions 17a, thus preventing new dislocations from occurring over the dislocation-concentrated regions or inverted-polarity regions 17a. This also increases the crystallinity of the gallium nitride crystal 79 and its resistance to cracking during the polishing.Type: GrantFiled: April 24, 2007Date of Patent: April 3, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Tomoki Uemura, Takashi Sakurada, Shinsuke Fujiwara, Takuji Okahisa, Koji Uematsu, Hideaki Nakahata
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Patent number: 8133318Abstract: An epitaxially coated silicon wafer comprises a plane surface misoriented relative to a {110} crystal plane, wherein the <110> direction of the single silicon crystal is tilted away by the angle ? from the normal to the wafer surface and the projection of the tilted <110> direction forms an angle ? with the direction <?110> in the wafer, and ? is given by 0???3° and 45°???90°, as well as for all symmetrically equivalent directions.Type: GrantFiled: May 26, 2009Date of Patent: March 13, 2012Assignee: Siltronic AGInventors: Erich Daub, Hans Oelkrug, Oliver Schmelmer
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Patent number: 8128756Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {10 11} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {10 13 } gallium nitride (GaN) grown on a {110} spinel substrate, (3) {11 22} gallium nitride (GaN) grown on a {1 100} sapphire substrate, and (4) {10 13} gallium nitride (GaN) grown on a {1 100} sapphire substrate.Type: GrantFiled: February 1, 2010Date of Patent: March 6, 2012Assignees: The Regents of the University of California, Japan Science and Technology AgencyInventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
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Patent number: 8119505Abstract: A method of making a group III nitride-based compound semiconductor includes providing a semiconductor substrate comprising group III nitride-based compound semiconductor, polishing a surface of said semiconductor substrate such that said polished surface includes an inclined surface that has an off-angle ? of 0.15 degrees or more and 0.6 degrees or less to one of an a-face, a c-face and an m-face of the semiconductor substrate, providing a stripe-shaped specific region on the polished surface, the specific region comprising a material that prevents the growth of the group III nitride-based compound semiconductor on its surface, and growing a semiconductor epitaxial growth layer of group III nitride-based compound semiconductor on the polished surface of the semiconductor substrate.Type: GrantFiled: March 2, 2010Date of Patent: February 21, 2012Assignees: Toyoda Gosei Co., Ltd., Sumitomo Electric Industries, Ltd.Inventor: Ryo Nakamura
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Patent number: 8118934Abstract: A method for growing flat, low defect density, and strain-free thick non-polar III-V nitride materials and devices on any suitable foreign substrates using a fabricated nano-pores and nano-network compliant layer with an HVPE, MOCVD, and integrated HVPE/MOCVD growth process in a manner that minimum growth will occur in the nano-pores is provided. The method produces nano-networks made of the non-polar III-V nitride material and the substrate used to grow it where the network is continuous along the surface of the template, and where the nano-pores can be of any shape.Type: GrantFiled: September 26, 2007Date of Patent: February 21, 2012Inventor: Wang Nang Wang
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Patent number: 8088222Abstract: A novel approach for the growth of high-quality on-axis epitaxial silicon carbide (SiC) films and boules, using the Chemical Vapor Deposition (CVD) technique, is described here. The method includes a method of substrate preparation, which allows for the growth of “on-axis” SiC films, plus an approach giving the opportunity to grow silicon carbide on singular (a small-angle miscut) substrates, using halogenated carbon-containing precursors (carbon tetrachloride, CCl4, or halogenated hydrocarbons, CHCl3, CH2Cl2, or CH3Cl, or similar compounds or chemicals), or introducing other chlorine-containing species, in the gas phase, in the growth chamber. At gas mixtures greater than the critical amount, small clusters of SiC are etched, before they can become stable nuclei. The presence of chlorine and the formation of gas species allow an increased removal rate of these nuclei, in contrast to the growth without the presence of chlorine.Type: GrantFiled: July 27, 2007Date of Patent: January 3, 2012Assignee: Widetronix Inc.Inventors: Yuri Makarov, Michael Spencer
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Publication number: 20110300058Abstract: The present invention relates to a method for manufacturing graphene by vapour phase epitaxy on a substrate comprising a surface of SiC, characterized in that the process of sublimation of silicon from the substrate is controlled by a flow of an inert gas or a gas other than an inert gas through the epitaxial reactor. The invention also relates to graphene obtained by this method.Type: ApplicationFiled: June 7, 2011Publication date: December 8, 2011Applicant: INSTYTUT TECHNOLOGII MATERIALOW ELEKTRONICZNYCHInventor: Wlodzimierz Strupinski
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Publication number: 20110290175Abstract: A multi-chamber CVD system includes a plurality of substrate carriers where each substrate carrier is adapted to support at least one substrate. A plurality of enclosures are each configured to form a deposition chamber enclosing one of the plurality of substrate carriers to maintain an independent chemical vapor deposition process chemistry for performing a processing step. A transport mechanism transports each of the plurality of substrate carriers to each of the plurality of enclosures in discrete steps that allow processing steps to be performed in the plurality of enclosures for a predetermined time. In some embodiments, the substrate carrier can be rotatable.Type: ApplicationFiled: July 18, 2011Publication date: December 1, 2011Applicant: VEECO INSTRUMENTS, INC.Inventors: Ajit Paranjpe, Eric A. Armour, William E. Quinn
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Publication number: 20110280790Abstract: The invention relates to single crystal diamond with optical quality and methods of making the same. The diamond possesses an intensity ratio of the second-order. Raman peak to the fluorescence background of around 5 or greater.Type: ApplicationFiled: May 17, 2011Publication date: November 17, 2011Applicant: Carnegie Institution of WashingtonInventors: Russell J. Hemley, Yu-fei Meng, Chih-Shiue Yan, Ho-kwang Mao
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Patent number: 8043429Abstract: The present invention relates to a method for fabricating a filament type high-temperature superconducting wire in which a thin film type high-temperature superconducting wire is fabricated into a filament shape suitable for use with alternating current.Type: GrantFiled: March 28, 2007Date of Patent: October 25, 2011Assignee: Korea Polytechnic UniversityInventors: Hee Gyoun Lee, Gye Won Hong, Kyeong Dal Choi
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Patent number: 8038795Abstract: A precursor chiral nanotube with a specified chirality is grown using an epitaxial process and then cloned. A substrate is provided of crystal material having sheet lattice properties complementary to the lattice properties of the selected material for the nanotube. A cylindrical surface(s) having a diameter of 1 to 100 nanometers are formed as a void in the substrate or as crystal material projecting from the substrate with an orientation with respect to the axes of the crystal substrate corresponding to the selected chirality. A monocrystalline film of the selected material is epitaxially grown on the cylindrical surface that takes on the sheet lattice properties and orientation of the crystal substrate to form a precursor chiral nanotube. A catalytic particle is placed on the precursor chiral nanotube and atoms of the selected material are dissolved into the catalytic particle to clone a chiral nanotube from the precursor chiral nanotube.Type: GrantFiled: July 16, 2008Date of Patent: October 18, 2011Assignee: Raytheon CompanyInventors: Delmar L. Barker, William R. Owens
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Patent number: 7998273Abstract: An epitaxial growth process for producing a thick III-N layer, wherein III denotes at least one element of group III of the periodic table of elements, is disclosed, wherein a thick III-N layer is deposited above a foreign substrate. The epitaxial growth process preferably is carried out by HVPE. The substrate can also be a template comprising the foreign substrate and at least one thin III-N intermediate layer. The surface quality is improved by providing a slight intentional misorientation of the substrate, and/or a reduction of the N/III ratio and/or the reactor pressure towards the end of the epitaxial growth process. Substrates and semiconductor devices with such improved III-N layers are also disclosed.Type: GrantFiled: May 5, 2006Date of Patent: August 16, 2011Assignees: Freiberger Compound Materials GmbH, Osram Opto Semiconductors GmbHInventors: Ferdinand Scholz, Peter Brückner, Frank Habel, Matthias Peter, Klaus Köhler
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Publication number: 20110179993Abstract: A nitride semiconductor layer formation method includes the steps of: (S1) placing a substrate in a reaction chamber, the substrate including an m-plane nitride semiconductor crystal at least in an upper surface; (S2) increasing a temperature of the substrate by heating the substrate placed in the reaction chamber; and (S3) growing a nitride semiconductor layer on the substrate. In the temperature increasing step (S2), a nitrogen source gas and a Group III element source gas are supplied into the reaction chamber, whereby an m-plane nitride semiconductor crystal having a smooth surface can be formed even if the thickness of the layer is 400 nm, and its growth time can be greatly decreased.Type: ApplicationFiled: November 26, 2009Publication date: July 28, 2011Inventors: Akira Inoue, Ryou Kato, Masaki Fujikane, Toshiya Yokogawa
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Publication number: 20110168082Abstract: A manufacturing method of a group III nitride semiconductor crystal is provided, comprising: the step of preparing a seed crystal; and the convex surface growing step of growing the group III nitride semiconductor crystal, with a growth surface of the group III nitride semiconductor crystal constituted only by a plurality of surfaces not vertical to a growth direction, and the growth surface constituted of the plurality of surfaces formed into a convex shape as a whole.Type: ApplicationFiled: June 16, 2010Publication date: July 14, 2011Applicant: HITACHI CABLE, LTD.Inventor: Yuichi Oshima
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Publication number: 20110150745Abstract: A method of producing a grown single crystal diamond substrate comprising: (a) providing a first diamond substrate which presents a (001) major surface, which major surface is bounded by at least one <100> edge, the length of the said at least one <100> edge exceeding any dimension of the surface that is orthogonal to the said at least one <100> edge by a ratio of at least 1.3:1; and (b) growing diamond material homoepitaxially on the (001) major surface of the diamond material surface under chemical vapour deposition (CVD) synthesis conditions, the diamond material growing both normal to the major (001) surface, and laterally therefrom.Type: ApplicationFiled: December 15, 2010Publication date: June 23, 2011Inventors: Daniel James Twitchen, Harpreet Kaur Dhillon, Geoffrey Alan Scarsbrook
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Publication number: 20110129669Abstract: A method for efficiently producing a plate-like nitride semiconductor crystal having the desired principal plane in a simple method is provided. A raw material gas is fed to a seed crystal in which a ratio (L/W) of length L in a longitudinal direction and maximum width W, of a plane of projection obtained by projecting a crystal growth face on the seed crystal in a growth direction is from 2 to 400, and the maximum width W is 5 mm or less, thereby growing a plate-like semiconductor crystal on the seed crystal.Type: ApplicationFiled: March 2, 2009Publication date: June 2, 2011Applicant: Mitsubishi Chemical CorporationInventors: Kenji Fujito, Shuichi Kubo, Yoko Mashige
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Patent number: 7942966Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.Type: GrantFiled: October 29, 2004Date of Patent: May 17, 2011Assignee: Apollo Diamond, Inc.Inventors: Robert C. Linares, Patrick J. Doering
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Publication number: 20110089431Abstract: A method for producing a compound single crystal includes a process (I) of growing the compound single crystal while causing an anti-phase boundary and a stacking fault to equivalently occur in a <110> direction parallel to the surface, the stacking fault being attributable to the elements A and B; a process (II) of merging and annihilating the stacking fault, attributable to the element A, and the anti-phase boundary, which occurs in the process (I); a process (III) of vanishing the stacking fault attributable to the element B, which occurs in the process (I); and a process (IV) of completely merging and annihilating the anti-phase boundary. The process (IV) is carried out simultaneously with the processes (II) and (III) or after the processes (II) and (III).Type: ApplicationFiled: October 15, 2010Publication date: April 21, 2011Applicant: HOYA CORPORATIONInventors: Kuniaki YAGI, Takahisa SUZUKI, Yasutaka YANAGISAWA, Masao HIROSE, Noriko SATO, Junya KOIZUMI, Hiroyuki NAGASAWA
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Patent number: 7910462Abstract: An assembly and method of making the same wherein the assembly incorporates a rare-earth oxide film to form a [110] crystal lattice orientation semiconductor film. The assembly comprises a substrate, a rare-earth oxide film formed on the substrate, and a [110]-oriented semiconductor film formed on the rare-earth oxide film. The rare-earth oxide film having a [110] crystal lattice orientation. The substrate has a [001] crystal lattice orientation.Type: GrantFiled: October 16, 2006Date of Patent: March 22, 2011Assignee: Intel CorporationInventor: Maxim B. Kelman
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Publication number: 20110056429Abstract: A method for rapid growth of gallium and nitrogen containing material is described. The method includes providing a bulk gallium and nitrogen containing substrate. A first epitaxial material of first thickness is formed over the substrate, preferably with a pseudomorphical process. The method also forms a second epitaxial layer over the first to create a stacked structure. The stacked structure consists of a total thickness of less than about 2 microns.Type: ApplicationFiled: August 18, 2010Publication date: March 10, 2011Applicant: Soraa, Inc.Inventors: James Raring, Arpan Chakraborty, Christiane Poblenz
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Patent number: 7892356Abstract: It is an object of the present invention to provide a diamond substrate with high toughness, a large surface area, and high quality, for use in semiconductor materials, electronic components, optical components, and so forth, and a method for manufacturing this substrate. A diamond polycrystalline film is laminated on the surface of a diamond monocrystalline substrate to create a diamond composite substrate. In said diamond composite substrate, it is preferable that the main face, which has the largest surface area of the diamond monocrystalline substrate, be the {100} plane, and the diamond polycrystalline film be laminated on the opposite face parallel to this face. The diamond monocrystalline substrate 3 may be made up of a plurality of diamond monocrystals having the same orientation of the main face, and these plurality of diamond monocrystals may be joined by a diamond crystal layer 4 to create a diamond composite substrate 2.Type: GrantFiled: January 22, 2004Date of Patent: February 22, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kiichi Meguro, Yoshiyuki Yamamoto, Takahiro Imai
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Patent number: 7857907Abstract: The present invention relates to a method for forming a layered structure with silicon nanocrystals. In one embodiment, the method comprises the steps of: (i) forming a first conductive layer on a substrate, (ii) forming a silicon-rich dielectric layer on the first conductive layer, and (iii) laser-annealing at least the silicon-rich dielectric layer to induce silicon-rich aggregation to form a plurality of silicon nanocrystals in the silicon-rich dielectric layer. The silicon-rich dielectric layer is one of a silicon-rich oxide film having a refractive index in the range of about 1.4 to 2.3, or a silicon-rich nitride film having a refractive index in the range of about 1.7 to 2.3. The layered structure with silicon nanocrystals in a silicon-rich dielectric layer is usable in a solar cell, a photodetector, a touch panel, a non-volatile memory device as storage node, and a liquid crystal display.Type: GrantFiled: January 25, 2007Date of Patent: December 28, 2010Assignee: AU Optronics CorporationInventors: An-Thung Cho, Chih-Wei Chao, Chia-Tien Peng, Wan-Yi Liu, Ming-Wei Sun
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Patent number: 7842134Abstract: The invention relates to a method of manufacture of a substrate for fabrication of semiconductor layers or devices, comprising the steps of providing a wafer of silicon including at least one first surface suitable for use as a substrate for CVD diamond synthesis, growing a layer of CVD diamond of predetermined thickness and having a growth face onto the first surface of the silicon wafer, reducing the thickness of the silicon wafer to a predetermined level, and providing a second surface on the silicon wafer that is suitable for further synthesis of at least one semiconductor layer suitable for use in electronic devices or synthesis of electronic devices on the second surface itself and to a substrate suitable for GaN device growth consisting of a CVD diamond layer intimately attached to a silicon surface.Type: GrantFiled: March 20, 2006Date of Patent: November 30, 2010Inventors: Andrew John Whitehead, Christopher John Howard Wort, Geoffrey Alan Scarsbrook
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Patent number: 7830027Abstract: The invention relates to inter-level realignment after a stage of epitaxy on a face (31) of a substrate (30), comprising the production of at least one initial guide mark (32) on the face of the substrate, this initial guide mark being designed so as to be transferred, during epitaxy, onto the surface of the epitaxied layer (36). The initial guide mark (32) is produced in such a way that, during epitaxy, its edges create growth defects that propagate as far as the surface of the epitaxied layer (36) to provide a transferred guide mark (37) on the surface of the epitaxied layer (36) reproducing the shape of the initial guide mark (32) and in alignment with the initial guide mark.Type: GrantFiled: April 20, 2005Date of Patent: November 9, 2010Assignees: Commissariat a l'Energie Atomique, Freescale Semiconductor, Inc.Inventors: Bernard Diem, Eugene Blanchet, Bishnu Gogoi
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Publication number: 20100275837Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.Type: ApplicationFiled: June 2, 2010Publication date: November 4, 2010Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, JAPAN SCIENCE AND TECHNOLOGY AGENCYInventors: Tadao Hashimoto, Hitoshi Sato, Shuji Nakamura
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Patent number: 7824493Abstract: A method for manufacturing a silicon wafer includes a step of annealing a silicon wafer which is sliced from a silicon single crystal ingot, thereby forming a DZ layer in a first surface and in a second surface of the silicon wafer and a step of removing either a portion of the DZ layer in the first surface or a portion of the DZ layer in the second surface.Type: GrantFiled: July 20, 2005Date of Patent: November 2, 2010Assignee: Sumitomo Mitsubishi Silicon CorporationInventors: Toshiaki Ono, Wataru Sugimura, Masataka Hourai
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Publication number: 20100269887Abstract: A crystallographically textured metallic substrate includes surfaces for connection and for receiving a thin layer deposit, and is made up of an alloy presenting a cubic crystalline system with centered faces and a predominantly cubic crystallographic texture {100}<001>, the receiving surface including grains mainly presenting crystallographic planes {100} parallel to the receiving surface. The alloy is iron-nickel with weight % relative to total weight: Ni?30%, Cu?15%, Cr?15%, Co?12%, Mn?5%, S<0.0007%, P<0.003%, B<0.0005%, Pb<0.0001%, and in the alloy: 34%?(Ni+Cr+Cu/2+Co/2+Mn). The alloy includes up to 1% in weight of one or several deoxidizing elements chosen among silicon, magnesium, aluminium and calcium, the rest of the elements in the alloy being iron and impurities.Type: ApplicationFiled: August 28, 2008Publication date: October 28, 2010Applicants: ARCELORMITTAL-STAINLESS AND NICKEL ALLOYS, ECOLE POLYTECHNIQUEInventors: Jean-Pierre Reyal, Pierre-Louis Reydet, Pere Roca Cabarrocas, Yassine Djeridane
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Publication number: 20100263707Abstract: The structure presented herein provides a base structure for semiconductor devices, in particular for III-V semiconductor devices or for a combination of III-V and Group IV semiconductor devices. The fabrication method for a base substrate comprises a buffer layer, a nucleation layer, a Group IV substrate and possibly a dopant layer. There are, in a general aspect, two growth steps: firstly the growth of a lattice-matched III-V material on a Group IV substrate, followed by secondly the growth of a lattice-mismatched III-V layer. The first layer, called the nucleation layer, is lattice-matched or closely lattice-matched to the Group IV substrate while the following layer, the buffer layer, deposited on top of the nucleation layer, is lattice-mismatched to the nucleation layer. The nucleation layer can further be used as a dopant source to the Group IV substrate, creating a p-n junction in the substrate through diffusion. Alternatively a separate dopant layer may be introduced.Type: ApplicationFiled: April 16, 2010Publication date: October 21, 2010Inventors: Dan Daeweon Cheong, Rafael Nathan Kleiman, Manuela Peter, Nicholas Komarnycky, Bradley Joseph Robinson, John Stewart Preston
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Patent number: 7811382Abstract: A wafer having a silicon layer that is strained is used to form transistors. The silicon layer is formed by first forming a silicon germanium (SiGe) layer of at least 30 percent germanium that has relaxed strain on a donor wafer. A thin silicon layer is epitaxially grown to have tensile strain on the relaxed SiGe layer. The amount tensile strain is related to the germanium concentration. A high temperature oxide (HTO) layer is formed on the thin silicon layer by reacting dichlorosilane and nitrous oxide at a temperature of preferably between 800 and 850 degrees Celsius. A handle wafer is provided with a supporting substrate and an oxide layer that is then bonded to the HTO layer. The HTO layer, being high density, is able to hold the tensile strain of the thin silicon layer. The relaxed SiGe layer is cleaved then etched away to expose the thin silicon layer.Type: GrantFiled: May 30, 2006Date of Patent: October 12, 2010Assignee: Freescale Semiconductor, Inc.Inventors: Mariam G. Sadaka, Alexander L. Barr, Bich-Yen Nguyen, Voon-Yew Thean, Ted R. White
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Patent number: 7804019Abstract: A substrate is provided including a growth surface that is offcut relative to a plane defined by a crystallographic orientation of the substrate at an offcut angle of about 5 degrees to about 45 degrees. A thermoelectric film is epitaxially grown on the growth surface. A crystallographic orientation of the thermoelectric film may be tilted about 5 degrees to about 30 degrees relative to the growth surface. The growth surface of the substrate may also be patterned to define a plurality of mesas protruding therefrom prior to epitaxial growth of the thermoelectric film. Related methods and thermoelectric devices are also discussed.Type: GrantFiled: February 1, 2008Date of Patent: September 28, 2010Assignee: Nextreme Thermal Solutions, Inc.Inventors: Jonathan Pierce, Robert P. Vaudo
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Publication number: 20100229789Abstract: A thin-film single crystal growing method includes preparing a substrate, irradiating an excitation beam on a metallic target made of a pure metal or an alloy in a predetermined atmosphere, and combining chemical species including any of atoms, molecules, and ions released from the metallic target by irradiation of the excitation beam with atoms contained in the predetermined atmosphere to form a thin film on the substrate.Type: ApplicationFiled: March 15, 2010Publication date: September 16, 2010Applicant: Waseda UniversityInventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki
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Patent number: 7794543Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: February 13, 2008Date of Patent: September 14, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
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Patent number: 7790584Abstract: A method of growing a semi-polar nitride single crystal thin film. The method includes forming a semi-polar nitride single crystal base layer on an m-plane hexagonal system single crystal substrate, forming a dielectric pattern layer on the semi-polar nitride single crystal base layer, and growing the semi-polar nitride single crystal thin film on the semi-polar nitride single crystal base layer having the dielectric pattern layer in a lateral direction. The growing of the semi-polar nitride single crystal thin film in a lateral direction includes primarily growing the semi-polar nitride single crystal thin film in the lateral direction such that part of a growth plane on the semi-polar nitride single crystal base layer has an a-plane, and secondarily growing the semi-polar nitride single crystal thin film in the lateral direction such that sidewalls of the primarily grown semi-polar nitride single crystal thin film are combined to have a (11 22) plane.Type: GrantFiled: October 7, 2008Date of Patent: September 7, 2010Assignee: Samsung Led Co., Ltd.Inventors: Ho Sun Paek, Jeong Wook Lee, Youn Joon Sung
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Publication number: 20100175613Abstract: The present invention is a base material for forming a single crystal diamond comprising, at least, a seed base material of a single crystal and a thin film heteroepitaxially grown on the seed base material, wherein the seed base material is a single crystal diamond and the thin film is Iridium film or Rhodium film. As a result, there is provided a base material for forming a single crystal diamond that enables a single crystal diamond having a high crystallinity to be heteroepitaxially grown thereon and that can be reused repeatedly and a method for producing a single crystal diamond that enables a single crystal diamond having a high crystallinity and a large area to be produced at low cost.Type: ApplicationFiled: November 23, 2009Publication date: July 15, 2010Applicant: SHIN-ETSU CHEMICAL CO., LTD.Inventor: Hitoshi Noguchi
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Patent number: 7745854Abstract: It is to provide a substrate for growing a semiconductor, which is effective for suppressing an occurrence of surface defects different in type from hillock defects in case of epitaxially growing a compound semiconductor layer, particularly an Al-based compound semiconductor layer. In a substrate for growing a compound semiconductor, in which a crystal surface inclined at a predetermined off angle with respect to a (100) plane is a principal plane, an angle made by a direction of a vector obtained by projecting a normal vector of the principal plane on the (100) plane and one direction of a [0-11] direction, a [01-1] direction, a [011] direction and a [0-1-1] direction is set to be less than 35°, and the compound semiconductor layer is epitaxially grown on the substrate.Type: GrantFiled: February 2, 2007Date of Patent: June 29, 2010Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Hideki Kurita, Ryuichi Hirano
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Patent number: 7736435Abstract: A method for producing a single crystals by preferential epitaxial growth of {100} face, comprising the steps of (1) growing the crystal on a single crystal {100} substrate; (2) forming on the side of the grown crystal a surface parallel to a {100} face different from the {100}face in the growth direction, and (3) growing the crystal on the formed {100} surface; and the steps (2) and (3) being performed once or more than once. A method for producing a single-crystal diamond using a metallic holder for the single-crystal diamond having a crystal holding portion which is raised above an outer peripheral portion of the holder, is part from the outer peripheral portion of the holder, and has a recessed shape. The methods enable the production of a large single-crystal diamond in a comparatively short time at low cost.Type: GrantFiled: November 16, 2005Date of Patent: June 15, 2010Assignee: National Institute of Advanced Industrial Science and TechnologyInventors: Yoshiaki Mokuno, Akiyoshi Chayahara, Yuji Horino, Naoji Fujimori
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Publication number: 20100119849Abstract: In one embodiment of the present invention, a monocrystal SiC epitaxial substrate is produced which includes a monocrystal SiC substrate; a buffer layer made of a first SiC epitaxial film formed on the monocrystal SiC substrate; and an active layer made of a second SiC epitaxial film formed on the buffer layer. The buffer layer is grown by heat-treating a set of the monocrystal SiC substrate, a carbon source plate, and a metal Si melt layer having a predetermined thickness and interposed between the monocrystal SiC substrate and the metal Si melt layer, so as to epitaxially grow monocrystal SiC on the monocrystal SiC substrate. The active layer is grown by epitaxially growing monocrystal SiC on the buffer layer by vapor phase growth method. This allows for production of a monocrystal SiC epitaxial substrate including a high-quality monocrystal SiC active layer being low in defects.Type: ApplicationFiled: March 11, 2008Publication date: May 13, 2010Inventors: Nobuhiko Nakamura, Toru Matsunami, Kimito Nishikawa
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Patent number: 7713353Abstract: A method for growing a ?-Ga2O3 single includes preparing a ?-Ga2O3 seed crystal and growing the ?-Ga2O3 single crystal from the ?-Ga2O3 seed crystal in a predetermined direction.Type: GrantFiled: June 12, 2008Date of Patent: May 11, 2010Assignee: Waseda UniversityInventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
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Patent number: 7686885Abstract: In some embodiments, the present invention addresses the challenges of fabricating nanorod arrays comprising a heterogeneous composition and/or arrangement of the nanorods. In some embodiments, the present invention is directed to multicomponent nanorod arrays comprising nanorods of at least two different chemical compositions, and to methods of making same. In some or other embodiments, the nanorods are spatially positioned within the array in a pre-defined manner.Type: GrantFiled: June 1, 2005Date of Patent: March 30, 2010Assignee: General Electric CompanyInventors: Anthony Yu-Chung Ku, Reed Roeder Corderman, Krzysztof Slowinski
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Patent number: RE41503Abstract: The first object of the present invention is to provide a PDP with improved panel brightness which is achieved by improving the efficiency in conversion from discharge energy to visible rays. The second object of the present invention is to provide a PDP with improved panel life which is achieved by improving the protecting layer protecting the dielectrics glass layer. To achieve the first object, the present invention sets the amount of xenon in the discharge gas to the range of 10% by volume to less than 100% by volume, and sets the charging pressure for the discharge gas to the range of 500 to 760 Torr which is higher than conventional charging pressures. With such construction, the panel brightness increases. Also, to achieve the second object, the present invention has, on the surface of the dielectric glass layer, a protecting layer consisting of an alkaline earth oxide with (100)-face or (110)-face orientation.Type: GrantFiled: May 18, 2006Date of Patent: August 17, 2010Assignee: Panasonic CorporationInventors: Masaki Aoki, Hideo Torii, Eiji Fujii, Mitsuhiro Ohtani, Takashi Inami, Hiroyuki Kawamura, Hiroyoshi Tanaka, Ryuichi Murai, Yasuhisa Ishikura, Yutaka Nishimura, Katsuyoshi Yamashita, Yasuko Nishimura, Syunsuke Nishimura, Emi Kawahara