Characterized By Specified Crystallography Or Arrangement Of Substrate (e.g., Wafer Cassette, Miller Index) Patents (Class 117/101)
  • Patent number: 8888914
    Abstract: The object is to provide a photoelectric surface member which allows higher quantum efficiency. In order to achieve this object, a photoelectric surface member 1a is a crystalline layer formed by a nitride type semiconductor material, and comprises a nitride semiconductor crystal layer 10 where the direction from the first surface 101 to the second surface 102 is the negative c polar direction of the crystal, an adhesive layer 12 formed along the first surface 101 of the nitride semiconductor crystal layer 10, and a glass substrate 14 which is adhesively fixed to the adhesive layer 12 such that the adhesive layer 12 is located between the glass substrate 14 and the nitride semiconductor crystal layer 10.
    Type: Grant
    Filed: April 16, 2010
    Date of Patent: November 18, 2014
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Tokuaki Nihashi, Masatomo Sumiya, Minoru Hagino, Shunro Fuke
  • Patent number: 8882909
    Abstract: Relaxed germanium buffer layers can be grown economically on misoriented silicon wafers by low-energy plasma-enhanced chemical vapor deposition. In conjunction with thermal annealing and/or patterning, the buffer layers can serve as high-quality virtual substrates for the growth of crack-free GaAs layers suitable for high-efficiency solar cells, lasers and field effect transistors.
    Type: Grant
    Filed: May 2, 2005
    Date of Patent: November 11, 2014
    Assignee: Dichroic Cell S.R.L.
    Inventor: Hans Von Kaenel
  • Patent number: 8876973
    Abstract: There is provided an n type (100) oriented single crystal diamond semiconductor film into which phosphorous atoms have been doped and a method of producing the same. The n type (100) oriented single crystal diamond semiconductor film, characterized in that (100) oriented diamond is epitaxially grown on a substrate under such conditions that; the diamond substrate is (100) oriented diamond, a means for chemical vapor deposition provides hydrogen, hydrocarbon and a phosphorous compound in the plasma vapor phase, the ratio of phosphorous atoms to carbon atoms in the plasma vapor phase is no less than 0.1%, and the ratio of carbon atoms to hydrogen atoms is no less than 0.05%, and the method of producing the same.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: November 4, 2014
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Hiromitsu Kato, Satoshi Yamasaki, Hideyo Ookushi, Shinichi Shikata
  • Patent number: 8852342
    Abstract: A surface of a single crystalline semiconductor-carbon alloy layer having a surface normal along or close to a major crystallographic direction is provided by mechanical means such as cutting and/or polishing. Such a surface has naturally formed irregular surface features. Small semiconductor islands are deposited on the surface of single crystalline semiconductor-carbon alloy layer. Another single crystalline semiconductor-carbon alloy structure may be placed on the small semiconductor islands, and the assembly of the two semiconductor-carbon alloy layers with the semiconductor islands therebetween is annealed. During the initial phase of the anneal, surface diffusion of the semiconductor material proceeds to form vicinal surfaces while graphitization is suppressed because the space between the two semiconductor-carbon alloy layers maintains a high vapor pressure of the semiconductor material.
    Type: Grant
    Filed: August 30, 2010
    Date of Patent: October 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Christos D. Dimitrakopoulos, Marcus O. Freitag, Alfred Grill, Robert L. Wisnieff
  • Patent number: 8846504
    Abstract: A method of growing GaN material on a silicon substrate includes providing a single crystal silicon substrate with a (100) surface orientation or a (100) with up to a 10° offset surface orientation and using epi-twist technology, epitaxially growing a single crystal stress managing layer on the silicon substrate. The single crystal stress managing layer includes rare earth oxide with a (110) crystal orientation and a cubic crystal structure. The method further includes epitaxially growing a single crystal buffer layer on the stress managing layer. The single crystal buffer layer includes rare earth oxide with a lattice spacing closer to a lattice spacing of GaN than the rare earth oxide of the stress managing layer. Epitaxially growing a layer of single crystal GaN material on the surface of the buffer, the GaN material having one of a (11-20) crystal orientation and a (0001) crystal orientation.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: September 30, 2014
    Assignee: Translucent, Inc.
    Inventors: Rytis Dargis, Andrew Clark, Erdem Arkun, Radek Roucka
  • Patent number: 8840723
    Abstract: An apparatus for manufacturing polycrystalline silicon whereby raw-material gas is supplied to one or more heated silicon seed rods provided vertically in a reactor so as to deposit the polycrystalline silicon on a surface of the silicon seed rod, having a seed rod holding member, made of conductive material, having a holding hole in which a lower end of the silicon seed rod is inserted, the holding hole having a horizontal cross-sectional shape with at least two corners, and the holding member having a screw hole extending from the outer surface of the seed rod holding member to at least the holding hole and formed at the location of at least two corners of the holding hole; and a fixing screw which fixes the silicon seed rod and is threaded through at least one of the screw holes.
    Type: Grant
    Filed: March 5, 2010
    Date of Patent: September 23, 2014
    Assignee: Mitsubishi Materials Corporation
    Inventors: Toshihide Endoh, Masayuki Tebakari, Toshiyuki Ishii, Masaaki Sakaguchi
  • Patent number: 8828140
    Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: September 9, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
  • Patent number: 8821635
    Abstract: Si—Ge materials are grown on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relaxed, and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides for precise control of morphology, composition, structure and strain. The grown materials possess the required characteristics for high frequency electronic and optical applications, and for templates and buffer layers for high mobility Si and Ge channel devices.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: September 2, 2014
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: John Kouvetakis, Ignatius S. T. Tsong, Changwu Hu, John Tolle
  • Patent number: 8795430
    Abstract: A method for improving the growth morphology of (Ga,Al,In,B)N thin films on nonpolar or semipolar (Ga,Al,In,B)N substrates, wherein a (Ga,Al,In,B)N thin film is grown directly on a nonpolar or semipolar (Ga,Al,In,B)N substrate or template and a portion of the carrier gas used during growth is comprised of an inert gas. Nonpolar or semipolar nitride LEDs and diode lasers may be grown on the smooth (Ga,Al,In,B)N thin films grown by the present invention.
    Type: Grant
    Filed: March 2, 2010
    Date of Patent: August 5, 2014
    Assignee: The Regents of the University of California
    Inventors: Robert M. Farrell, Michael Iza, James S. Speck, Steven P. DenBaars, Shuji Nakamura
  • Patent number: 8778513
    Abstract: An article including a perovskite manganese (Mn) oxide thin film, includes a substrate having an oriented perovskite structure that is (m10) oriented, where 19?m?2, and having an [100] axis direction; and a perovskite manganese (Mn) oxide thin film having a perovskite crystal lattice containing barium Ba and a rare earth element Ln in A sites of the perovskite crystal lattice, the perovskite manganese (Mn) oxide thin film being formed on the substrate so as to cover at least part of a surface of the substrate, and having atomic planes stacked in a pattern of LnO—MnO2—BaO—MnO2-LnO . . . in the [100] axis direction of the substrate. The perovskite manganese (Mn) oxide thin film provided thoroughly exploits the resistance changes caused by charge and orbital ordering in the perovskite manganese oxide.
    Type: Grant
    Filed: March 2, 2012
    Date of Patent: July 15, 2014
    Assignee: Fuji Electric Co., Ltd.
    Inventor: Yasushi Ogimoto
  • Patent number: 8760584
    Abstract: A memory space configuration method applied in a video signal processing apparatus is provided. The method includes: arranging a first memory space and a second memory space in a memory, the first and second memory spaces being partially overlapped; determining a type of a signal source; when the signal source is a first video signal source, enabling a first processing circuit and buffering data associated with the first video signal source by using the first memory space; and, when the signal source is a second video signal source, enabling a second processing circuit and buffering data associated with the second video signal source by using the second memory space. The second processing circuit is disabled when the first processing circuit is enabled; the first processing circuit is disabled when the second processing circuit is enabled.
    Type: Grant
    Filed: May 14, 2013
    Date of Patent: June 24, 2014
    Assignee: MSTAR Semiconductor, Inc.
    Inventor: Po-Jen Yang
  • Patent number: 8747553
    Abstract: A method of growing a p-type thin film of ?-Ga2O3 includes preparing a substrate including a ?-Ga2O3 single crystal, and growing a p-type thin film of ?-Ga2O3 on the substrate. The p-type thin film is grown in a manner that Ga in the thin film is replaced by a p-type dopant selected from H, Li, Na, K, Rb, Cs, Fr, Be, Mg, Ca, Sr, Ba, Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Tl, and Pb.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: June 10, 2014
    Assignee: Waseda University
    Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
  • Publication number: 20140138679
    Abstract: A nonpolar III-nitride film grown on a miscut angle of a substrate, in order to suppress the surface undulations, is provided. The surface morphology of the film is improved with a miscut angle towards an a-axis direction comprising a 0.15° or greater miscut angle towards the a-axis direction and a less than 30° miscut angle towards the a-axis direction.
    Type: Application
    Filed: January 27, 2014
    Publication date: May 22, 2014
    Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Asako Hirai, Zhongyuan Jia, Makoto Saito, Hisashi Yamada, Kenji Iso, Steven P. DenBaars, Shuji Nakamura, James S. Speck
  • Patent number: 8728622
    Abstract: Provided is a base substrate with which a Group-III nitride crystal having a large area and a large thickness can be grown while inhibiting crack generation. A single-crystal substrate for use in growing a Group-III nitride crystal thereon, which satisfies the following expression (1), wherein Z1 (?m) is an amount of warpage of physical shape in a growth surface of the single-crystal substrate and Z2 (?m) is an amount of warpage calculated from a radius of curvature of crystallographic-plane shape in a growth surface of the single-crystal substrate: ?40<Z2/Z1<?1: Expression (1).
    Type: Grant
    Filed: July 13, 2012
    Date of Patent: May 20, 2014
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Kenji Fujito, Yasuhiro Uchiyama
  • Patent number: 8728236
    Abstract: Large area single crystal III-V nitride material having an area of at least 2 cm2, having a uniformly low dislocation density not exceeding 3×106 dislocations per cm2 of growth surface area, and including a plurality of distinct regions having elevated impurity concentration, wherein each distinct region has at least one dimension greater than 50 microns, is disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.
    Type: Grant
    Filed: January 17, 2011
    Date of Patent: May 20, 2014
    Assignee: Cree, Inc.
    Inventors: Xueping Xu, Robert P. Vaudo
  • Patent number: 8715414
    Abstract: There are provided a Si(1-v-w-x)CwAlxNv substrate that achieves high crystallinity and low costs, an epitaxial wafer, and manufacturing methods thereof. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate according to the present invention includes the steps of preparing a different type of substrate 11 and growing a Si(1-v-w-x)CwAlxNv layer having a main surface on the different type of substrate 11. The component ratio x+v at the main surface of the Si(1-v-w-x)CwAlxNv layer is 0<x+v<1. The component ratio x+v increases or decreases monotonically from the interface between the Si(1-v-w-x)CwAlxNv layer and the different type of substrate 11 to the main surface of the Si(1-v-w-x)CwAlxNv layer. The component ratio x+v at the interface between the Si(1-v-w-x)CwAlxNv layer and the different type of substrate 11 is closer to that of the material of the different type of substrate 11 than the component ratio x+v at the main surface of the Si(1-v-w-x)CwAlxNv layer.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: May 6, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Issei Satoh, Michimasa Miyanaga, Shinsuke Fujiwara, Hideaki Nakahata
  • Patent number: 8715413
    Abstract: The invention provides a method for manufacturing a Group III nitride semiconductor crystal. The method includes the steps of preparing a seed crystal and performing a convex surface-growing step to grow the group III nitride semiconductor crystal. The growth surface of the group III nitride semiconductor crystal is constituted only by a plurality of surfaces not vertical to a growth direction and the group III nitride semiconductor crystal grows while forming a convex shape as a whole by the growth surface constituted of the plurality of surfaces. The invention also provides a method for manufacturing a group III nitride semiconductor substrate.
    Type: Grant
    Filed: June 16, 2010
    Date of Patent: May 6, 2014
    Assignee: Hitachi Cable, Ltd.
    Inventor: Yuichi Oshima
  • Patent number: 8709923
    Abstract: Provided is a method of manufacturing III-nitride crystal having a major surface of plane orientation other than {0001}, designated by choice, the III-nitride crystal manufacturing method including: a step of slicing III-nitride bulk crystal through a plurality of planes defining a predetermined slice thickness in the direction of the designated plane orientation, to produce a plurality of III-nitride crystal substrates having a major surface of the designated plane orientation; a step of disposing the substrates adjoining each other sideways in a manner such that the major surfaces of the substrates parallel each other and such that any difference in slice thickness between two adjoining III-nitride crystal substrates is not greater than 0.1 mm; and a step of growing III-nitride crystal onto the major surfaces of the substrates.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: April 29, 2014
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8673074
    Abstract: A method of growing planar non-polar m-plane or semi-polar III-Nitride material, such as an m-plane gallium nitride (GaN) epitaxial layer, wherein the III-Nitride material is grown on a suitable substrate, such as an m-plane sapphire substrate, using hydride vapor phase epitaxy (HVPE). The method includes in-situ pretreatment of the substrate at elevated temperatures in an atmosphere of ammonia and argon, growing an intermediate layer such as an aluminum nitride (AlN) or aluminum-gallium nitride (AlGaN) on the annealed substrate, and growing the non-polar m-plane III-Nitride epitaxial layer on the intermediate layer using HVPE.
    Type: Grant
    Filed: July 15, 2009
    Date of Patent: March 18, 2014
    Assignee: Ostendo Technologies, Inc.
    Inventors: Alexander Usikov, Alexander Syrkin, Robert G. W. Brown, Hussein S. El-Ghoroury, Philippe Spiberg, Vladimir Ivantsov, Oleg Kovalenkov, Lisa Shapovalova
  • Patent number: 8636844
    Abstract: A method of forming a template on a silicon substrate includes epitaxially growing a template of single crystal ternary rare earth oxide on a silicon substrate and epitaxially growing a single crystal semiconductor active layer on the template. The active layer has either a cubic or a hexagonal crystal structure. During the epitaxial growth of the template, a partial pressure of oxygen is selected and a ratio of metals included in the ternary rare earth oxide is selected to match crystal spacing and structure of the template at a lower interface to the substrate and to match crystal spacing and structure of the template at an upper interface to crystal spacing and structure of the semiconductor active layer. A high oxygen partial pressure during growth of the template produces a stabilized cubic crystal structure and a low oxygen partial pressure produces a predominant peak with a hexagonal crystal structure.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: January 28, 2014
    Assignee: Translucent, Inc.
    Inventors: Rytis Dargis, Andrew Clark, Michael Lebby
  • Publication number: 20140020620
    Abstract: The present invention relates to an HPHT method for synthesizing single crystal diamond, wherein a single crystal diamond seed having an aspect ratio of at least 1.5 is utilised. Single crystal diamond seeds having an aspect ratio of at least 1.5 and synthetic single crystal diamond which may be obtained by the method recited are also described. The growth surface is substantially aligned along a <100> or <110> direction in the plane of the growth surface.
    Type: Application
    Filed: September 6, 2013
    Publication date: January 23, 2014
    Inventors: Carlton Nigel Dodge, Raymond Anthony Spits
  • Patent number: 8597427
    Abstract: A semiconductor device is provided which is constituted by semiconductor devices including a thin film transistor with a GOLD structure, the GOLD structure thin film transistor being such that: a semiconductor layer, a gate insulating film, and a gate electrode are formed in lamination from the side closer to a substrate; the gate electrode is constituted of a first-layer gate electrode and a second-layer gate electrode shorter in the size than the first-layer gate electrode; the first-layer gate electrode corresponding to the region exposed from the second-layer gate electrode is formed into a tapered shape so as to be thinner toward the end portion; a first impurity region is formed in the semiconductor layer corresponding to the region with the tapered shape; and a second impurity region having the same conductivity as the first impurity region is formed in the semiconductor layer corresponding to the outside of the first-layer gate electrode, which is characterized in that a dry etching process consisting
    Type: Grant
    Filed: August 29, 2008
    Date of Patent: December 3, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoru Okamoto
  • Patent number: 8591652
    Abstract: The invention relates to a free-standing semiconductor substrate as well as a process and a mask layer for the manufacture of a free-standing semiconductor substrate, wherein the material for forming the mask layer consists at least partially of tungsten silicide nitride or tungsten silicide and wherein the semiconductor substrate self-separates from the starting substrate without further process steps.
    Type: Grant
    Filed: August 24, 2006
    Date of Patent: November 26, 2013
    Assignee: Freiberger Compound Materials GmbH
    Inventors: Christian Hennig, Markus Weyers, Eberhard Richter, Guenther Traenkle
  • Patent number: 8592289
    Abstract: A gallium nitride based semiconductor device is provided which includes a gallium nitride based semiconductor film with a flat c-plane surface provided on a gallium oxide wafer. A light emitting diode LED includes a gallium oxide support base 32 having a primary surface 32a of monoclinic gallium oxide, and a laminate structure 33 of Group III nitride. A semiconductor mesa of the laminate structure 33 includes a low-temperature GaN buffer layer 35, an n-type GaN layer 37, an active layer 39 of a quantum well structure, and a p-type gallium nitride based semiconductor layer 37. The p-type gallium nitride based semiconductor layer 37 includes, for example, a p-type AlGaN electron block layer and a p-type GaN contact layer. The primary surface 32a of the gallium oxide support base 32 is inclined at an angle of not less than 2 degrees and not more than 4 degrees relative to a (100) plane of monoclinic gallium oxide.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: November 26, 2013
    Assignees: Sumitomo Electric Industries, Ltd., KOHA Co., Ltd.
    Inventors: Shin Hashimoto, Katsushi Akita, Shinsuke Fujiwara, Hideaki Nakahata, Kensaku Motoki
  • Patent number: 8585822
    Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: November 19, 2013
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Masanori Ikari, Edward Letts
  • Patent number: 8585821
    Abstract: In one embodiment of the present invention, a monocrystal SiC epitaxial substrate is produced which includes a monocrystal SiC substrate; a buffer layer made of a first SiC epitaxial film formed on the monocrystal SiC substrate; and an active layer made of a second SiC epitaxial film formed on the buffer layer. The buffer layer is grown by heat-treating a set of the monocrystal SiC substrate, a carbon source plate, and a metal Si melt layer having a predetermined thickness and interposed between the monocrystal SiC substrate and the metal Si melt layer, so as to epitaxially grow monocrystal SiC on the monocrystal SiC substrate. The active layer is grown by epitaxially growing monocrystal SiC on the buffer layer by vapor phase growth method. This allows for production of a monocrystal SiC epitaxial substrate including a high-quality monocrystal SiC active layer being low in defects.
    Type: Grant
    Filed: March 11, 2008
    Date of Patent: November 19, 2013
    Assignees: Ecotron Co., Ltd., Research Institute of Innovative Technology for the Earth
    Inventors: Nobuhiko Nakamura, Toru Matsunami, Kimito Nishikawa
  • Patent number: 8580035
    Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities—e.g., a dislocation density below 104 cm?2 and an inclusion density below 104 cm?3 and/or a MV density below 104 cm?3.
    Type: Grant
    Filed: December 6, 2012
    Date of Patent: November 12, 2013
    Assignee: Crystal IS, Inc.
    Inventors: Robert Bondokov, Kenneth E. Morgan, Glen A. Slack, Leo J. Schowalter
  • Patent number: 8574528
    Abstract: A method of growing an epitaxial layer on a substrate is generally provided. According to the method, the substrate is heated in a chemical vapor deposition chamber to a growth temperature in the presence of a carbon source gas, then the epitaxial layer is grown on the substrate at the growth temperature, and finally the substrate is cooled in a chemical vapor deposition chamber to at least about 80% of the growth temperature in the presence of a carbon source gas. Substrates formed from this method can have a carrier lifetime between about 0.25 ?s and about 9.9 ?s.
    Type: Grant
    Filed: September 7, 2010
    Date of Patent: November 5, 2013
    Assignee: University of South Carolina
    Inventors: Tangali S. Sudarshan, Amitesh Srivastava
  • Publication number: 20130276697
    Abstract: It is to suppress abnormal growth of GaN crystals around edge ends of a seed substrate. A susceptor is provided that has a pocket section in which a seed substrate is fixed, and a sub-susceptor provided between the susceptor and the seed substrate, the sub-susceptor being not reactive with the seed substrate, with a gap provided between the seed substrate and the sub-susceptor.
    Type: Application
    Filed: January 7, 2011
    Publication date: October 24, 2013
    Applicant: A.E. TECH CORPORATION
    Inventor: Hideki Goto
  • Patent number: 8557043
    Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.
    Type: Grant
    Filed: December 27, 2012
    Date of Patent: October 15, 2013
    Assignee: SixPoint Materials, Inc.
    Inventors: Tadao Hashimoto, Masanori Ikari, Edward Letts
  • Publication number: 20130263776
    Abstract: A method of fabricating a semiconductor processing device includes providing a susceptor including a substantially cylindrical body portion having opposing upper and lower surfaces. The body portion has a diameter larger than a wafer diameter. The method also includes providing a set of holes circumferentially disposed at a first susceptor diameter, the set of holes being evenly spaced with respect to adjacent holes and extending through the upper and lower surfaces in an area. The first susceptor diameter is larger than the wafer diameter, and holes are omitted along the first diameter in a set of predetermined orientations.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Applicant: MEMC Electronic Materials, Inc.
    Inventors: John Allen Pitney, Manabu Hamano
  • Patent number: 8551246
    Abstract: A method for manufacturing a silicon single crystal wafer, having at least: a step of preparing a silicon single crystal ingot; a step of slicing the silicon single crystal ingot to fabricate a plurality of sliced substrates; a processing step of processing the plurality of sliced substrates into a plurality of substrates by performing at least one of lapping, etching, and polishing; a step of sampling at least one from the plurality of substrates; a step of measuring surface roughness of the substrate sampled at the sampling step by an AFM and obtaining an amplitude (an intensity) of a frequency band corresponding to a wavelength of 20 nm to 50 nm to make a judgment of acceptance; and a step of sending the substrate to the next step if a judgment result is acceptance or performing reprocessing if the judgment result is rejection.
    Type: Grant
    Filed: May 7, 2009
    Date of Patent: October 8, 2013
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Fumio Tahara, Tsuyoshi Ohtsuki, Takatoshi Nagoya, Kiyoshi Mitani
  • Patent number: 8524012
    Abstract: A method for growing planar, semi-polar nitride film on a miscut spinel substrate, in which a large area of the planar, semi-polar nitride film is parallel to the substrate's surface. The planar films and substrates are: (1) {1011} gallium nitride (GaN) grown on a {100} spinel substrate miscut in specific directions, (2) {1013} gallium nitride (GaN) grown on a {110} spinel substrate, (3) {1122} gallium nitride (GaN) grown on a {1100} sapphire substrate, and (4) {1013} gallium nitride (GaN) grown on a {1100} sapphire substrate.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: September 3, 2013
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Troy J. Baker, Benjamin A. Haskell, Paul T. Fini, Steven P. DenBaars, James S. Speck, Shuji Nakamua
  • Patent number: 8506707
    Abstract: A compositionally graded material having low defect densities and improved electronic properties is disclosed and described. A compositionally graded inorganic crystalline material can be formed by preparing a crystalline substrate by forming crystallographically oriented pits across an exposed surface of the substrate. A transition region can be deposited on the substrate under substantially epitaxial growth conditions. Single crystal substrates of a wide variety of materials such as diamond, aluminum nitride, silicon carbide, etc. can be formed having relatively low defect rates.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: August 13, 2013
    Inventor: Chien-Min Sung
  • Patent number: 8491718
    Abstract: A method is disclosed for making semiconductor films from a eutectic alloy comprising a metal and a semiconductor. Through heterogeneous nucleation said film is deposited at a deposition temperature on relatively inexpensive buffered substrates, such as glass. Specifically said film is vapor deposited at a fixed temperature in said deposition temperature where said deposition temperature is above a eutectic temperature of said eutectic alloy and below a temperature at which the substrate softens. Such films could have widespread application in photovoltaic and display technologies.
    Type: Grant
    Filed: October 13, 2010
    Date of Patent: July 23, 2013
    Inventors: Karin Chaudhari, Ashok Chaudhari, Pia Chaudhari
  • Patent number: 8475588
    Abstract: A wafer structure and epitaxial growth method for growing the same. The method may include forming a mask layer having nano-sized areas on a wafer, forming a porous layer having nano-sized pores on a surface of the wafer by etching the mask layer and a surface of the wafer, and forming an epitaxial material layer on the porous layer using an epitaxial growth process.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: July 2, 2013
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventor: Sung-Soo Park
  • Patent number: 8470091
    Abstract: A direction of a dislocation line of a threading dislocation is aligned, and an angle between the direction of the dislocation line of the threading dislocation and a [0001]-orientation c-axis is equal to or smaller than 22.5 degrees. The threading dislocation having the dislocation line along with the [0001]-orientation c-axis is perpendicular to a direction of a dislocation line of a basal plane dislocation. Accordingly, the dislocation does not provide an extended dislocation on the c-face, so that a stacking fault is not generated. Thus, when an electric device is formed in a SiC single crystal substrate having the direction of the dislocation line of the threading dislocation, which is the [0001]-orientation c-axis, a SiC semiconductor device is obtained such that device characteristics are excellent without deterioration, and a manufacturing yield ration is improved.
    Type: Grant
    Filed: January 21, 2010
    Date of Patent: June 25, 2013
    Assignee: DENSO CORPORATION
    Inventors: Yasuo Kitou, Hiroki Watanabe, Masanori Nagaya, Kensaku Yamamoto, Eiichi Okuno
  • Patent number: 8465587
    Abstract: Hydride vapor-phase deposition (HVPE) systems are disclosed. An HVPE hydride vapor-phase deposition system may include a reactant source chamber and a growth chamber containing a susceptor coupled to the reactant source chamber. The reactant source chamber may be configured to create a reactant gas through a chemical reaction between a solid or liquid precursor and a different precursor gas. The reactant source chamber can be configured to operate at a temperature T(M) significantly above room temperature. The reactant gas can be chemically unstable at or near room temperature. The susceptor is configured to receive a substrate and maintain the substrate at a substrate temperature T(S). The growth chamber includes walls can be configured to operate at a temperature T(C) such that T(M), T(S) are greater than T(C).
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: June 18, 2013
    Assignee: CBL Technologies, Inc.
    Inventors: Glenn S. Solomon, David J. Miller
  • Publication number: 20130143022
    Abstract: The present invention relates to a method for producing diamond layers, wherein firstly, in a first growing step, diamond is grown on a growing surface of a off axis or a off-axis heterosubstrate in such a way that a texture width, in particular a polar and/or azimuthal texture width, of a diamond layer produced during the growth decreases with increasing distance from the substrate and then, in a second growing step, diamond is grown in such a way that the texture width of the diamond layer remains substantially constant as the distance from the substrate further increases, and lattice planes of the substrate being inclined by an angle greater than zero with respect to the growing surface.
    Type: Application
    Filed: June 16, 2011
    Publication date: June 6, 2013
    Applicant: UNIVERSITAET AUGSBURG
    Inventors: Matthias Schreck, Stefan Gsell, Martin Fischer
  • Patent number: 8449675
    Abstract: A semiconductor wafer is formed of a substrate wafer of single crystal silicon doped with dopant atoms of the n type or p type, with a front surface and a back surface, contains a layer deposited epitaxially on the front surface of the substrate wafer. The substrate wafer additionally includes an n++ or p++ doped layer, which extends from the front surface of the substrate wafer into the substrate wafer and has a defined thickness. The semiconductor wafer is produced by a process in which dopant atoms of the n type or p type are introduced into the substrate wafer through the front surface of the substrate wafer, the dopant concentration in a layer which extends from the front surface of the substrate wafer into the substrate wafer being increased from the level n+ or p+ to the level n++ or p++, and an epitaxial layer is then deposited on this layer.
    Type: Grant
    Filed: July 28, 2008
    Date of Patent: May 28, 2013
    Assignee: Siltronic AG
    Inventors: Rupert Krautbauer, Gerhard Huettl, Andrej Lenz, Erwin-Peter Mayer, Rainer Winkler
  • Patent number: 8415546
    Abstract: Disclosed is a fabrication method of a metal nanoplate using metal, metal halide or a mixture thereof as a precursor. The single crystalline metal nanoplate is fabricated on a single crystalline substrate by performing heat treatment on a precursor including metal, metal halide or a mixture thereof and placed at a front portion of a reactor and the single crystalline substrate placed at a rear portion of the reactor under an inert gas flowing condition. A noble metal nanoplate of several micrometers in size can be fabricated using a vapor-phase transport process without any catalyst. The fabricated nanoplate is a single crystalline metal nanoplate having high crystallinity, high purity and not having a two-dimensional defect. Morphology and orientation of the metal nanoplate with respect to the substrate can be controlled by controlling a surface direction of the single crystalline substrate. The metal nanoplate of several micrometer size is mass-producible.
    Type: Grant
    Filed: September 22, 2009
    Date of Patent: April 9, 2013
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Bongsoo Kim, Youngdong Yoo
  • Patent number: 8404042
    Abstract: III-nitride crystal composites are made up of especially processed crystal slices cut from III-nitride bulk crystal having, ordinarily, a {0001} major surface and disposed adjoining each other sideways, and of III-nitride crystal epitaxially on the bulk-crystal slices. The slices are arranged in such a way that their major surfaces parallel each other, but are not necessarily flush with each other, and so that the [0001] directions in the slices are oriented in the same way.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: March 26, 2013
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Naho Mizuhara, Koji Uematsu, Michimasa Miyanaga, Keisuke Tanizaki, Hideaki Nakahata, Seiji Nakahata, Takuji Okahisa
  • Patent number: 8357243
    Abstract: The present invention discloses a new testing method of group III-nitride wafers. By utilizing the ammonothermal method, GaN or other Group III-nitride wafers can be obtained by slicing the bulk GaN ingots. Since these wafers originate from the same ingot, these wafers have similar properties/qualities. Therefore, properties of wafers sliced from an ingot can be estimated from measurement data obtained from selected number of wafers sliced from the same ingot or an ingot before slicing. These estimated properties can be used for product certificate of untested wafers. This scheme can reduce a significant amount of time, labor and cost related to quality control.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: January 22, 2013
    Assignee: Sixpoint Materials, Inc.
    Inventors: Tadao Hashimoto, Masanori Ikari, Edward Letts
  • Patent number: 8349077
    Abstract: Reducing the microvoid (MV) density in AlN ameliorates numerous problems related to cracking during crystal growth, etch pit generation during the polishing, reduction of the optical transparency in an AlN wafer, and, possibly, growth pit formation during epitaxial growth of AlN and/or AlGaN. This facilitates practical crystal production strategies and the formation of large, bulk AlN crystals with low defect densities—e.g., a dislocation density below 104 cm?2 and an inclusion density below 104 cm?3 and/or a MV density below 104 cm?3.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: January 8, 2013
    Assignee: Crystal IS, Inc.
    Inventors: Robert T. Bondokov, Kenneth Morgan, Glen A. Slack, Leo J. Schowalter
  • Patent number: 8278672
    Abstract: A semiconductor light-emitting device is disclosed. The semiconductor light-emitting device comprises a multilayer epitaxial structure disposed on a semiconductor substrate. The semiconductor substrate has a predetermined lattice direction perpendicular to an upper surface thereof, wherein the predetermined lattice direction is angled toward [0 11] or [01 1] from [100], or toward [011] or [0 11] from [ 100] so that the upper surface of the semiconductor substrate comprises at least two lattice planes with different lattice plane directions. The multilayer epitaxial structure has a roughened upper surface perpendicular to the predetermined lattice direction. The invention also discloses a method for fabricating a semiconductor light-emitting device.
    Type: Grant
    Filed: March 26, 2007
    Date of Patent: October 2, 2012
    Assignee: Epistar Corporation
    Inventors: Ya-Ju Lee, Ta-Cheng Hsu, Ming-Ta Chin, Yen-Wen Chen, Wu-Tsung Lo, Chung-Yuan Li, Min-Hsun Hsieh
  • Publication number: 20120234231
    Abstract: The process for producing silicon carbide single crystals of the present invention comprises a step for growing single crystals of silicon carbide on a silicon carbide seed crystal by supplying a sublimed gas of a silicon carbide source material to the silicon carbide seed crystal arranged on a pedestal, wherein a spacing member composed of silicon carbide is arranged between the pedestal and the silicon carbide seed crystal, the spacing member is non-adhesively held on the pedestal by a supporting member, the silicon carbide seed crystal is adhered to the surface of the spacing member on the opposite side of the pedestal, and the spacing member and the supporting member are relatively arranged so that the adhesive surface of the spacing member adhered with the silicon carbide seed crystal is separated by 5 mm or more in the vertical direction from the lowest position of the supporting member.
    Type: Application
    Filed: October 18, 2010
    Publication date: September 20, 2012
    Applicant: SHOWA DENKO K.K.
    Inventors: Takashi Masuda, Hisao Kogoi, Katsuhiko Hashimoto
  • Patent number: 8268076
    Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: September 18, 2012
    Assignee: Siltronic AG
    Inventors: Thomas Schroeder, Peter Storck, Hans Joachim Muessig
  • Patent number: 8263424
    Abstract: A method for growing III-V nitride films having an N-face or M-plane using an ammonothermal growth technique. The method comprises using an autoclave, heating the autoclave, and introducing ammonia into the autoclave to produce smooth N-face or M-plane Gallium Nitride films and bulk GaN.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: September 11, 2012
    Assignees: The Regents of the University of California, Japan Science and Technology Agency
    Inventors: Tadao Hashimoto, Hitoshi Sato, Shuji Nakamura
  • Patent number: 8262796
    Abstract: A thin-film single crystal growing method includes preparing a substrate, irradiating an excitation beam on a metallic target made of a pure metal or an alloy in a predetermined atmosphere, and combining chemical species including any of atoms, molecules, and ions released from the metallic target by irradiation of the excitation beam with atoms contained in the predetermined atmosphere to form a thin film on the substrate.
    Type: Grant
    Filed: March 15, 2010
    Date of Patent: September 11, 2012
    Assignee: Waseda University
    Inventors: Noboru Ichinose, Kiyoshi Shimamura, Kazuo Aoki, Encarnacion Antonia Garcia Villora
  • Publication number: 20120225004
    Abstract: In a physical vapor transport growth technique for silicon carbide a silicon carbide powder and a silicon carbide seed crystal are introduced into a physical vapor transport growth system and halosilane gas is introduced separately into the system. The source powder, the halosilane gas, and the seed crystal are heated in a manner that encourages physical vapor transport growth of silicon carbide on the seed crystal, as well as chemical transformations in the gas phase leading to reactions between halogen and chemical elements present in the growth system.
    Type: Application
    Filed: May 15, 2012
    Publication date: September 6, 2012
    Applicant: II-VI INCORPORATED
    Inventors: Ilya Zwieback, Thomas E. Anderson, Avinash K. Gupta