Characterized By Specified Crystallography Or Arrangement Of Substrate (e.g., Wafer Cassette, Miller Index) Patents (Class 117/101)
  • Patent number: 5743956
    Abstract: A method of producing a high-quality single crystal thin film in which a temperature of a semiconductor single crystal substrate is raised or lowered in a short time with no occurrence of slippage in the substrate. In a cold-wall type reaction vessel, a substrate is placed on a holder which has no heating capability in the reaction vessel and a thin film is grown on the substrate, while a reaction gas is fed to flow in one direction through the reaction vessel, and at the same time, a temperature profile on the substrate along the flow direction of the reaction gas is adjusted to be uniform by a spatially controlled heating energy distribution and/or with the help of an auxiliary heating region provided at an upstream part of the substrate.
    Type: Grant
    Filed: June 17, 1996
    Date of Patent: April 28, 1998
    Assignee: Shin-Etsu Handotai, Co., Ltd.
    Inventors: Hitoshi Habuka, Masanori Mayuzumi
  • Patent number: 5738720
    Abstract: The present invention aims to provide a method of manufacturing a microstructure pattern of a high orientation aggregate of organic molecular material by forming a fine pattern made by single crystal growing ionic material of another property on an ionic substrate by lithography and epitaxial growth, and forming a pattern made by organic molecular material having functionability to light on the fine pattern by utilizing dependence of substrate material of crystal growth rate in epitaxial growth, and is applied to the formation of a microstructure pattern of organic molecular material which can be utilized for optical waveguide, optical integrated circuit, non-linear optical element and laser resonator.
    Type: Grant
    Filed: February 12, 1996
    Date of Patent: April 14, 1998
    Assignee: The University of Tokyo
    Inventors: Toshihiro Shimada, Atsushi Koma
  • Patent number: 5739086
    Abstract: A biaxially textured article includes a rolled and annealed, biaxially textured substrate of a metal having a face-centered cubic, body-centered cubic, or hexagonal close-packed crystalline structure; and an epitaxial superconductor or other device epitaxially deposited thereon.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: April 14, 1998
    Assignee: Lockheed Martin Energy Systems, Inc.
    Inventors: Amit Goyal, John D. Budai, Donald M. Kroeger, David P. Norton, Eliot D. Specht, David K. Christen
  • Patent number: 5718761
    Abstract: A method of forming a crystalline compound semiconductor film comprises introducing into a crystal forming space housing a substrate on which a non-nucleation surface (S.sub.NDS) having a smaller nucleation density and a nucleation surface (S.sub.NDL) having a fine surface area sufficient for crystal growth only from a single nucleus and having a larger nucleation density (ND.sub.L) than the nucleation density (NDs) of the non-nucleation surface (S.sub.NDS) are arranged adjacent to each other an organometallic compound (VI) for supplying an element belonging to the group VI of Periodic Table represented by the general formula R.sub.1 --X.sub.n --R.sub.2 wherein n is an integer of 2 or more; R.sub.1 and R.sub.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: February 17, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Tokunaga, Jun-ichi Hanna, Isamu Shimizu
  • Patent number: 5716450
    Abstract: In a method of growing a gallium nitride related compound semiconductor crystal on a single crystal substrate, the {011} plane or the {101} plane of rare earth group 13 (3B) perovskite is used as the single crystal substrate. As a result, a gallium nitride group semiconductor crystal excellent in crystallinity can be grown epitaxially.
    Type: Grant
    Filed: December 6, 1995
    Date of Patent: February 10, 1998
    Assignee: Japan Energy Corporation
    Inventors: Seiji Togawa, Hitoshi Okazaki
  • Patent number: 5714006
    Abstract: A method of growing a compound semiconductor layer includes epitaxially growing a III-V compound semiconductor layer including nitrogen (N) for as the Group V element on a front surface of a semiconductor substrate of cadmium telluride (CdTe). Therefore, the atoms of the crystal lattice of the III-V compound semiconductor layer are periodically lattice-matched with the atoms of the crystal lattice of the CdTe semiconductor substrate, whereby the III-V compound semiconductor layer is epitaxially grown with high crystalline quality.
    Type: Grant
    Filed: December 18, 1995
    Date of Patent: February 3, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hirotaka Kizuki, Yasutomo Kajikawa
  • Patent number: 5685906
    Abstract: A set (10) of susceptors (12) having essentially equal outer diameters (14) and different depression diameters (20) is used in a horizontal flow semiconductor epitaxial reactor. The susceptors receiving smaller diameter wafers (24) have an increased surface area (84) that preheats the process gases and leads to reduced resistivity variation in the epitaxial layers. The susceptors fit interchangeably onto a susceptor support (32) and into a susceptor ring (38), thereby allowing wafers of different diameters to be processed by changing only the susceptor and not the susceptor support, the susceptor ring, and other associated hardware. Set-up time is greatly reduced, thereby allowing more flexibility in scheduling wafers to be processed and improving reactor utilization. Inventory of reactor components can be reduced because it is no longer necessary to stock susceptor rings and other hardware for wafers of different diameters.
    Type: Grant
    Filed: March 23, 1995
    Date of Patent: November 11, 1997
    Assignee: SEH America, Inc.
    Inventors: Gerald R. Dietze, Erik D. Holman
  • Patent number: 5679179
    Abstract: A method of forming GaAs/AlGaAs hetero-structure. The method includes the steps of preparing a GaAs substrate having a (411)A-oriented surface and setting the GaAs substrate inside a growth container with the (411)A surface being disposed as a surface to be deposited. The pressure inside the growth chamber is reduced and the GaAs substrate is heated up to a predetermined temperature to cause epitaxial growth of Ga, Al, As on the (411)A substrate and forming a GaAs/AlGaAs hetero-structure on the (411)A-oriented GaAs substrate.
    Type: Grant
    Filed: September 5, 1995
    Date of Patent: October 21, 1997
    Assignee: Kubota Corporation
    Inventors: Satoshi Hiyamizu, Satoshi Shimomura, Yasunori Okamoto
  • Patent number: 5660628
    Abstract: There is provided a method for suppressing generation of cracks or damages on a compound semiconductor epitaxial wafer during an epitaxial growth due to growth of an epitaxial layer on the rear surface at the edge of the epitaxial layer which is located at the upstream side of the flow of the source gas. In manufacturing a semiconductor wafer by growing a single crystal semiconductor epitaxial layer having a zinc blend structure on a single crystal semiconductor substrate having a zinc blend structure, the surface of the single crystal semiconductor substrate has (100) surface orientation having an off angle and a source gas is supplied in the direction of the off angle or in a direction at 30.degree. or less to the direction at 180.degree. thereto.
    Type: Grant
    Filed: August 18, 1994
    Date of Patent: August 26, 1997
    Assignee: Mitsubishi Kasei Corp.
    Inventors: Tadashige Sato, Hitora Takahashi
  • Patent number: 5660697
    Abstract: An electroluminescent display device with decreased voltage requirements comprises:(a) a substrate having a major surface;(b) a first electrode disposed over the major surface of the substrate;(c) a first insulating film disposed over the first electrode;(d) a light-emitting film disposed over the first insulating film;(e) a second insulating film disposed over the light-emitting film; and(f) a second electrode disposed over the second insulating film. The insulating films have a columnar structure oriented perpendicular to an electric field formed between the two electrodes, and either of the insulating films may be omitted.
    Type: Grant
    Filed: June 2, 1995
    Date of Patent: August 26, 1997
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Tomoyuki Kawashima, Harutaka Taniguchi, Hisato Kato, Kazuyoshi Shibata
  • Patent number: 5653803
    Abstract: One or a plurality of silicon growth layers are formed on both sides of a silicon base substrate wafer and the product is then divided, with the dividing plane in said silicon base substrate wafer parallel to the main surface, into two pieces to obtain two substrates used for manufacturing silicon semiconductor elements. Said dividing-in-half process is a process in which said silicon base substrate wafer portion is cut along a plane parallel to the main surface, or a process which includes said cutting process followed by a process of treating the cut-surface. Said process which cuts the silicon base substrate wafer portion is a process in which the wafers are cut one by one, or cut after a plurality of them are laminated.
    Type: Grant
    Filed: March 1, 1995
    Date of Patent: August 5, 1997
    Assignee: Shin-Etsu Handotai Co. Ltd.
    Inventor: Tatsuo Ito
  • Patent number: 5628824
    Abstract: The deposition of high quality diamond films at high linear growth rates and substrate temperatures for microwave-plasma chemical vapor deposition is disclosed. The linear growth rate achieved for this process is generally greater than 50 .mu.m/hr for high quality films, as compared to rates of less than 5 .mu.m/hr generally reported for MPCVD processes.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: May 13, 1997
    Assignee: The University of Alabama at Birmingham Research Foundation
    Inventors: Yogesh K. Vohra, Thomas S. McCauley
  • Patent number: 5604151
    Abstract: .beta.-silicon carbide which is optically transmitting in the visible and infrared regions is produced by chemical vapor deposition. Deposition conditions are temperatures within a 1400.degree.-1500.degree. C. range, pressure 50 torr or less, H.sub.2 /methyltrichlorosilane molar ratios of 4-30 and a deposition rate of 1 .mu.m or less.
    Type: Grant
    Filed: May 11, 1995
    Date of Patent: February 18, 1997
    Assignee: CVD, Incorporated
    Inventors: Jitendra S. Goela, Lee E. Burns, Raymond L. Taylor
  • Patent number: 5580381
    Abstract: A crystal forming method comprises disposing, on a surface of a substrate or in recessed portion formed in the substrate having a surface with a low nucleation density, primary seed having a sufficient small volume to singly aggregate and a rectangular prismatic or cubic shape in which all the sides and the bottom are surrounded by an insulator in contact therewith; performing heat treatment for aggregating the primary seed to form monocrystalline seed crystal having controlled plane orientation and in-plane orientation; and selectively growing monocrystal by crystal growth treatment using the seed crystal as starting point.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: December 3, 1996
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Yamagata
  • Patent number: 5512375
    Abstract: High quality epitaxial layers can be grown on a multi-layer substrate which has a crystalline pseudomorphic layer with an exposed surface used for the epitaxial growth. The pseudomorphic layer of the substrate has a thickness at or below the pseudomorphic limit so it will be deformed as stress forces are developed during epitaxial growth of heteroepitaxial structures. A plastically deformable layer is bonded to the pseudomorphic layer, This plastically deformable layer is made of material that plastically flows at epitaxial growth temperatures.
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: April 30, 1996
    Assignee: Intevac, Inc.
    Inventors: Roger T. Green, Gary A. Davis, Verle W. Aebi
  • Patent number: 5501173
    Abstract: A method for epitaxially growing a-axis .alpha.-SiC on an a-axis substrate is provided. A section is formed from the SiC crystal by making a pair of parallel cuts in the crystal. Each of these cuts is parallel to the c-axis of the crystal. The resulting section formed from the crystal has opposing a-face surfaces parallel to the c-axis of the crystal. A gas mixture having hydrocarbon and silane is passed over one of the a-face surfaces of the section. The hydrocarbon and silane react on this a-face surface to form an epitaxial layer of SiC. Preferably, the SiC is grown at a temperature of approximately 1450.degree. C.
    Type: Grant
    Filed: October 18, 1993
    Date of Patent: March 26, 1996
    Assignee: Westinghouse Electric Corporation
    Inventors: Albert A. Burk, Jr., Donovan L. Barrett, Hudson M. Hobgood, Rowland C. Clarke, Graeme W. Eldridge, Charles D. Brandt
  • Patent number: 5500389
    Abstract: A process for formation of a hetero junction structured film utilizing V grooves is disclosed. A monocrystalline film 1 is etched into V grooves, and thereupon, a hetero film 2 having misfits is grown, so that dislocations would be intensively distributed within the V grooves. Then, an oxide layer 3 is formed thereupon, and then, the portions of the oxide layer 3 and the hereto film 2 corresponding to the V grooves are removed by carrying out an etching. Then, the residue oxide layer is removed, thereby forming a non-stress non-dislocation hetero junction structure. Further, the following steps can be added. That is, on the above structure, a thin oxide layer 3 is deposited by carrying out a thermal oxidation or a chemical deposition, and then, a polycrystalline silicon film 4 is deposited. Then the surface irregularities are smoothened by carrying out a selective grinding. Or the following steps may be added.
    Type: Grant
    Filed: November 17, 1994
    Date of Patent: March 19, 1996
    Assignee: Electronics & Telecommunications Research Institute
    Inventors: Seung-Chang Lee, Sun-Jin Yun, Bo-Woo Kim, Sang-Won Kang
  • Patent number: 5474021
    Abstract: A plurality of single-crystalline diamond plates having principal surfaces consisting essentially of {100} planes are prepared. The diamond plates are so arranged that the respective principal surfaces are substantially flush with each other. In this arrangement, an angle formed by crystal orientations of the principal surfaces between adjacent plates is not more than 5.degree., a clearance between the adjacent plates is not more than 30 .mu.m, and a difference in height of the principal surfaces is not more than 30 .mu.m between the adjacent plates. To secure this arrangement, the plurality of diamond plates are joined to each other by depositing diamond on the plates to form a single large diamond plate. After such joining, the principal surfaces of the diamond plates are polished in order to eliminate steps or height differences. Then, diamond is epitaxially grown on a polished surface of the large diamond plate from a vapor phase.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: December 12, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takashi Tsuno, Takahiro Imai, Naoji Fujimori
  • Patent number: 5439844
    Abstract: A process for forming a deposited film comprises the steps:(a) arranging a substrate having crystal orientability uniformly on its surface in a film forming space for formation of a deposited film;(b) introducing into said film forming space an activated species (A) formed by decomposition of a compound (SX) containing silicon and a halogen and an activated species (B) formed from a chemical substance (B) for film formation which is chemically mutually reactive with said activated species (A) separately from each other, thus permitting both the species to react chemically with each other thereby to form a deposited film on the above substrate; and(c) introducing into said film forming space a gaseous substance (E) having etching action on said deposited film to be formed or a gaseous substance (E2) forming said gaseous substance (E) during the above film formation step (b), thus exposing the surface for deposited film growth to said gaseous substance (E) and thereby effecting an etching action to conduct crys
    Type: Grant
    Filed: May 12, 1993
    Date of Patent: August 8, 1995
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akira Sakai
  • Patent number: 5398641
    Abstract: A method and apparatus (10) for forming a p-doped layer (68, 80, 92) of Group II and Group VI elements by molecular beam epitaxial process in which a nitrogen dopant is introduced as the layer (68, 80, 92) is being grown. In one embodiment, molecular nitrogen is passed through a plasma generator (46) for converting it to activated nitrogen, and the activated nitrogen is conducted through an elongated guide tube (50) toward the substrate (66) upon which a Group II-Group VI layer (68, 80, 92) is being grown. In one embodiment, an n-type dopant source (72) is also provided, the apparatus (10) being operable for forming electrical devices (86, 88) having successive layers (78, 80, 90, 92, 94) of differing electrical characteristics.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: March 21, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Hung-Dah Shih
  • Patent number: 5394826
    Abstract: A group II-VI epitaxial layer grown on a (111) silicon substrate has a lattice mismatch which is minimized, as between the group II-VI epitaxial layer and the silicon substrate. The grown group II-VI epitaxial layer also has a (111) plane at the interface with the substrate, and a 30.degree. in-plane rotation slip is formed at the interface between the (111) silicon substrate and the group II-VI epitaxial layer. The above structure is produced by a metal organic chemical vapor deposition method (MOCVD), in which a mol ratio of a group VI gas source supply to a group II gas source supply is kept greater than 15 during the growth. The (111) silicon substrate is preferably mis-oriented toward the <110> direction of the silicon substrate. When a HgCdTe layer is grown on the epitaxial layer, the product thus formed has utility as a monolithic infrared detector in which a plurality of detector elements are formed in the HgCdTe layer and a signal processing circuit is formed in the silicon substrate.
    Type: Grant
    Filed: October 22, 1993
    Date of Patent: March 7, 1995
    Assignee: Fujitsu Limited
    Inventors: Hiroji Ebe, Akira Sawada
  • Patent number: 5387310
    Abstract: A single crystal diamond film having good electrical characteristics is produced by a method which comprises steps of decomposing a raw material gas comprising a hydrogen gas and a carbon-containing compound and epitaxially growing a single crystal diamond film on a single crystal substrate in a vapor phase, wherein a molar ratio of the carbon atoms in the carbon-containing compound to the hydrogen is from 2:100 to 10:100 and a lattice constant of the single crystal substrate satisfies the following relation:.vertline.(a-a.sub.0)/a.vertline..times.100.ltoreq.20 (I)wherein a.sub.0 is the lattice constant of diamond (3.567 .ANG.) and a is a lattice constant of the single crystal substrate.
    Type: Grant
    Filed: April 16, 1993
    Date of Patent: February 7, 1995
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Hiromu Shiomi, Naoji Fujimori
  • Patent number: 5363800
    Abstract: This invention is a method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.
    Type: Grant
    Filed: November 9, 1992
    Date of Patent: November 15, 1994
    Assignee: The United States of America as represented by the United States National Aeronautics and Space Administration
    Inventors: David J. Larkin, Powell, J. Anthony
  • Patent number: 5362682
    Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.
    Type: Grant
    Filed: March 15, 1993
    Date of Patent: November 8, 1994
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl O. Bozler, John C.C. Fan, Robert W. McClelland