Characterized By Specified Crystallography Or Arrangement Of Substrate (e.g., Wafer Cassette, Miller Index) Patents (Class 117/101)
  • Patent number: 6530990
    Abstract: A susceptor is disclosed for minimizing or eliminating thermal gradients that affect a substrate wafer during epitaxial growth. The susceptor comprises a first susceptor portion including a surface for receiving a semiconductor substrate wafer thereon, and a second susceptor portion facing the substrate-receiving surface and spaced from the substrate-receiving surface. The spacing is sufficiently large to permit the flow of gases therebetween for epitaxial growth on a substrate on the surface, while small enough for the second susceptor portion to heat the exposed face of a substrate to substantially the same temperature as the first susceptor portion heats the face of a substrate that is in direct contact with the substrate-receiving surface.
    Type: Grant
    Filed: February 21, 2001
    Date of Patent: March 11, 2003
    Assignee: Cree, Inc.
    Inventors: Hua-Shuang Kong, Calvin Carter, Jr., Joseph Sumakeris
  • Patent number: 6508879
    Abstract: A method of fabricating a group III-V nitride compound semiconductor in which high crystallinity is achieved without lack of nitrogen, even when it is grown at a low temperature, and a method of fabricating a semiconductor device employing the method of fabricating a group III-V nitride compound semiconductor are provided. Along with carrier gas, a gas source including a nitrogen-including compound such as hydrazine, a substitution product of hydrazine, amine or azide as a nitrogen source is supplied to a reaction tube of a MOCVD apparatus. These nitrogen-including compounds have higher decomposition efficiencies than those of ammonia. Therefore, even though MOCVD is performed at a growth temperature below or equal to 900° C., a large amount of nitrogen which contributes growth is supplied onto the growth surface of a substrate (that is, an underlying layer). As a result, crystallinity of the group III-V nitride compound semiconductor layer is improved.
    Type: Grant
    Filed: November 10, 2000
    Date of Patent: January 21, 2003
    Assignee: Sony Corporation
    Inventor: Shigeki Hashimoto
  • Patent number: 6500258
    Abstract: This invention relates to a method of growing a nitride semiconductor layer by molecular beam epitaxy comprising the steps of: a) heating a GaN substrate (S) disposed in a growth chamber (10) to a substrate temperature of at least 850° C.; and b) growing a nitride semiconductor layer on the GaN substrate by molecular beam epitaxy at a substrate temperature of at least 850° C., ammonia gas being supplied to the growth chamber (10) during the growth of the nitride semiconductor layer; wherein the method comprises the further step of commencing the supply ammonia gas to the growth chamber during step (a), before the substrate temperature has reached 800° C.
    Type: Grant
    Filed: June 18, 2001
    Date of Patent: December 31, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Edward Hooper, Jonathan Heffernan, Jennifer Mary Barnes, Alistair Henderson Kean
  • Publication number: 20020189533
    Abstract: The present invention utilizes magnesium diboride (MgB2) or (Mg1−xMx)B2 as a superconductivity thin film which can be applied to a rapid single flux quantum (RSFQ) circuit. A method for manufacturing a superconductor incorporating therein a superconductivity thin film, begins with preparing a single crystal substrate. Thereafter, a template film is formed on top of the substrate, wherein the template has a hexagonal crystal structure. The superconductivity thin film of MgB2 or (Mg1−xMx)B2 is formed on top of the template film. If Mg amount in the superconductivity thin film is insufficient, Mg vapor is flowed on the surface of the superconductivity thin film while a post annealing process is carried out at the temperature ranging from 400° C. to 900° C.
    Type: Application
    Filed: November 28, 2001
    Publication date: December 19, 2002
    Inventors: Jun Ho Kim, Sang Hyeob Kim, Gun Yong Sung
  • Publication number: 20020170489
    Abstract: Methods of crystal growth for semiconductor materials, such as nitride semiconductors, and methods of manufacturing semiconductor devices are provided. The method of crystal growth includes forming a number of island crystal regions during a first crystal growth phase and continuing growth of the island crystal regions during a second crystal growth phase while bonding of boundaries of the island crystal regions occurs. The second crystal growth phase can include a crystal growth rate that is higher than the crystal growth rate of the first crystal growth phase and/or a temperature that is lower than the first crystal growth phase. This can reduce the density of dislocations, thereby improving the performance and service life of a semiconductor device which is formed on a nitride semiconductor made in accordance with an embodiment of the present invention.
    Type: Application
    Filed: April 11, 2002
    Publication date: November 21, 2002
    Inventors: Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
  • Patent number: 6478873
    Abstract: A method of optimizing a process of selective epitaxial growth sets a guideline for the reaction temperature, pressure, and gas ratio and calculates a non-equilibrium factor (NEF=[exp(l−(A/B))×C−D]×F×(1/S)) depending on the characteristic of the equipment and the types of source gases by controlling a super-saturation ratio depending on a basic thermodynamic law. The selective epitaxial growth by CVD is a deposition method by which a reactive product by thermal activation of a reactive gas is obtained in the shape of a thin film. Therefore, it can successfully form the selective epitaxial growth through control of the super-saturation ratio so that the selective epitaxial growth can be optimized. Also, the method can optimize the process by monitoring the quality of the thin film such as selectivity securing control of deposition speed, facet, reduction in deflects, etch depending on the pattern material.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: November 12, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Woo Seock Cheong, Hai Won Kim
  • Patent number: 6471769
    Abstract: When nitride series III-V group compound semiconductor is manufactured by gas phase growing using starting material for a group III element, ammonia as a starting material for a group V element and hydrogen, the gas phase molar ratio of hydrogen to the total amount of hydrogen and ammonia (H2/(H2+NH3)) is specified to 0.3<(H2/(H2+NH3))<0.7, 0.3<(H2/(H2+NH3))<0.6 or 0.4<(H2/(H2+NH3))<0.5. A nitride series III-V group compound semiconductor can thus be manufactured with less non-emission center and of excellent crystallinity.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: October 29, 2002
    Assignee: Sony Corporation
    Inventors: Shigeki Hashimoto, Katsunori Yanashima, Tsunenori Asatsuma, Masao Ikeda
  • Patent number: 6464780
    Abstract: The invention relates to a method for the production of a monocrystalline layer on a substrate with a non-adapted lattice. To this end, a monocrystalline substrate with a buried amply defective layer and a monocrystalline layer produce thereon are used. The buried amply defective layer can be produced by hydrogen implantation.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: October 15, 2002
    Assignee: Forschungszentrum Julich GmbH
    Inventors: Siegfried Mantl, Bernhard Holländer, Ralf Liedtke
  • Patent number: 6458206
    Abstract: AFM/STM probes are based on whiskers grown by the vapor-liquid-solid (VLS) mechanism. Silicon cantilevers oriented along the crystallographic plane (111) are prepared from silicon-on-insulator structures that contain a thin layer (111) on a (100) substrate with SiO2 interposed layer. At removal of solidified alloy globules inherent in the growth mechanism sharpening of the whiskers takes place and, in such a way, the probes are formed. Cross-sections of the wiskers grown by the mechanism on the cantilevers can be controllably changed during the growth process so that step-shaped whiskers optimal for fabrication of the probes can be prepared. Also, whiskers with expansions/contractions can be formed that are important for fabrication of probes suitable for investigations in coarse surfaces, complicated cavitites, grooves typical for semiconductor microelectronics, etc.
    Type: Grant
    Filed: March 9, 2001
    Date of Patent: October 1, 2002
    Assignee: Crystals and Technologies, Ltd.
    Inventors: Evgeny Invievich Givargizov, Lidiya Nikolaevna Obolenskaya, Ala Nikolaevna Stepanova, Evgeniya Sergeevna Mashkova, Michail Evgenievich Givargizov
  • Patent number: 6451112
    Abstract: A crucible for growing a single crystal therein has a seed crystal attachment portion and a peripheral portion surrounding the seed crystal attachment portion through a gap provided therebetween. The seed crystal attachment portion has a support surface for holding a seed crystal on which the single crystal is to be grown, and the support surface is recessed from a surface of the peripheral portion. The seed crystal is attached to the support surface to cover an entire area of the support surface. Accordingly, no poly crystal is formed on the seed crystal attachment portion, and the single crystal can be grown on the seed crystal with high quality.
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: September 17, 2002
    Assignee: Denso Corporation
    Inventors: Kazukuni Hara, Kouki Futatsuyama, Shoichi Onda, Fusao Hirose, Emi Oguri, Naohiro Sugiyama, Atsuto Okamoto
  • Patent number: 6440214
    Abstract: A method of growing a nitride semiconductor layer, such as a GaN layer, by molecular beam epitaxy comprises the step of growing a GaAlN nucleation layer on a substrate by molecular beam epitaxy. The nucleation layer is annealed, and a nitride semiconductor layer is then grown over the nucleation layer by molecular beam epitaxy. The nitride semiconductor layer is grown at a V/III molar ratio of 100 or greater, and this enables a high substrate temperature to be used so that a good quality semiconductor layer is obtained. Ammonia gas is supplied during the growth process, to provide the nitrogen required for the MBE growth process.
    Type: Grant
    Filed: June 9, 2000
    Date of Patent: August 27, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Stewart Edward Hooper, Jennifer Mary Barnes, Jonathan Heffernan, Alistair Henderson Kean
  • Patent number: 6428621
    Abstract: A low defect (e.g., dislocation and micropipe) density silicon carbide (SiC) is provided as well as an apparatus and method for growing the same. The SiC crystal, growing using sublimation techniques, is preferably divided into two stages of growth. During the first stage of growth, the crystal grows in a normal direction while simultaneously expanding laterally. Although dislocation and other material defects may propagate within the axially grown material, defect propagation and generation in the laterally grown material are substantially reduced, if not altogether eliminated. After the crystal has expanded to the desired diameter, the second stage of growth begins in which lateral growth is suppressed and normal growth is enhanced. A substantially reduced defect density is maintained within the axially grown material that is based on the laterally grown first stage material.
    Type: Grant
    Filed: February 14, 2001
    Date of Patent: August 6, 2002
    Assignee: The Fox Group, Inc.
    Inventors: Yury Alexandrovich Vodakov, Mark Grigorievich Ramm, Evgeny Nikolaevich Mokhov, Alexandr Dmitrievich Roenkov, Yury Nikolaevich Makarov, Sergei Yurievich Karpov, Mark Spiridonovich Ramm, Heikki I. Helava
  • Patent number: 6428635
    Abstract: An alloy capable of forming a (100) [001] cube-texture by thermo-mechanical techniques has 5 to 45 atomic percent nickel with the balance being copper. The alloy is useful as a conductive substrate for superconducting composites where the substrate is coated with a superconducting oxide. A buffer layer can optionally be coated on the substrate to enhance deposition of the superconducting oxide. Methods for producing the alloys, substrates, and superconductors are included.
    Type: Grant
    Filed: October 1, 1997
    Date of Patent: August 6, 2002
    Assignees: American Superconductor Corporation, The Regents of the University of California
    Inventors: Leslie G. Fritzemeier, Elliott D. Thompson, Edward J. Siegal, Cornelis Leo Hans Thieme, Robert D. Cameron, James L. Smith, W. Larry Hults
  • Patent number: 6416578
    Abstract: There is disclosed a method for manufacturing a silicon carbide film in which a crystal orientation continued on a single crystal substrate surface and silicon carbide is allowed to epitaxially grow, the method comprising the steps of: entirely or partially providing the substrate surface with a plurality of undulations extended parallel in one direction; and allowing silicon carbide to grow on the substrate surface.
    Type: Grant
    Filed: February 29, 2000
    Date of Patent: July 9, 2002
    Assignee: Hoya Corporation
    Inventors: Yukitaka Nakano, Hiroyuki Nagasawa, Kuniaki Yagi, Takamitsu Kawahara
  • Patent number: 6372981
    Abstract: A group-IV semiconductor substrate has an inclined front surface, the inclination being toward a direction differing from the <010>crystal lattice direction. The substrate is cleansed by heating in the presence of a gas including a compound of the group-IV substrate element. A source gas of a group-III element is then supplied, forming an atomic film of the group-III element on the substrate surface. Starting at the same time, or shortly afterward, a source gas of a group-V element is supplied, and a III-V compound semiconductor hetero-epitaxial layer is grown. Chemical bonding of the group-III element to the group-IV substrate surface produces a crystal alignment of the hetero-epitaxial layer that leads to improved conversion efficiency when the semiconductor substrate is used in the fabrication of solar cells with compound semiconductor base and emitter layers.
    Type: Grant
    Filed: August 8, 2000
    Date of Patent: April 16, 2002
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Takashi Ueda, Chouho Yamagishi, Osamu Goto
  • Patent number: 6368405
    Abstract: A single crystal silicon growth apparatus, comprising: a chamber where a silicon substrate is to be inserted; a heat source for rising the temperature in an interior of the chamber; a cooling line for rapidly dropping the temperature in the interior of the chamber; a gas sprayer for providing a source gas and a purge gas inside the chamber; a gas inflow line connected to the gas sprayer for inflowing the source gas and the purge gas into the gas sprayer; and a gas exhausting line for maintaining the interior of the chamber with a vacuum.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: April 9, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventor: Seung Woo Shin
  • Publication number: 20010047751
    Abstract: A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1-y)1-xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.
    Type: Application
    Filed: November 24, 1999
    Publication date: December 6, 2001
    Inventors: ANDREW Y. KIM, EUGENE A. FITZGERALD
  • Patent number: 6296701
    Abstract: The present invention provides a biaxially textured laminate article having a polycrystalline biaxially textured metallic substrate with an electrically conductive oxide layer epitaxially deposited thereon and methods for producing same. In one embodiment a biaxially texture Ni substrate has a layer of LaNiO3 deposited thereon. An initial layer of electrically conductive oxide buffer is epitaxially deposited using a sputtering technique using a sputtering gas which is an inert or forming gas. A subsequent layer of an electrically conductive oxide layer is then epitaxially deposited onto the initial layer using a sputtering gas comprising oxygen. The present invention will enable the formation of biaxially textured devices which include HTS wires and interconnects, large area or long length ferromagnetic and/or ferroelectric memory devices, large area or long length, flexible light emitting semiconductors, ferroelectric tapes, and electrodes.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: October 2, 2001
    Assignee: UT-Battelle, LLC
    Inventors: David K. Christen, Qing He
  • Patent number: 6280523
    Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: August 28, 2001
    Assignee: LumiLeds Lighting, U.S., LLC
    Inventors: Carrie Carter Coman, Fred A. Kish, Jr., R. Scott Kern, Michael R. Krames, Paul S. Martin
  • Patent number: 6273949
    Abstract: A method for fabricating gallium arsenide (GaAs) based structure groups with inverted crystallographic orientation to form wavelength converters that utilizes germanium as a crystallographic neutral template layer deposited on a GaAs substrate. A crystallographic inverted gallium arsenide layer is grown on top of the template layer. In a selective trench etching process areas of the substrate are exposed again for a consecutive collective deposition of GaAs.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: August 14, 2001
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Loren A. Eyres, Martin M. Fejer, Christopher B. Ebert, James S. Harris
  • Patent number: 6270573
    Abstract: A silicon carbide thin film is epitaxially grown by an MBE or the like method with silicon atoms 2 being maintained to be in excess of carbon atoms on a growth surface 1a of a silicon carbide crystal in a substrate 1. A silicon carbide substrate with a good crystallinity is thereby achieved at a low temperature with a good reproducibility. This crystal growth is possible at a low temperature of 1300° C. or lower, and the productions of a high-concentration doped film, a selectively grown film, and a grown film of a cubic silicon carbide on a hexagonal crystal are achieved. In crystallizing a cubic silicon carbide on a hexagonal crystal, the use of an off-cut surface inclined towards a <1{overscore (1)}00> direction is effective to prevent an occurrence of twin.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: August 7, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi
  • Patent number: 6270574
    Abstract: A method of growing a Group III-V nitrite buffer layer on a substrate made of a different material by molecular beam epitaxy is provided, which compensates for lattice mismatching between a material of the substrate and a material of a further layer to be grown on the substrate. The method includes the steps of: placing the substrate in a vacuum chamber at a reduced pressure suitable for epitaxial growth and at an elevated temperature; and supplying species to the vacuum chamber to be used in the epitaxial growth including a nitrogen precursor species supplying nitrogen to the substrate to cause epitaxial growth on the substrate of the buffer layer. The elevated temperature is in the range of 300 to 800 ° C., and a supply rate of nitrogen to the substrate is such as to cause epitaxial growth on the substrate of the Group III-V nitride buffer layer of uniform thickness less than 2000 Å at a growth rate in the range of 2 to 10 &mgr;m/hr.
    Type: Grant
    Filed: July 14, 2000
    Date of Patent: August 7, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Stewart Edward Hooper
  • Patent number: 6225650
    Abstract: A GaN group crystal base member comprising a base substrate, a mask layer partially covering the surface of said base substrate to give a masked region, and a GaN group crystal layer grown thereon to cover the mask layer, which is partially in direct contact with the non-masked region of the base substrate, use thereof for a semiconductor element, manufacturing methods thereof and a method for controlling a dislocation line. The manufacturing method of the present invention is capable of making a part in the GaN group crystal layer, which is above a masked region or non-masked region, have a low dislocation density.
    Type: Grant
    Filed: March 24, 1998
    Date of Patent: May 1, 2001
    Assignee: Mitsubishi Cable Industries, Ltd.
    Inventors: Kazuyuki Tadatomo, Hiroaki Okagawa, Youichiro Ohuchi, Keiji Miyashita, Kazumasa Hiramatsu, Nobuhiko Sawaki, Katsunori Yahashi, Takumi Shibata
  • Patent number: 6176925
    Abstract: An n-doped, high quality gallium nitride substrate suitable for further device or epitaxial processing, and method for making the same. The nitride substrate is produced by epitaxial deposition of first metal nitride layer on a non-native substrate followed by a second deposition of metal nitride. During the second deposition of metal nitride, a liquid metal layer is formed at the interface of the non-native substrate and the metal nitride layer form. The formed metal nitride layer may be detached from the non-native substrate to provide an metal nitride substrate with a high quality inverse surface. A epitaxial metal nitride layer may be deposited on the inverse surface of metal nitride substrate. The metal nitride substrate and the epitaxial metal nitride layer thereon may be deposited using the same hydride vapor-phase epitaxy system.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: January 23, 2001
    Assignees: CBL Technologies, Inc., Matsushita Electronics Corporation
    Inventors: Glenn S. Solomon, David J. Miller, Tetsuzo Ueda
  • Patent number: 6159287
    Abstract: A vapor-phase deposition system includes one or more channel units for promoting the downstream passage of reagent gases. A reactor of a vapor-phase deposition system may include one or more channels to promote passage of reagent gases beneath a susceptor stage. A susceptor, for arrangement within a reactor during epitaxial growth on a substrate, may include a truncated stage and a truncation side. The substrate may be aligned with a lower edge of the truncated stage, thereby avoiding chemical deposition on surfaces upstream of the substrate. One or more channels of the susceptor promote the downstream passage of reagent gases within the reactor. Methods for vapor-phase deposition and for promoting downstream passage of reagent gases within a reactor are also disclosed.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: December 12, 2000
    Assignees: CBL Technologies, Inc., Matsushita Electronics Corporation
    Inventors: Glenn S. Solomon, David J. Miller, Tetsuzo Ueda
  • Patent number: 6146457
    Abstract: A method for producing thick, high quality GaN substrates uses an epitaxially deposited film is used as a substrate material for further device or epitaxial processing. The film is deposited using an epitaxial technique on a thin substrate called the disposable substrate. The deposited film is thick enough so that upon cooling the thermal mismatched strain is relieved through cracking of the lower disposable substrate and not the newly deposited epitaxy. The epitaxial film now becomes a platform for either further epitaxial deposition or device processing.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: November 14, 2000
    Assignee: CBL Technologies, Inc.
    Inventor: Glenn S. Solomon
  • Patent number: 6114287
    Abstract: The present invention provides methods and biaxially textured articles having a deformed epitaxial layer formed therefrom for use with high temperature superconductors, photovoltaic, ferroelectric, or optical devices. A buffer layer is epitaxially deposited onto biaxially-textured substrates and then mechanically deformed. The deformation process minimizes or eliminates grooves, or other irregularities, formed on the buffer layer while maintaining the biaxial texture of the buffer layer. Advantageously, the biaxial texture of the buffer layer is not altered during subsequent heat treatments of the deformed buffer. The present invention provides mechanical densification procedures which can be incorporated into the processing of superconducting films through the powder deposit or precursor approaches without incurring unfavorable high-angle grain boundaries.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: September 5, 2000
    Assignee: UT-Battelle, LLC
    Inventors: Dominic F. Lee, Donald M. Kroeger, Amit Goyal
  • Patent number: 6110277
    Abstract: A process for the fabrication on a monocrystal silicon substrate of epitaxial layers of a III-V nitride compound semi-conductor having the structure In.sub.x Al.sub.y Ga.sub.1-x-y N (0.ltoreq.x, 0.ltoreq.y, x+y.ltoreq.1). The process consists of the following steps. A parcel-like structure is created on the surface of a monocrystal silicon substrate. The silicon surface within the parcels is uncovered and the edges of the parcels are covered by a masking material. By means of epitaxial growth of the nitride compound semiconductor exclusively within the parcels on the silicon surface, local islands are created on whose edges the dislocations generated by the lattice mismatches are able to break down. Finally, components are fabricated in and on the parcels.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: August 29, 2000
    Assignee: Temic Telefunken microelectronic GmbH
    Inventor: Matthias Braun
  • Patent number: 6110278
    Abstract: A template for seeding growth of a desired single-crystal material (e.g., Si, GaAs) is created by passing through a monocrystalline channelizing mask, in a channelizing direction thereof, at least one of a nucleation-friendly species (e.g., Si, Ga) and a knock-off species (e.g., Ar, F) for respective implant of a nucleation-friendly species within or removal of a nucleation-unfriendly material (e.g., SiO.sub.2) of a supplied substrate. The desired single-crystal material is then grown in epitaxial-like manner from the thus-formed seeding-template. In one embodiment, silicon ions are projected through a monocrystalline silicon mask of a selected crystal orientation ((100), or (111)) in its channelizing direction so as to implant the silicon ions in a silicon dioxide layer of a supplied substrate according to the selected crystal orientation of the channelizing mask. Monocrystalline silicon is then epitaxially grown on top of the silicon dioxide layer with the same crystal orientation.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: August 29, 2000
    Inventor: Arjun N. Saxena
  • Patent number: 6103019
    Abstract: A method for producing a pattern of regularly spaced-apart nucleation sites and corresponding devices are disclosed. The method enables formation of a device having an amorphous or otherwise non-single crystal surface from which single crystal layers of a desired orientation may be grown using the regularly spaced nucleation sites as a growth template. The method can be used to produce a single crystal semiconductor layer of a desired orientation (e.g., <100> or <111>) on an amorphous insulating layer (e.g. of SiO.sub.2 or Si.sub.3 N.sub.4). For example, single crystal Si of a <100> orientation may be grown on an SiO.sub.2 layer. Monocrystalline semiconductor films may be similarly grown on amorphous glass substrates or the like for producing solar cells of high efficiency and low cost.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: August 15, 2000
    Inventor: Arjun Saxena
  • Patent number: 6096130
    Abstract: A method of crystal growth of a GaN layer with an extremely high surface planarity over a GaAs substrate is provided, wherein a GaAs substrate is heated to a temperature in the range of 600.degree. C. to 700.degree. C. without supplying any group-V element including arsenic to form a Ga-rich surface on the GaAs substrate, before a first source material including N and a second source material including Ga are supplied along with a carrier gas onto a surface of the GaAs substrate to form a GaN layer over the GaAs substrate.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: August 1, 2000
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido
  • Patent number: 6090358
    Abstract: A novel material Si.sub.X C.sub.y N.sub.z, having a crystal structure similar to that of a.Si.sub.3 N.sub.4 with carbon atoms substituting most of the Si sites, is synthesized in crystalline form onto crystalline Si substrates by microwave plasma enhanced decomposition of carbon, silicon and nitrogen containing gasses.
    Type: Grant
    Filed: August 20, 1997
    Date of Patent: July 18, 2000
    Assignee: National Science Council of Republic of China
    Inventors: Li-Chyong Chen, Kuei-Hsien Chen, Dhananjay Manohar Bhusari, Chun-Ku Chen
  • Patent number: 6063187
    Abstract: A method for the growth of diamond on a substrate combines an ECR (Electron cyclotron resonance) MPCVD (Microwave plasma chemical vapor deposition) method with a MPCVD method in one system. A two-step diamond growing method comprises firstly etching and nucleation performed by the ECR method and then diamond grown by the microwave plasma CVD method. Not only are high quality continuous polycrystalline diamond films on silicon wafer obtained but also heteroepitaxial growth has been achieved in the present invention. Auger electron spectroscopy (AES), scanning electron microscopy (SEM) and Raman spectroscopy have been used to characterize the structure and morphology of the synthesized diamond films.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: May 16, 2000
    Assignee: City University of Hong Kong
    Inventors: Shuit Tong Lee, Chun Sing Lee, Yat Wah Lam, Zhangda Lin
  • Patent number: 6045614
    Abstract: A method is provided for depositing a (111)-oriented heteroepitaxial II-VI alloy film on Si substrates. The (111)-oriented heteroepitaxial II-VI alloy film may comprise II-VI semiconductor and/or II-VI semimetal. As such, the method of the present invention provides a means for growing a (111)-oriented heteroepitaxial II-VI semiconductor film or a (111)-oriented heteroepitaxial II-VI semimetal film. The method of the present invention overcomes the inherent difficulties associated with forming (111)-oriented heteroepitaxial II-VI alloy films on Si(001). These difficulties include twin formation and poor crystalline quality. The novelty of the method of the present invention consists principally in choosing a Si substrate having a surface which has a specific Si crystallographic orientation. In particular, the present invention utilizes a Si surface having a crystallographic orientation near Si(111) rather than Si(001). The Si surface is vicinal Si(111).
    Type: Grant
    Filed: March 14, 1996
    Date of Patent: April 4, 2000
    Assignee: Raytheon Company
    Inventors: Terence J. de Lyon, Scott M. Johnson
  • Patent number: 6039803
    Abstract: A method of processing semiconductor materials, including providing a monocrystalline silicon substrate having a (001) crystallographic surface orientation; off-cutting the substrate to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and epitaxially growing a relaxed graded layer of a crystalline GeSi on the substrate. A semiconductor structure including a monocrystalline silicon substrate having a (001) crystallographic surface orientation, the substrate being off-cut to an orientation from about 2.degree. to about 6.degree. offset towards the [110] direction; and a relaxed graded layer of a crystalline GeSi which is epitaxially grown on the substrate.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: March 21, 2000
    Assignee: Massachusetts Institute of Technology
    Inventors: Eugene A. Fitzgerald, Srikanth B. Samavedam
  • Patent number: 6036773
    Abstract: A Group III atomic layer required for fabrication of a semiconductor quantum nanostructure is grown to be properly restricted to a monolayer.A substrate is configured to have a fast-growth surface portion where growth of a Ga atomic layer proceeds at a relatively high rate and a slow-growth surface portion where the growth of the Ga atomic layer proceeds at a relatively low rate. Ga atoms are supplied to the fast-growth surface portion in an amount not less than that which grows one layer of the Group III atoms. Excess Ga atoms on the fast-growth surface portion are allowed to migrate to the slow-growth surface portion by surface migration, thereby growing only one layer of the Ga atoms on the fast-growth surface portion.
    Type: Grant
    Filed: March 27, 1997
    Date of Patent: March 14, 2000
    Assignee: Agency of Industrial Science & Technology, Ministry of International Trade & Industry
    Inventors: Xue-Lun Wang, Mutsuo Ogura
  • Patent number: 6030452
    Abstract: A method of manufacturing a semiconductor device includes the steps of preparing a semiconductor substrate having a step on a surface thereof and growing a group III-V compound semiconductor layer on a surface of the semiconductor substrate by metal organic vapor phase epitaxy using a source gas added with halogenated hydrocarbon containing one or two halogen atoms per one molecule. The surface of a substrate with a step thereon can be planarized by depositing an embedding layer on a lower level area.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: February 29, 2000
    Assignee: Fujitsu Limited
    Inventor: Tatsuya Takeuchi
  • Patent number: 6001174
    Abstract: A method to grow diamond crystal by an utilization of liquid template on which carbon precursor is deposited. The liquid template is to replace the conventional solid template to improve the quality and the size of the diamond crystal through the inherent property of the liquid. Its ideal smoothness, its amorphosity and therefore, an absence of the grain boundary, and its high surface mobility for carbon aggregation to form diamond crystal, thus to grow diamond crystal.
    Type: Grant
    Filed: March 11, 1998
    Date of Patent: December 14, 1999
    Assignee: Richard J. Birch
    Inventor: Pao-Hsien Fang
  • Patent number: 5993543
    Abstract: The first object of the present invention is to provide a PDP with improved panel brightness which is achieved by improving the efficiency in conversion from discharge energy to visible rays. The second object of the present invention is to provide a PDP with improved panel life which is achieved by improving the protecting layer protecting the dielectrics glass layer. To achieve the first object, the present invention sets the amount of xenon in the discharge gas to the range of 10% by volume to less than 100% by volume, and sets the charging pressure for the discharge gas to the range of 500 to 760 Torr which is higher than conventional charging pressures. With such construction, the panel brightness increases. Also, to achieve the second object, the present invention has, on the surface of the dielectric glass layer, a protecting layer consisting of an alkaline earth oxide with (100)-face or (110)-face orientation.
    Type: Grant
    Filed: July 9, 1997
    Date of Patent: November 30, 1999
    Assignee: Masaki Aoki Et Al.
    Inventors: Masaki Aoki, Hideo Torii, Eiji Fujii, Mitsuhiro Ohtani, Takashi Inami, Hiroyuki Kawamura, Hiroyoshi Tanaka, Ryuichi Murai, Yasuhisa Ishikura, Yutaka Nishimura, Katsuyoshi Yamashita
  • Patent number: 5972108
    Abstract: Method of preferentially-ordering a thermally sensitive element (50) may comprise the step of forming a first thin film layer of electrically conductive material (75). A thin film layer of thermally sensitive material (80) may be formed on a surface of the first layer of electrically conductive material (75). A second thin film layer of electrically conductive material (85) of lanthanum strontium cobalt oxide (LSCO) may be formed on a surface of the layer of thermally sensitive material (80) opposite the first thin film layer (75). A nucleation layer (87) may be formed in communication with the surface of the layer of thermally sensitive material (80) opposite the first thin film layer (75). The layer of thermally sensitive material (80) may be crystallized beginning at the surface of the thermally sensitive layer (80) in communication with nucleation layer (87). The nucleation layer (87) may be removed.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: October 26, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: Howard R. Beratan, Charles M. Hanson
  • Patent number: 5951756
    Abstract: A method of forming GaAs/AlGaAs hetero-structure. The method includes the steps of preparing a GaAs substrate having a (411)A-oriented surface and setting the GaAs substrate inside a growth container with the (411)A surface being disposed as a surface to be deposited. The pressure inside the growth chamber is reduced and the GaAs substrate is heated up to a predetermined temperature to cause epitaxial growth of Ga, Al, As on the (411)A substrate and forming a GaAs/AlGaAs hetero-structure on the (411)A-oriented GaAs substrate.
    Type: Grant
    Filed: February 13, 1996
    Date of Patent: September 14, 1999
    Assignee: Kubota Corporation
    Inventors: Satoshi Hiyamizu, Satoshi Shimomura, Yasunori Okamoto
  • Patent number: 5944890
    Abstract: In a method of producing single crystals on a seed crystal, the seed crystal is covered by a protection layer except for a surface on which the single crystals are to be formed. The protection layer is made of material such as carbon or the like, which is stable in a step of forming the single crystals. As a result, a temperature gradient and mass transfer in the seed crystal can be prevented, whereby quality of the single crystals formed on the seed crystal can be improved.
    Type: Grant
    Filed: March 28, 1997
    Date of Patent: August 31, 1999
    Assignee: Denso Corporation
    Inventors: Yasuo Kitou, Naohiro Sugiyama, Atsuto Okamoto, Toshihiko Tani, Nobuo Kamiya
  • Patent number: 5919305
    Abstract: A concept and process is disclosed by which an epitaxially deposited film is removed from its substrate at elevated temperatures to inhibit thermal mismatch strain induced defect generation in the epitaxial layer. The process occurs by gas phase reactions of an intermediate layer purposely deposited to react with a component in the gas stream during or after epitaxial growth. While the concept of an intermediate layer has been used extensively to improve the crystal quality of the epitaxial layer this is not the purpose of this interlayer. Although this interlayer may aid in nucleation of the epitaxial layer, the objective is to separate the epitaxial material on top of the interlayer from the substrate below the interlayer at or near the growth temperature to reduce the effects of the thermal mismatch between the substrate and epitaxial layers. An application is an addition to the above invention. A thick epitaxially deposited film can now be removed from its substrate at elevated temperatures.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: July 6, 1999
    Assignee: CBL Technologies, Inc.
    Inventor: Glenn S. Solomon
  • Patent number: 5855669
    Abstract: A grating coupler is formed by growing an optical waveguide layer on a substrate by an epitaxial growing process such as a metalorganic chemical vapor deposition and a molecular beam deposition. The optical waveguide layer has a surface on which a cross-hatch pattern serving as the grating is continuously formed. The optical waveguide layer is formed with a material having a reflective index greater than a reflective index of the substrate or an atmosphere. Specifically, the substrate is formed with GaAs and the optical waveguide layer is formed with InGaAs. Further, the substrate is an on-substrate having an orientation coinciding with a ?100! plane, so as to form the optical waveguide layer having continuous cross-hatch patterns on the surface thereof. The spacing between the cross-hatch patterns can be varied according to variation of a growth temperature of the optical waveguide layer.
    Type: Grant
    Filed: April 17, 1997
    Date of Patent: January 5, 1999
    Assignee: Electronics And Telecommunications Research Institute
    Inventors: Jong-Hyeob Baek, Bun Lee
  • Patent number: 5849077
    Abstract: A method of growing epitaxial regions comprising the steps of providing a silicon substrate, forming a patterned oxide layer having a planar upper surface on the substrate, the oxide layer having an aperture therein extending to the substrate, forming a layer of silicon in the aperture extending above the surface of the oxide layer and removing the portion of the layer of silicon extending above the surface of the oxide layer. The sidewalls of the oxide layer defining the aperture are outwardly sloped in the direction of the upper surface. The layer of silicon is formed by a procedure which forms crystalline silicon in the aperture and forms no silicon over the oxide layer. The portion of the layer of silicon extending above the surface of the oxide layer is removed by a chemical-mechanical polishing operation. In addition, to provide auto-alignment, the layer of oxide is selectively etched relative to the layer of silicon to provide a step at the interface of the layer of oxide and the layer of silicon.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: December 15, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Danny J. Kenney
  • Patent number: 5843227
    Abstract: A crystal growth method for growing on a gallium arsenide (GaAs) substrate a gallium nitride (GaN) film which is good in surface flatness and superior in crystallinity. According to the method, a GaAs substrate having a surface which is inclined with respect to the GaAs(100) face is used. The inclination angle of the substrate surface is larger than 0 degree but smaller than 35 degrees with respect to the GaAs(100) face. The inclination direction of the substrate surface is within a range of an angular range from the ?0,0,1! direction of GaAs to the ?0,-1,0! direction past the ?0,-1,1! direction and angles less than 5 degrees on opposite sides of the angular range around an ?1,0,0! direction of gallium arsenide taken as an axis, or within another range crystallographically equivalent to the range. The GaN layer is formed on the surface of the GaAs substrate preferably by hydride vapor deposition method.
    Type: Grant
    Filed: January 13, 1997
    Date of Patent: December 1, 1998
    Assignee: NEC Corporation
    Inventors: Akitaka Kimura, Haruo Sunakawa, Masaaki Nido, Atsushi Yamaguchi
  • Patent number: 5833749
    Abstract: A compound semiconductor substrate having at least one compound semiconductor layer epitaxially grown on a silicon single crystal substrate, wherein the silicon single crystal substrate has a surface on which the compound semiconductor layer is epitaxially grown, the surface being inclined at an off angle of not more than 1 deg to a (100) plane of silicon crystal; and the compound semiconductor layer has a free or top surface having a roughness of 3 nm or less in terms of a mean square roughness, Rms, determined by an atomic force microscopic measurement in a view field area of 10 .mu.m.times.10 .mu.m or a roughness of 10.5 nm or less in terms of a maximum height difference, Ry.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: November 10, 1998
    Assignee: Nippon Steel Corporation
    Inventors: Akihiro Moritani, Aiji Yabe, Akiyoshi Tachikawa, Takashi Aigo
  • Patent number: 5807433
    Abstract: The present invention concerns a novel multilayer system comprising a diamond layer, and the method of manufacturing this multilayer system.The invention concerns a multilayer system comprising a metallic substrate, an interphase and a diamond layer, the interphase being composed of the product of thermal decomposition of at least one metallocene compound.This multilayer system, capable of being used as an electrode, has improved adhesion between the substrate and the diamond layer.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: September 15, 1998
    Assignee: Eastman Kodak Company
    Inventors: Olivier Jean Christian Poncelet, Jean-Jacques Edgar Garenne
  • Patent number: 5759264
    Abstract: A method for a vapor-phase growth of a GaAs.sub.1-x P.sub.x epitaxial layer having a uniform thickness is disclosed. This method allows the GaAs.sub.1-x P.sub.x epitaxial layer (wherein x stands for an alloy composition satisfying the expression, 0.ltoreq.x.ltoreq.1) to be formed on a plurality of semiconductor single crystal substrates 1 by setting the semiconductor single crystal substrates 1 in place on a wafer holder 16 disposed inside a vapor-phase growth apparatus 30 in an amount of not less than 70% as the covering ratio of the total surface area of the substrates to the surface area of the wafer holder 16.
    Type: Grant
    Filed: March 21, 1996
    Date of Patent: June 2, 1998
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Masataka Watanabe, Tsuneyuki Kaise, Masayuki Shinohara, Masahisa Endo
  • Patent number: 5755879
    Abstract: A method is presented to manufacture substrates for growing monocrystalline diamond films by chemical vapor deposition (CVD) on large area at low cost. The substrate materials are either Pt or its alloys, which have been subject to a single or multiple cycle of cleaning, roller press, and high temperature annealing processes to make the thickness of the substrate materials to 0.5 mm or less, or most preferably to 0.2 mm or less, so that either (111) crystal surfaces or inclined crystal surfaces with angular deviations within .+-.10 degrees from (111), or both, appear on the entire surfaces or at least part of the surfaces of the substrates. The annealing is carried out at a temperature above 800.degree. C. The present invention will make it possible to markedly improve various characteristics of diamond films, and hence put them into practical use.
    Type: Grant
    Filed: November 17, 1995
    Date of Patent: May 26, 1998
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Yoshihiro Shintani, Takeshi Tachibana, Kozo Nishimura, Koichi Miyata, Yoshihiro Yokota, Koji Kobashi