Using An Organic Precursor (e.g., Propane, Metal-organic, Mocvd, Movpe) Patents (Class 117/104)
-
Patent number: 8048225Abstract: The present invention includes a high-quality, large-area bulk GaN seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal is of ultra-low defect density, has flat surfaces free of bowing, and is free of foreign substrate material. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.Type: GrantFiled: September 9, 2009Date of Patent: November 1, 2011Assignee: Soraa, Inc.Inventors: Christiane Poblenz, Mathew C. Schmidt, Derrick S. Kamber
-
Patent number: 8048223Abstract: The present invention provides in one example embodiment a synthetic diamond and a method of growing such a diamond on a plurality of seed diamonds, implanting the grown diamond with ions, and separating the grown diamond from the plurality of seed diamonds.Type: GrantFiled: July 21, 2005Date of Patent: November 1, 2011Assignee: Apollo Diamond, Inc.Inventors: Alfred Genis, Robert C. Linares, Patrick J. Doering
-
Publication number: 20110262773Abstract: A high-quality, large-area seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal comprises double-side GaN growth on a large-area substrate. The seed crystal is of relatively low defect density and has flat surfaces free of bowing. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.Type: ApplicationFiled: July 1, 2011Publication date: October 27, 2011Applicant: Soraa, IncInventors: Christiane Poblenz, James S. Speck, Derrick S. Kamber
-
Patent number: 8043429Abstract: The present invention relates to a method for fabricating a filament type high-temperature superconducting wire in which a thin film type high-temperature superconducting wire is fabricated into a filament shape suitable for use with alternating current.Type: GrantFiled: March 28, 2007Date of Patent: October 25, 2011Assignee: Korea Polytechnic UniversityInventors: Hee Gyoun Lee, Gye Won Hong, Kyeong Dal Choi
-
Publication number: 20110254134Abstract: The non-polar or semi-polar Nitride film is grown using Metal Organic Vapor Phase Epitaxy over a substrate. The in-situ grown seed layer comprising Magnesium and Nitrogen is deposited prior to the Nitride film growth. The said seed layer enhances the crystal growth of the Nitride material and makes it suitable for electronics and optoelectronics applications. The use of non-polar and/or semi-polar epitaxial films of the Nitride materials allows avoiding the unwanted effects related to polarization fields and associated interface and surface charges, thus significantly improving the semiconductor device performance and efficiency. In addition, the said seed layer is also easily destroyable by physical or chemical stress, including the ability to dissolve in water or acid, which makes the substrate removal process available and easy.Type: ApplicationFiled: April 15, 2011Publication date: October 20, 2011Inventors: Theeradetch Detchprohm, Mingwei Zhu, Christian Wetzel
-
Patent number: 8017416Abstract: Presented is a method for the production of a plurality of optoelectronic semiconductor chips each having a plurality of structural elements with at least one semiconductor layer. The method involves providing a chip composite base that includes a substrate and a growth surface. A mask material layer is formed on the growth surface. The mask material layer includes a multiplicity of windows having an average extent of less than or equal to 1 ?m. A mask material is chosen so that a semiconductor material of the semiconductor layer that is to be grown essentially cannot grow on the mask material or can grow in a substantially worse manner in comparison with the growth surface. Subsequently, semiconductor layers are deposited essentially simultaneously onto regions of the growth surface that lie within the windows. The chip composite base with applied material is singulated to form semiconductor chips.Type: GrantFiled: July 22, 2004Date of Patent: September 13, 2011Assignee: OSRAM Opto Semiconductors GmbHInventor: Volker Härle
-
Patent number: 7993455Abstract: A polycrystalline silicon production apparatus is provided whereby when deposited silicon is caused to drip down into an underlying collection part by heating the reaction tube inner surface at a temperature equal to or above the melting point of silicon, the silicon melt can be prevented from solidifying at a lower end portion of the reaction tube due to temperature lowering at the lower end portion. When a reaction tube is heated with a high frequency heating coil, the temperature lowering at a lower end portion of the reaction tube is prevented through temperature lowering prevention means which may be an infrared device capable of heating the outer periphery of the lower end portion by means of infrared rays, or which may be a lower end coil that is constituted by a coil near the lower end of the high frequency heating coil and has an increased heating intensity relative to an upper coil.Type: GrantFiled: August 17, 2004Date of Patent: August 9, 2011Assignee: Tokuyama CorporationInventors: Junichirou Nakashima, Hiroyuki Oda
-
Patent number: 7976899Abstract: Embodiments of the invention include a selective deposition method that allows for coating of selective portions of an object, such as an electronic device, and inhibits coating of other selective portions of the object, such as the electric contacts. The selective deposition method includes providing a web to transport the object through a deposition chamber. The web may include and reference mechanisms to register the object relative to the web. The method further includes providing deposition material and a shadow mask that has open spaces in it to inhibit coating selective portions of the object. The deposition material serves as the coating material.Type: GrantFiled: October 23, 2006Date of Patent: July 12, 2011Assignee: General Electric CompanyInventors: Min Yan, Ahmet Gun Erlat, Paul Alan McConnelee, Anil Raj Duggal, Svetlana Rogojevic
-
Patent number: 7976630Abstract: A high-quality, large-area seed crystal for ammonothermal GaN growth and method for fabricating. The seed crystal comprises double-side GaN growth on a large-area substrate. The seed crystal is of relatively low defect density and has flat surfaces free of bowing. The seed crystal is useful for producing large-volume, high-quality bulk GaN crystals by ammonothermal growth methods for eventual wafering into large-area GaN substrates for device fabrication.Type: GrantFiled: September 9, 2009Date of Patent: July 12, 2011Assignee: Soraa, Inc.Inventors: Christiane Poblenz, James S. Speck, Derrick S. Kamber
-
Publication number: 20110160065Abstract: An electronic component that includes a substrate and a phase-separated layer supported on the substrate and a method of forming the same are disclosed. The phase-separated layer includes a first phase comprising lanthanum manganate (LMO) and a second phase selected from a metal oxide (MO), metal nitride (MN), a metal (Me), and combinations thereof. The phase-separated material can be an epitaxial layer and an upper surface of the phase-separated layer can include interfaces between the first phase and the second phase. The phase-separated layer can be supported on a buffer layer comprising a composition selected from the group consisting of IBAD MgO, LMO/IBAD-MgO, homoepi-IBAD MgO and LMO/homoepi-MgO. The electronic component can also include an electronically active layer supported on the phase-separated layer.Type: ApplicationFiled: November 17, 2010Publication date: June 30, 2011Applicant: UT-Battelle, LLCInventors: Tolga Aytug, Mariappan Parans Paranthaman, Ozgur Polat
-
Patent number: 7964483Abstract: The present invention relates to a method for growing a nitride semiconductor epitaxial layer, which comprises the steps of growing a second nitride semiconductor epitaxial layer on a first nitride semiconductor epitaxial layer at a first temperature, growing a third nitride semiconductor epitaxial layer on the second nitride semiconductor epitaxial layer at a second temperature, and releasing nitrogen from the second nitride semiconductor epitaxial layer by increasing a temperature to a third temperature higher than the second temperature, thereby, it is possible to lower the defect density of epitaxial layers and reduce warpage of a substrate.Type: GrantFiled: July 7, 2004Date of Patent: June 21, 2011Assignee: Seoul National University Industry FoundationInventors: Euijoon Yoon, Hyunseok Na
-
Patent number: 7955435Abstract: A method for minimizing particle generation during deposition of a graded Si.sub.1-xGe.sub.x layer on a semiconductor material includes providing a substrate in an atmosphere including a Si precursor and a Ge precursor, wherein the Ge precursor has a decomposition temperature greater than germane, and depositing the graded Si.sub.1-xGe.sub.x layer having a final Ge content of greater than about 0.15 and a particle density of less than about 0.3 particles/cm.sup.2 on the substrate.Type: GrantFiled: February 24, 2010Date of Patent: June 7, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Eugene Fitzgerald, Richard Westhoff, Matthew T. Currie, Christopher J. Vineis, Thomas A. Langdo
-
Patent number: 7955959Abstract: A method for manufacturing GaN-based film LED based on masklessly transferring photonic crystal structure is disclosed. Two dimensional photonic crystals are formed on a sapphire substrate. Lattice quality of GaN-based epitaxy on the sapphire substrate is improved, and the internal quantum efficiency of GaN-based LED epitaxy is increased. After the GaN-based film is transferred onto heat sink substrate, the two dimensional photonic crystals structure is masklessly transferred onto the light exiting surface of the GaN-based film by using different etching rates between the GaN material and the SiO2 mask, so that light extraction efficiency of the GaN-based LED is improved. That is, the GaN-based film LED according to the invention has a relatively high illumination efficiency and heat sink.Type: GrantFiled: September 23, 2010Date of Patent: June 7, 2011Assignee: Xiamen Sanan Optoelectronics Technology Co., Ltd.Inventors: Jyh Chiarng Wu, Xuejiao Lin, Qunfeng Pan, Meng Hsin Yeh, Huijun Huang
-
Patent number: 7947128Abstract: In one embodiment the present invention provides for a method for depositing a thin film layer onto a composite tape 16, that comprises depositing at least one thin film layer of physically enhancing material 30 onto at least one portion of the composite tape. The depositing is accomplished by atomic layer epitaxy and the thin film layer is approximately 1-10 molecules thick.Type: GrantFiled: June 28, 2007Date of Patent: May 24, 2011Assignee: Siemens Energy, Inc.Inventor: Douglas J. Conley
-
Patent number: 7935617Abstract: A method of providing a layer in a semiconductor device, wherein the layer includes Si1-x-yGexCy, and wherein the carbon in the layer is in a stable condition, includes preparing a silicon substrate; preparing a SiGeC precursor; forming a Si1-x-yGexCy layer on the silicon substrate from the precursor; forming a top silicon layer on the Si1-x-yGexCy layer; and completing the semiconductor device.Type: GrantFiled: August 31, 2004Date of Patent: May 3, 2011Assignee: Sharp Laboratories of America, Inc.Inventor: Douglas J. Tweet
-
Publication number: 20110089433Abstract: In order to provide a method for manufacturing a single crystal SiC substrate that can obtain an SiC layer with good crystallinity, an Si substrate 1 having a surface Si layer 3 of a predetermined thickness and an embedded insulating layer 4 is prepared, and when the Si substrate 1 is heated in a carbon-series gas atmosphere to convert the surface Si layer 3 into a single crystal SiC layer 6, surface Si layer 3 into a single crystal SIC layer 6, the Si layer in the vicinity of an interface 8 with the embedded insulating layer 4 is left as a residual Si layer 5.Type: ApplicationFiled: June 9, 2009Publication date: April 21, 2011Inventors: Keisuke Kawamura, Katsutoshi Izumi, Hidetoshi Asamura, Takashi Yokoyama
-
Publication number: 20110083601Abstract: Embodiments of the invention generally relate processes for epitaxial growing Group III/V materials at high growth rates, such as about 30 ?m/hr or greater, for example, about 40 ?m/hr, about 50 ?m/hr, about 55 ?m/hr, about 60 ?m/hr, or greater. The deposited Group III/V materials or films may be utilized in solar, semiconductor, or other electronic device applications. In some embodiments, the Group III/V materials may be formed or grown on a sacrificial layer disposed on or over the support substrate during a vapor deposition process. Subsequently, the Group III/V materials may be removed from the support substrate during an epitaxial lift off (ELO) process. The Group III/V materials are thin films of epitaxially grown layers which contain gallium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium arsenide nitride, gallium aluminum indium phosphide, phosphides thereof, nitrides thereof, derivatives thereof, alloys thereof, or combinations thereof.Type: ApplicationFiled: October 13, 2010Publication date: April 14, 2011Applicant: Alta Devices, Inc.Inventors: Lori D. WASHINGTON, David P. BOUR, Gregg HIGASHI, Gang HE
-
Publication number: 20110064103Abstract: A dislocation-free high quality template with relaxed lattice constant, fabricated by spatially restricting misfit dislocation(s) around heterointerfaces. This can be used as a template layer for high In composition devices. Specifically, the present invention prepares high quality InGaN templates (In composition is around 5-10%), and can grow much higher In-composition InGaN quantum wells (QWs) (or multi quantum wells (MQWs)) on these templates than would otherwise be possible.Type: ApplicationFiled: August 23, 2010Publication date: March 17, 2011Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Hiroaki Ohta, Feng Wu, Anurag Tyagi, Arpan Chakraborty, James S. Speck, Steven P. DenBaars, Shuji Nakamura, Erin C. Young
-
Publication number: 20110056429Abstract: A method for rapid growth of gallium and nitrogen containing material is described. The method includes providing a bulk gallium and nitrogen containing substrate. A first epitaxial material of first thickness is formed over the substrate, preferably with a pseudomorphical process. The method also forms a second epitaxial layer over the first to create a stacked structure. The stacked structure consists of a total thickness of less than about 2 microns.Type: ApplicationFiled: August 18, 2010Publication date: March 10, 2011Applicant: Soraa, Inc.Inventors: James Raring, Arpan Chakraborty, Christiane Poblenz
-
Patent number: 7896965Abstract: A method for the production of a plurality of optoelectronic semiconductor chips each having a plurality of structural elements with respectively at least one semiconductor layer. The method involves providing a chip composite base having a substrate and a growth surface. A non-closed mask material layer is grown onto the growth surface in such a way that the mask material layer has a plurality of statistically distributed windows having varying forms and/or opening areas, a mask material being chosen in such a way that a semiconductor material of the semiconductor layer that is to be grown in a later method step essentially cannot grow on said mask material or can grow in a substantially worse manner in comparison with the growth surface. Subsequently, semiconductor layers are deposited essentially simultaneously onto regions of the growth surface that lie within the windows. A further method step is singulation of the chip composite base with applied material to form semiconductor chips.Type: GrantFiled: July 22, 2004Date of Patent: March 1, 2011Assignee: OSRAM Opto Semiconductors GmbHInventor: Volker Härle
-
Publication number: 20110045281Abstract: A method for reducing/eliminating basal plane dislocations from SiC epilayers is disclosed. An article having: an off-axis SiC substrate having an off-axis angle of no more than 6°; and a SiC epitaxial layer grown on the substrate. The epitaxial layer has no more than 2 basal plane dislocations per cm2 at the surface of the epitaxial layer. A method of growing an epitaxial SiC layer on an off-axis SiC substrate by: flowing a silicon source gas, a carbon source gas, and a carrier gas into a growth chamber under growth conditions to epitaxially grow SiC on the substrate in the growth chamber. The substrate has an off-axis angle of no more than 6°. The growth conditions include: a growth temperature of 1530-1650° C.; a pressure of 50-125 mbar; a C/H gas flow ratio of 9.38×10?5-1.5×10?3; a C/Si ratio of 0.5-3; a carbon source gas flow rate during ramp to growth temperature from 0 to 15 sccm; and an electron or hole concentration of 1013-1019/cm3.Type: ApplicationFiled: August 20, 2010Publication date: February 24, 2011Applicant: The Government of the United States of America, as represented by the Secretary of the NavyInventors: Rachael L. Myers-Ward, David Kurt Gaskill, Brenda L. VanMil, Robert E. Stahlbush, Charles R. Eddy, JR.
-
Patent number: 7892356Abstract: It is an object of the present invention to provide a diamond substrate with high toughness, a large surface area, and high quality, for use in semiconductor materials, electronic components, optical components, and so forth, and a method for manufacturing this substrate. A diamond polycrystalline film is laminated on the surface of a diamond monocrystalline substrate to create a diamond composite substrate. In said diamond composite substrate, it is preferable that the main face, which has the largest surface area of the diamond monocrystalline substrate, be the {100} plane, and the diamond polycrystalline film be laminated on the opposite face parallel to this face. The diamond monocrystalline substrate 3 may be made up of a plurality of diamond monocrystals having the same orientation of the main face, and these plurality of diamond monocrystals may be joined by a diamond crystal layer 4 to create a diamond composite substrate 2.Type: GrantFiled: January 22, 2004Date of Patent: February 22, 2011Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kiichi Meguro, Yoshiyuki Yamamoto, Takahiro Imai
-
Publication number: 20110039071Abstract: There are provided a method for manufacturing a Si(1-v-w-x)CwAlxNv substrate having a reduced number of cracks and high processibility, a method for manufacturing an epitaxial wafer, a Si(1-v-w-x)CwAlxNv substrate, and an epitaxial wafer. A method for manufacturing a Si(1-v-w-x)CwAlxNv substrate 10a includes the following steps. First, a Si substrate 11 is prepared. A Si(1-v-w-x)CwAlxNv layer (0<v<1, 0<w<1, 0<x<1, and 0<v+w+x<1) is then grown on the Si substrate at a temperature below 550° C.Type: ApplicationFiled: April 17, 2009Publication date: February 17, 2011Applicant: Sumitomo Electric Industries, LtdInventors: Issei Satoh, Michimasa Miyanaga, Shinsuke Fujiwara, Hideaki Nakahata
-
Patent number: 7887634Abstract: In a method of producing a semiconductor element in a substrate, a plurality of carbide precipitates is formed in the substrate, doping atoms are implanted into the substrate, thereby forming crystal defects in the substrate, the substrate is heated, such that at least a part of the crystal defects is eliminated using the carbide precipitates, and the semiconductor element is formed using the doping atoms.Type: GrantFiled: December 22, 2006Date of Patent: February 15, 2011Assignee: Infineon Technologies AGInventor: Luis-Felipe Giles
-
Patent number: 7879148Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.Type: GrantFiled: March 13, 2008Date of Patent: February 1, 2011Assignee: Apollo Diamond, Inc.Inventors: Robert C. Linares, Patrick J. Doering
-
Patent number: 7879147Abstract: Large area, uniformly low dislocation density single crystal III-V nitride material, e.g., gallium nitride having a large area of greater than 15 cm2, a thickness of at least 1 mm, an average dislocation density not exceeding 5E5 cm?2, and a dislocation density standard deviation ratio of less than 25%, and methods of forming same, are disclosed. Such material can be formed on a substrate by a process including (i) a first phase of growing the III-V nitride material on the substrate under pitted growth conditions, e.g., forming pits over at least 50% of the growth surface of the III-V nitride material, wherein the pit density on the growth surface is at least 102 pits/cm2 of the growth surface, and (ii) a second phase of growing the III-V nitride material under pit-filling conditions.Type: GrantFiled: September 17, 2007Date of Patent: February 1, 2011Assignee: Cree, Inc.Inventors: Xueping Xu, Robert P. Vaudo
-
Patent number: 7871469Abstract: A method of forming a planar waveguide structure, comprising forming a first graded layer on a substrate, wherein the first graded layer comprises a first and a second optical material, wherein the concentration of the first optical material increases with the height of the first graded layer; forming a second graded layer on the first graded layer, the second graded layer comprising the first and second optical materials wherein the concentration of the first optical material decreases with the height of the second graded layer. The method further including forming a uniform layer on the first graded layer, the uniform layer containing first and second optical materials wherein the first optical material concentration is constant.Type: GrantFiled: June 14, 2004Date of Patent: January 18, 2011Inventors: Dan Maydan, Arkadii V. Samoilov
-
Patent number: 7867335Abstract: GaN is grown by creating a Ga vapor from a powder, and using an inert purge gas from a source to transport the vapor to a growth site where the GaN growth takes place. In one embodiment, the inert gas is N2, and the powder source is GaN powder that is loaded into source chambers. The GaN powder is congruently evaporated into Ga and N2 vapors at temperatures between approximately 1000 and 1200° C. The formation of Ga liquid in the powder is suppressed by the purging of an inert gas through the powder. The poser may also be isolated from a nitride containing gas provided at the growth cite. In one embodiment, the inert gas is flowed through the powder.Type: GrantFiled: October 2, 2006Date of Patent: January 11, 2011Assignee: Cornell Research Foundation, Inc.Inventors: Michael G. Spencer, Phani Konkapaka, Huaqiang Wu, Yuri Makarov
-
Patent number: 7858536Abstract: A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.Type: GrantFiled: September 20, 2007Date of Patent: December 28, 2010Assignee: Kabushiki Kaisha ToshibaInventors: Kazuhiro Eguchi, Seiji Inumiya, Yoshitaka Tsunashima
-
Patent number: 7857907Abstract: The present invention relates to a method for forming a layered structure with silicon nanocrystals. In one embodiment, the method comprises the steps of: (i) forming a first conductive layer on a substrate, (ii) forming a silicon-rich dielectric layer on the first conductive layer, and (iii) laser-annealing at least the silicon-rich dielectric layer to induce silicon-rich aggregation to form a plurality of silicon nanocrystals in the silicon-rich dielectric layer. The silicon-rich dielectric layer is one of a silicon-rich oxide film having a refractive index in the range of about 1.4 to 2.3, or a silicon-rich nitride film having a refractive index in the range of about 1.7 to 2.3. The layered structure with silicon nanocrystals in a silicon-rich dielectric layer is usable in a solar cell, a photodetector, a touch panel, a non-volatile memory device as storage node, and a liquid crystal display.Type: GrantFiled: January 25, 2007Date of Patent: December 28, 2010Assignee: AU Optronics CorporationInventors: An-Thung Cho, Chih-Wei Chao, Chia-Tien Peng, Wan-Yi Liu, Ming-Wei Sun
-
Publication number: 20100288190Abstract: A kind of growth method of non-polarized-plane InN which is growing m-plane InN and In-rich m-plane InGaN on LiA1O2 (100) substrate by the metal organic chemical vapor deposition (MOCVD), and m-plane is one kind of non-polarized-plane, In-rich denotes that the component of In x is higher than 0.3 in InxGa1?xN. The invention synthetically grows m-plane InN and In-rich m-plane InGaN using LiA1O2 (100) as substrate which will be disposed and the buffer by MOCVD. And the non-polarized-plane InN would be produced through choosing appropriate substrate and the technique condition of growth as well as using the design of buffer by MOCVD.Type: ApplicationFiled: March 28, 2010Publication date: November 18, 2010Applicant: NANJING UNIVERSITYInventors: RONG ZHANG, ZILI XIE, BIN LIU, XIANGQIAN XIU, HONG ZHAO, XUEMEI HUA, PING HAN, DEYI FU, YI SHI, YOUDOU ZHENG
-
Patent number: 7824492Abstract: Process for producing silicon oxide containing thin films on a growth substrate by the ALCVD method. In the process, a vaporisable silicon compound is bonded to the growth substrate, and the bonded silicon compound is converted to silicon dioxide. The invention comprises using a silicon compound which contains at least one organic ligand and the bonded silicon compound is converted to silicon dioxide by contacting it with a vaporised, reactive oxygen source, in particular with ozone. The present invention provides a controlled process for growing controlling thin films containing SiO2, with sufficiently short reaction times.Type: GrantFiled: October 2, 2003Date of Patent: November 2, 2010Assignee: ASM International N.V.Inventors: Eva Tois, Suvi Haukka, Marko Tuominen
-
Publication number: 20100263588Abstract: Epitaxial growth of semiconductor materials is carried out by introducing two or more reaction gases along with their carrier gas into a reaction chamber via one or more concentric pipe inlets and a plurality of separately distributed injection ports with a gas distribution system. The reaction gas can be injected into the reaction chamber either continuously or in pulse mode, wherein reaction gases are mixed together or injected alternately into the reaction chamber. The semiconductor materials are deposited on the substrates which are located on the rotating heated susceptor within the reaction chamber.Type: ApplicationFiled: April 15, 2009Publication date: October 21, 2010Inventor: Gan Zhiyin
-
Publication number: 20100252808Abstract: The present invention relates to growth of III-V semiconductor nanowires (2) on a Si substrate (3). Controlled vertical nanowire growth is achieved by a step, to be taken prior of the growing of the nanowire, of providing group III or group V atoms to a (111) surface of the Si substrate to provide a group III or group V 5 surface termination (4). A nanostructured device comprising a plurality of aligned III-V semiconductor nanowires (2) grown on, and protruding from, a (111) surface of a Si substrate (3) in an ordered pattern in compliance with a predetermined device layout is also presented.Type: ApplicationFiled: October 27, 2008Publication date: October 7, 2010Inventors: Lars Samuelson, Jonas Ohlsson, Thomas Mårtensson, Patrik Svensson
-
Publication number: 20100248455Abstract: A manufacturing method of a group III nitride semiconductor comprising: preparing a substrate including a buffer layer; forming a first layer on the buffer layer from a group III nitride semiconductor by MOCVD while doping an anti-surfactant, wherein a thickness of the first layer is equal to or thinner than 2 ?m; forming a second layer on the first layer from a group III nitride semiconductor by MOCVD while doping at least one of surfactant and an anti-surfactant; and controlling a crystalline quality and a surface flatness of the second layer by adjusting an amount of the anti-surfactant and the surfactant doped during the formation of the second layer.Type: ApplicationFiled: February 26, 2010Publication date: September 30, 2010Applicant: TOYODA GOSEI CO., LTD.Inventor: Koji Okuno
-
Patent number: 7799132Abstract: A patterned layer is formed by removing nanoscale passivating particle from a first plurality of nanoscale structural particles or by adding nanoscale passivating particles to the first plurality of nanoscale structural particles. Each of a second plurality of nanoscale structural particles is deposited on each of corresponding ones of the first plurality of nanoscale structural particles that is not passivated by one of the plurality of nanoscale passivating particles.Type: GrantFiled: December 13, 2007Date of Patent: September 21, 2010Assignee: Zyvex Labs, LLCInventors: John N. Randall, Jingping Peng, Jun-Fu Liu, George D. Skidmore, Christof Baur, Richard E. Stallcup, Robert J. Folaron
-
Patent number: 7794543Abstract: A low dislocation density GaN single crystal substrate is made by forming a seed mask having parallel stripes regularly and periodically aligning on an undersubstrate, growing a GaN crystal on a facet-growth condition, forming repetitions of parallel facet hills and facet valleys rooted upon the mask stripes, maintaining the facet hills and facet valleys, producing voluminous defect accumulating regions (H) accompanying the valleys, yielding low dislocation single crystal regions (Z) following the facets, making C-plane growth regions (Y) following flat tops between the facets, gathering dislocations on the facets into the valleys by the action of the growing facets, reducing dislocations in the low dislocation single crystal regions (Z) and the C-plane growth regions (Y), and accumulating the dislocations in cores (S) or interfaces (K) of the voluminous defect accumulating regions (H).Type: GrantFiled: February 13, 2008Date of Patent: September 14, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Kensaku Motoki, Ryu Hirota, Takuji Okahisa, Seiji Nakahata
-
Patent number: 7776153Abstract: A method and apparatus for producing bulk single crystals of AlN having low dislocation densities of about 10,000 cm?2 or less includes a crystal growth enclosure with Al and N2 source material therein, capable of forming bulk crystals. The apparatus maintains the N2 partial pressure at greater than stoichiometric pressure relative to the Al within the crystal growth enclosure, while maintaining the total vapor pressure in the crystal growth enclosure at super-atmospheric pressure. At least one nucleation site is provided in the crystal growth enclosure, and provision is made for cooling the nucleation site relative to other locations in the crystal growth enclosure. The Al and N2 vapor is then deposited to grow single crystalline low dislocation density AlN at the nucleation site. High efficiency ultraviolet light emitting diodes and ultraviolet laser diodes are fabricated on low defect density AlN substrates, which are cut from the low dislocation density AlN crystals.Type: GrantFiled: November 3, 2005Date of Patent: August 17, 2010Assignee: Crystal IS, Inc.Inventors: Leo J. Schowalter, Glen A. Slack, J. Carlos Rojo
-
Patent number: 7776152Abstract: Apparatus and method for growing and observing the growth of epitaxial layers on a wafer. The apparatus includes: epitaxial growth apparatus; a source of light mounted to illuminate an entire surface of the wafer in the apparatus during growth of the epitaxial layer on the entire surface of the wafer; and apparatus for observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The method includes growing the epitaxial layer on a surface of the wafer and observing scattering of the light from the entire surface of the wafer during growth of the epitaxial layer on the entire surface of the wafer. The growing process is varied in accordance with the observation. With an epitaxial layer of gallium nitride (GaN) the entire surface of the wafer is observed for balls of gallium.Type: GrantFiled: November 1, 2006Date of Patent: August 17, 2010Assignee: Raytheon CompanyInventors: William E. Hoke, Theodore D. Kennedy
-
Patent number: 7771533Abstract: Process for producing silicon oxide containing thin films on a growth substrate by the ALCVD method. In the process, a vaporisable silicon compound is bonded to the growth substrate, and the bonded silicon compound is converted to silicon dioxide. The invention comprises using a silicon compound which contains at least one organic ligand and the bonded silicon compound is converted to silicon dioxide by contacting it with a vaporised, reactive oxygen source, in particular with ozone. The present invention provides a controlled process for growing controlling thin films containing SiO2 with sufficiently short reaction times.Type: GrantFiled: December 4, 2000Date of Patent: August 10, 2010Assignee: ASM International N.V.Inventors: Eva Tois, Suvi Haukka, Marko Tuominen
-
Patent number: 7771534Abstract: Process for producing silicon oxide containing thin films on a growth substrate by the ALCVD method. In the process, a vaporizable silicon compound is bonded to the growth substrate, and the bonded silicon compound is converted to silicon dioxide. The invention comprises using a silicon compound which contains at least one organic ligand and the bonded silicon compound is converted to silicon dioxide by contacting it with a vaporized, reactive oxygen source, in particular with ozone. The present invention provides a controlled process for growing controlling thin films containing SiO2, with sufficiently short reaction times.Type: GrantFiled: December 22, 2006Date of Patent: August 10, 2010Assignee: ASM International N.V.Inventors: Eva Tois, Suvi Haukka, Marko Tuominen
-
Publication number: 20100190322Abstract: A substrate for epitaxial growth, which is capable of improving a surface state of an epitaxial layer at microroughness level. In a substrate for epitaxial growth, when haze is defined as a value calculated by dividing intensity of scattered light obtained when light is incident from a predetermined light source onto a surface of a substrate, by intensity of the incident light from the light source, the haze is not more than 2 ppm all over an effectively used area of the substrate and an off-angle with respect to a plane direction is 0.05 to 0.10°.Type: ApplicationFiled: April 5, 2010Publication date: July 29, 2010Inventors: Kenji SUZUKI, Ryuichi HIRANO, Masashi NAKAMURA
-
Patent number: 7763317Abstract: Surface preparation of a compound semiconductor surface, such as indium antimonide (InSb), with a triflating agent, such as triflic anhydride or a trifluoroacetylating agent, such as trifluoroacetic anhydride is described. In one embodiment, the triflating or trifluoroacetylating passivates the compound semiconductor surface by terminating the surface with triflate trifluoroacetate groups. In a further embodiment, a triflating agent or trifluoroacetylating agent is employed to first convert a thin native oxide present on a compound semiconductor surface to a soluble species. In another embodiment, the passivated compound semiconductor surface is activated in an ALD chamber by reacting the triflate or trifluoroacetate protecting groups with a protic source, such as water (H2O). Metalorganic precursors are then introduced in the ALD chamber to form a good quality interfacial layer, such as aluminum oxide (Al2O3), on the compound semiconductor surface.Type: GrantFiled: March 30, 2007Date of Patent: July 27, 2010Assignee: Intel CorporationInventors: James M. Blackwell, Willy Rachmady, Gregory J. Kearns, Darryl J. Morrison
-
Patent number: 7754013Abstract: A deposition station allows atomic layer deposition (ALD) of films onto a substrate. The station comprises an upper and a lower substantially flat part between which a substrate is accommodated. The parts are positioned opposite each other and parallel to the substrate during processing. At least one of the parts is provided with a plurality of gas channels that allow at least two mutually reactive reactants to be discharged out of that part to the substrate. The discharge is configured to occur in a sequence of alternating, separated pulses for ALD. In addition, each part is preferably configured to be about 1 mm or less from the substrate to minimize the volume of the reaction chamber to increase the efficiency with which gases are purged from the chamber. Also, for each reactant, the upper and lower parts are preferably kept at a temperature outside of the window in which optimal ALD of that reactant occurs, thereby minimizing deposition of that reactant on deposition station surfaces.Type: GrantFiled: September 25, 2006Date of Patent: July 13, 2010Assignee: ASM International N.V.Inventor: Ernst H. A. Granneman
-
Patent number: 7749828Abstract: Affords high electron mobility transistors having a high-purity channel layer and a high-resistance buffer layer. A high electron mobility transistor 11 is provided with a supporting substrate 13 composed of gallium nitride, a buffer layer 15 composed of a first gallium nitride semiconductor, a channel layer 17 composed of a second gallium nitride semiconductor, a semiconductor layer 19 composed of a third gallium nitride semiconductor, and electrode structures (a gate electrode 21, a source electrode 23 and a drain electrode 25) for the transistor 11. The band gap of the third gallium nitride semiconductor is broader than that of the second gallium nitride semiconductor. The carbon concentration NC1 of the first gallium nitride semiconductor is 4×1017 cm?3 or more. The carbon concentration NC2 of the second gallium nitride semiconductor is less than 4×1016 cm?3.Type: GrantFiled: March 3, 2006Date of Patent: July 6, 2010Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shin Hashimoto, Makoto Kiyama, Takashi Sakurada, Tatsuya Tanabe, Kouhei Miura, Tomihito Miyazaki
-
Patent number: 7745315Abstract: A method for forming vertically oriented, crystallographically aligned nanowires (nanocolumns) using monolayer or submonolayer quantities of metal atoms to form uniformly sized metal islands that serve as catalysts for MOCVD growth of Group III nitride nanowires.Type: GrantFiled: October 3, 2007Date of Patent: June 29, 2010Assignee: Sandia CorporationInventors: George T. Wang, Qiming Li, J. Randall Creighton
-
Patent number: 7727332Abstract: In a process for forming a mask material on a III-N layer, wherein III denotes an element of the group III of the Periodic Table of Elements, selected from Al, Ga and In, a III-N layer having a surface is provided which comprises more than one facet. Mask material is selectively deposited only on one or multiple, but not on all facets. The deposition of mask material may be particularly carried out during epitaxial growth of a III-N layer under growth conditions, by which (i) growth of at least a further III-N layer selectively on a first type or a first group of facet(s) and (ii) a deposition of mask material selectively on a second type or a second group of facet(s) proceed simultaneously. By the process according to the invention, it is possible to produce free-standing thick III-N layers. Further, semiconductor devices or components having special structures and layers can be produced.Type: GrantFiled: December 21, 2006Date of Patent: June 1, 2010Assignee: Freiberger Compound Materials GmbHInventors: Frank Habel, Ferdinand Scholz, Barbara Neubert, Peter Brückner, Thomas Wunderer
-
Patent number: 7727331Abstract: A crystal foundation having dislocations is used to obtain a crystal film of low dislocation density, a crystal substrate, and a semiconductor device. One side of a growth substrate (11) is provided with a crystal layer (13) with a buffer layer (12) in between. The crystal layer (13) has spaces (13a), (13b) in an end of each threading dislocation D1 elongating from below. The threading dislocation D1 is separated from the upper layer by the spaces (13a), (13b), so that each threading dislocation D1 is blocked from propagating to the upper layer. When the displacement of the threading dislocation D1 expressed by Burgers vector is preserved to develop another dislocation, the spaces (13a), (13b) vary the direction of its displacement. As a result, the upper layer above the spaces (13a), (13b) turns crystalline with a low dislocation density.Type: GrantFiled: January 31, 2007Date of Patent: June 1, 2010Assignee: Sony CorporationInventors: Etsuo Morita, Yousuke Murakami, Goshi Biwa, Hiroyuki Okuyama, Masato Doi, Toyoharu Oohata
-
Patent number: 7727333Abstract: Hydride phase vapor epitaxy (HVPE) growth apparatus, methods and materials and structures grown thereby. A HVPE growth apparatus includes generation, accumulation and growth zones. A first reactive gas reacts with an indium source inside the generation zone to produce a first gas product having an indium-containing compound. The first gas product is transported to the accumulation zone where it cools and condenses into a source material having an indium-containing compound. The source material is collected in the accumulation zone and evaporated. Vapor or gas resulting from evaporation of the source material forms reacts with a second reactive gas in the growth zone for growth of ternary and quaternary materials including indium gallium nitride, indium aluminum nitride, and indium gallium aluminum nitride.Type: GrantFiled: March 27, 2007Date of Patent: June 1, 2010Assignee: Technologies and Devices International, Inc.Inventors: Alexander L. Syrkin, Vladimir Ivantsov, Alexander Usikov, Oleg Kovalenkov, Vladimir A. Dmitriev
-
Patent number: RE41503Abstract: The first object of the present invention is to provide a PDP with improved panel brightness which is achieved by improving the efficiency in conversion from discharge energy to visible rays. The second object of the present invention is to provide a PDP with improved panel life which is achieved by improving the protecting layer protecting the dielectrics glass layer. To achieve the first object, the present invention sets the amount of xenon in the discharge gas to the range of 10% by volume to less than 100% by volume, and sets the charging pressure for the discharge gas to the range of 500 to 760 Torr which is higher than conventional charging pressures. With such construction, the panel brightness increases. Also, to achieve the second object, the present invention has, on the surface of the dielectric glass layer, a protecting layer consisting of an alkaline earth oxide with (100)-face or (110)-face orientation.Type: GrantFiled: May 18, 2006Date of Patent: August 17, 2010Assignee: Panasonic CorporationInventors: Masaki Aoki, Hideo Torii, Eiji Fujii, Mitsuhiro Ohtani, Takashi Inami, Hiroyuki Kawamura, Hiroyoshi Tanaka, Ryuichi Murai, Yasuhisa Ishikura, Yutaka Nishimura, Katsuyoshi Yamashita, Yasuko Nishimura, Syunsuke Nishimura, Emi Kawahara