Of Amorphous Precursor Patents (Class 117/8)
  • Patent number: 10777573
    Abstract: A semiconductor device includes a semiconductor layer containing metal atoms, a charge storage layer provided on a surface of the semiconductor layer via a first insulating film, and an electrode layer provided on a surface of the charge storage layer via a second insulating film. The thickness of the first insulating film is 5 nm or more and 10 nm or less. The concentration of the metal atoms in the semiconductor layer is 5.0×1017 [EA/cm3] or higher and 1.3×1020 [EA/cm3] or lower.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: September 15, 2020
    Inventors: Yuta Saito, Shinji Mori, Keiichi Sawa, Kazuhisa Matsuda, Kazuhiro Matsuo, Hiroyuki Yamashita
  • Patent number: 10679889
    Abstract: A method for manufacturing a semiconductor structure includes at least following steps. A device layer is formed on a first semiconductor substrate. The device layer is separated from the first semiconductor substrate. A dielectric layer is formed on a second semiconductor substrate. The device layer is bonded onto the dielectric layer.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: June 9, 2020
    Inventors: Yu-Hsiang Tsai, Chung-Chuan Tseng, Chia-Wei Liu, Li-Hsin Chu
  • Patent number: 10553439
    Abstract: Semiconductor structures and methods of fabricating the same using multiple nanosecond pulsed laser anneals are provided. The method includes exposing a gate stack formed on a semiconducting material to multiple nanosecond laser pulses at a peak temperature below a melting point of the semiconducting material.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 4, 2020
    Inventors: Aritra Dasgupta, Oleg Gluschenkov
  • Patent number: 10446229
    Abstract: Phase change material can be set with a multistage set process. Set control logic can heat a phase change semiconductor material (PM) to a first temperature for a first period of time. The first temperature is configured to promote nucleation of a crystalline state of the PM. The control logic can increase the temperature to a second temperature for a second period of time. The second temperature is configured to promote crystal growth within the PM. The nucleation and growth of the crystal set the PM to the crystalline state. The multistage ramping up of the temperature can improve the efficiency of the set process relative to traditional approaches.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventors: Sanjay Rangan, Kiran Pangal, Nevil N Gajera, Lu Liu, Gayathri Rao Subbu
  • Patent number: 10431496
    Abstract: Disclosed herein is a device chip package manufacturing method including a cutting step of forming cut grooves having a depth reaching a finished thickness of device chips by cutting a device wafer from a top surface of the device wafer along streets by a cutting blade, a cut groove inclination state detecting step of detecting an inclination state of the cut grooves, a sealing resin layer forming step of forming a sealing resin layer coating the top surface and the cut grooves of the device wafer by supplying a sealing resin to the top surface of the device wafer, and a laser processing step of dividing the device wafer into individual chips and forming device chip packages by applying a laser beam having a wavelength absorbable by the sealing resin layer along the cut grooves of the device wafer held by a chuck table.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: October 1, 2019
    Inventor: Toshiyuki Tateishi
  • Patent number: 10301712
    Abstract: A process for obtaining a substrate provided with a coating, in which the coating includes a pattern with spatial modulation of at least one property of the coating, includes performing a heat treatment, using a laser radiation, of a continuous coating deposited on the substrate. The heat treatment is such that the substrate is irradiated with the laser radiation focused on the coating in the form of at least one laser line, keeping the coating continuous and without melting of the coating, and a relative displacement of the substrate and of the laser line focused on the coating is imposed in a direction transverse to the longitudinal direction of the laser line, while temporally modulating during this relative displacement the power of the laser line as a function of the speed of relative displacement and of the dimensions of the pattern in the direction of relative displacement.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: May 28, 2019
    Inventors: Nicolas Nadaud, Emmanuel Mimoun, Brice Dubost
  • Patent number: 10224453
    Abstract: A solar cell and a method for manufacturing the same are disclosed. The solar cell includes a semiconductor substrate containing impurities of a first conductive type, a tunnel layer positioned on the semiconductor substrate, an emitter region positioned on the tunnel layer and containing impurities of a second conductive type opposite the first conductive type, a dopant layer positioned on the emitter region and formed of a dielectric material containing impurities of the second conductive type, a first electrode connected to the semiconductor substrate, and a second electrode configured to pass through the dopant layer and connected to the emitter region.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 5, 2019
    Inventors: Kwangsun Ji, Jin-won Chung, Yujin Lee
  • Patent number: 10186584
    Abstract: A method of forming a p-n junction device comprises providing a base layer including a p-type diamond. A monolayer or few layer of a transition metal dichalcogenide (TMDC) is disposed on at least a portion of the base layer so as to form a heterojunction therebetween. The TMDC monolayer is an n-type layer such that the heterojunction between the intrinsic and p-type diamond base layer and the n-type TMDC monolayer is a p-n junction.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: January 22, 2019
    Assignee: UChicago Argonne, LLC
    Inventors: Anirudha V. Sumant, Kiran Kumar Kovi
  • Patent number: 10115854
    Abstract: The present disclosure provides a method of manufacturing a semiconductor device. Furthermore the present disclosure provides a photovoltaic device and a light emitting diode manufactured in accordance with the method. The method comprises the steps of forming a germanium layer using deposition techniques compatible with high-volume, low-cost manufacturing, such as magnetron sputtering, and exposing the germanium layer to laser light to reduce the amount of defects in the germanium layer. After the method is performed the germanium layer can be used as a virtual germanium substrate for the growth of III-V materials.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 30, 2018
    Assignee: NewSouth Innovations Pty Limited
    Inventors: Xiaojing Hao, Martin Andrew Green, Ziheng Liu, Wei Li, Anita Wing Yi Ho-Baillie
  • Patent number: 10002780
    Abstract: A method of manufacturing a semiconductor structure includes providing a substrate, disposing a first semiconductive material over the substrate at a first temperature, disposing a second semiconductive material over the first semiconductive material at a second temperature, and disposing a third semiconductive material over the second semiconductive material at a third temperature, wherein a first interval between the first temperature and the second temperature is substantially same as a second interval between the second temperature and the third temperature.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: June 19, 2018
    Inventors: Su-Horng Lin, Victor Y. Lu, Tsung-Hsi Yang
  • Patent number: 9947897
    Abstract: A substrate including a light-emitting element and a terminal for connection to the outside is prepared. The light-emitting element includes a light-emitting layer, an anode, and a cathode. The anode and the cathode interpose the light-emitting layer therebetween. A sealing layer is formed on the substrate so as to cover the light-emitting element and the terminal. An amorphous carbon film is formed on the sealing layer so as to cover a region above the light-emitting element and avoid a region above the terminal. The sealing layer is dry-etched so as to expose the terminal from the sealing layer using the amorphous carbon film as a mask. The amorphous carbon film is removed.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: April 17, 2018
    Assignee: Japan Display Inc.
    Inventor: Akinori Kamiya
  • Patent number: 9859121
    Abstract: Semiconductor structures and methods of fabricating the same using multiple nanosecond pulsed laser anneals are provided. The method includes exposing a gate stack formed on a semiconducting material to multiple nanosecond laser pulses at a peak temperature below a melting point of the semiconducting material.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: January 2, 2018
    Inventors: Aritra Dasgupta, Oleg Gluschenkov
  • Patent number: 9839976
    Abstract: A thermal processing apparatus and method in which a first laser source, for example, a CO2 emitting at 10.6 ?m is focused onto a silicon wafer as a line beam and a second laser source, for example, a GaAs laser bar emitting at 808 nm is focused onto the wafer as a larger beam surrounding the line beam. The two beams are scanned in synchronism in the direction of the narrow dimension of the line beam to create a narrow heating pulse from the line beam when activated by the larger beam. The energy of GaAs radiation is greater than the silicon bandgap energy and creates free carriers. The energy of the CO2 radiation is less than the silicon bandgap energy so silicon is otherwise transparent to it, but the long wavelength radiation is absorbed by the free carriers.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: December 12, 2017
    Inventors: Dean Jennings, Haifan Liang, Mark Yam, Vijay Parihar, Abhilash J. Mayur, Aaron Muir Hunter, Bruce E. Adams, Joseph Michael Ranish
  • Patent number: 9777393
    Abstract: Process for fabricating a thin single-crystalline layer n, including steps of: a) providing a support substrate n, b) placing a seed sample n, c) depositing a thin layer n so as to form an initial interface region n including a proportion of seed sample n and a proportion of thin layer n, the proportion of seed sample n decreasing from the first peripheral part n towards the second peripheral part n, e) providing an energy input to the initial interface region n contiguous to the first peripheral part n so as to liquefy a portion n of the thin layer and form a solid/liquid interface region n, and f) gradually moving the energy input away from the seed sample n so as to solidify the portion n so as to gradually move the solid/liquid interface region n.
    Type: Grant
    Filed: July 15, 2013
    Date of Patent: October 3, 2017
    Inventor: Lamine Benaissa
  • Patent number: 9768019
    Abstract: A laser crystallization method includes forming a plurality of first protrusions and depressions on a surface of an amorphous silicon layer, wherein a first protrusion and an adjacent first depression of the plurality of first protrusions and depressions, together, have a first pitch, and irradiating the amorphous silicon layer with a laser beam to form a polycrystalline silicon layer.
    Type: Grant
    Filed: May 19, 2016
    Date of Patent: September 19, 2017
    Inventors: Joon-Hwa Bae, Byoung Kwon Choo, Jeong Kyun Na, Byoung Ho Cheong, Joo Woan Cho
  • Patent number: 9741925
    Abstract: Methods for doping an active Hall effect region of a Hall effect device in a semiconductor substrate, and Hall effect devices having a doped active Hall effect region are provided. A method includes forming a first doping profile of a first doping type in a first depth region of the active Hall effect region by means of a first implantation with a first implantation energy level, forming a second doping profile of the first doping type in a second depth region of the active Hall effect region by means of a second implantation with a second implantation energy level, and forming an overall doping profile of the active Hall effect region by annealing the semiconductor substrate with the active Hall effect region having the first and the second doping profile.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: August 22, 2017
    Inventors: Markus Eckinger, Stefan Kolb
  • Patent number: 9647117
    Abstract: A method comprises forming a fin structure over a substrate, wherein the fin structure comprises a channel connected between a drain region and a source region, depositing a semiconductor layer in an amorphous state over the drain region and the source region at a first temperature and performing a solid phase epitaxial regrowth process on the semiconductor layer at a second temperature, wherein the second temperature is higher than the first temperature.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: May 9, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jean-Pierre Colinge
  • Patent number: 9558973
    Abstract: Laser annealing systems and methods for annealing a semiconductor wafer with ultra-short dwell times are disclosed. The laser annealing systems can include one or two laser beams that at least partially overlap. One of the laser beams is a pre-heat laser beam and the other laser beam is the annealing laser beam. The annealing laser beam scans sufficiently fast so that the dwell time is in the range from about 1 ?s to about 100 ?s. These ultra-short dwell times are useful for annealing product wafers formed from thin device wafers because they prevent the device side of the device wafer from being damaged by heating during the annealing process. Embodiments of single-laser-beam annealing systems and methods are also disclosed.
    Type: Grant
    Filed: September 18, 2014
    Date of Patent: January 31, 2017
    Assignee: Ultratech, Inc.
    Inventors: Andrew M. Hawryluk, Serguel Anikitchev
  • Patent number: 9540743
    Abstract: There is provided a method of crystallizing amorphous silicones, which includes: forming a stacked structure of a second amorphous silicon film followed by a first amorphous silicon film on an underlay film, the second amorphous silicon film having a faster crystal growth rate than the first amorphous silicon film; and performing a crystallization treatment on the stacked structure to crystallize silicones contained in at least the second amorphous silicon film.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: January 10, 2017
    Inventors: Kazuya Takahashi, Yoshikazu Furusawa, Mitsuhiro Okada, Hiromasa Yonekura
  • Patent number: 9499901
    Abstract: Methods for depositing a layer on a substrate are provided herein. In some embodiments, a method of depositing a metal-containing layer on a substrate in a physical vapor deposition (PVD) chamber may include applying RF power at a VHF frequency to a target comprising a metal disposed in the PVD chamber above the substrate to form a plasma from a plasma-forming gas; optionally applying DC power to the target; sputtering metal atoms from the target using the plasma while maintaining a first pressure in the PVD chamber sufficient to ionize a predominant portion of the sputtered metal atoms; and controlling the potential on the substrate to be the same polarity as the ionized metal atoms to deposit a metal-containing layer on the substrate.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: November 22, 2016
    Inventors: Yong Cao, Xianmin Tang, Adolph Miller Allen, Tza-Jing Gung
  • Patent number: 9425073
    Abstract: A depression filling method for filling a depression of a workpiece including a semiconductor substrate and an insulating film formed on the semiconductor substrate is provided. The depression penetrating the insulating film is configured so as to extend to the semiconductor substrate. The method includes: forming a thin film of a semiconductor material along a wall surface that defines the depression; annealing the workpiece to cause the semiconductor material of the thin film to move toward a bottom of the depression and to form an epitaxial region corresponding to crystals of the semiconductor substrate; and etching the thin film.
    Type: Grant
    Filed: August 21, 2014
    Date of Patent: August 23, 2016
    Inventors: Satoshi Onodera, Daisuke Suzuki, Akinobu Kakimoto
  • Patent number: 9331078
    Abstract: According to one embodiment, provided is a thin film transistor device with further improved area efficiency. First contact regions of a first semiconductor layer portion are formed with the first channel region therebetween in a predetermined direction and doped with an N-type impurity, one of the first contact regions electrically connected with a shared electrode, while the other electrically connected with a first electrode. Second contact regions of a second semiconductor layer portion are formed with the second channel region therebetween in the predetermined direction and doped with a P-type impurity, one of the second contact regions electrically connected with the shared electrode, while the other electrically connected with a second electrode. The first and second contact regions are partially disposed alternately and adjacently in a direction intersecting with the predetermined direction.
    Type: Grant
    Filed: June 12, 2015
    Date of Patent: May 3, 2016
    Assignee: Japan Display Inc.
    Inventor: Takanori Tsunashima
  • Patent number: 9245967
    Abstract: A device formed from a method of fabricating a fine metal silicide layer having a uniform thickness regardless of substrate doping. A planar vacancy is created by the separation of an amorphousized surface layer of a silicon substrate from an insulating layer, a metal source enters the vacancy through a contact hole through the insulating later connecting with the vacancy, and a heat treatment converts the metal in the vacancy into metal silicide. The separation is induced by converting the amorphous silicon into crystalline silicon.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: January 26, 2016
    Inventor: Jong-Ki Jung
  • Patent number: 9099386
    Abstract: According to one embodiment, a laser annealing method includes: detecting an intensity distribution of a laser light formed as a line beam by a line beam optical system; dividing width in short axis direction of the line beam in the detected intensity distribution by number of times of the irradiation per one site and partitioning the width; and calculating increment of crystal grain size of a non-crystalline thin film for energy density corresponding to wave height of the partitioned intensity distribution, and summing the increments by number of times of pulse irradiation, when energy density of the laser light is larger than a threshold, the crystal grain size of the non-crystalline thin film taking a downward turn at the threshold, the increment summed before the energy density exceeds the threshold being set to zero.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: August 4, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tsutomu Kakuno, Ryuichi Togawa, Hiroshi Ito
  • Patent number: 9039832
    Abstract: A high pressure high temperature (HPHT) method for synthesizing single crystal diamond, wherein a single crystal diamond seed having an aspect ratio of at least (1) and a growth surface substantially parallel to a {110} crystallographic plane is utilized is described. The growth is effected at a temperature in the range from 1280° C. to 1390° C.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: May 26, 2015
    Assignee: Element Six Technologies Limited
    Inventors: Raymond Anthony Spits, Carlton Nigel Dodge
  • Patent number: 9034102
    Abstract: A method of fabricating a hybrid orientation substrate is described. A silicon substrate with a first orientation having a silicon layer with a second orientation directly thereon is provided, and then a stress layer is formed on the silicon layer. A trench is formed between a first portion and a second portion of the silicon layer through the stress layer and into the substrate. The first portion of the silicon layer is amorphized. A SPE process is performed to recrystallize the amorphized first portion of the silicon layer to be a recrystallized layer with the first orientation. An annealing process is performed at a temperature lower than 1200° C. to convert a surface layer of the second portion of the silicon layer to a strained layer. The trench is filled with an insulating material after the SPE process or the annealing process, and the stress layer is removed.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: May 19, 2015
    Inventors: Yao-Tsung Huang, Chien-Ting Lin, Che-Hua Hsu, Guang-Hwa Ma
  • Publication number: 20150104637
    Abstract: A method for producing a ferroelectric thin film comprising: coating a composition for forming a ferroelectric thin film on a base electrode of a substrate having a substrate body and the base electrode that has crystal daces oriented in the (111) direction, calcining the coated composition, and subsequently performing firing the coated composition to crystallize the coated composition, and thereby forming a ferroelectric thin film on the base electrode, wherein the method includes formation of an orientation controlling layer by coating the composition on the base electrode, calcining the coated composition, and firing the coated composition, where an amount of the composition coated on the base electrode is controlled such that a thickness of the orientation controlling layer after crystallization is in a range of 5 nm to 30 nm, and thereby controlling the preferential crystal orientation of the orientation controlling layer to be in the (110) plane.
    Type: Application
    Filed: December 19, 2014
    Publication date: April 16, 2015
    Inventors: Toshiaki Watanabe, Hideaki Sakurai, Nobuyuki Soyama, Toshihiro Doi
  • Publication number: 20150059640
    Abstract: A method for depositing a column III-V material over a selected portion of a substrate through a window formed in a dielectric layer disposed over the selected portion of the substrate. The method includes forming a single crystal layer or polycrystalline layer over a field region of the dielectric layer adjacent to the window; and, growing, by MOCVD, column III-V material over the single crystal layer or polycrystalline layer and through the window over the selected portion of the substrate.
    Type: Application
    Filed: August 27, 2013
    Publication date: March 5, 2015
    Applicant: Raytheon Company
    Inventors: Jeffrey R. LaRoche, William E. Hoke, Thomas E. Kazior
  • Patent number: 8956453
    Abstract: The present invention provides a method for providing a crystalline germanium layer on a crystalline base substrate having a crystalline surface. The method comprises cleaning the base substrate for removing contaminants and/or native oxides from the surface, providing an amorphous germanium layer on the surface of the base substrate while exposing to the base substrate to a hydrogen source such as e.g. a hydrogen plasma, a H2 flux or hydrogen originating from dissociation of GeH4 and/or to a non-reactive gas source such as N2, He, Ne, Ar, Kr, Xe, Rn or mixtures thereof, and crystallizing the amorphous germanium layer by annealing the base substrate so as to provide a crystalline germanium layer.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: February 17, 2015
    Assignees: IMEC, Vrije Universiteit Brussel
    Inventors: Ruben Lieten, Stefan Degroote
  • Patent number: 8945301
    Abstract: A method for producing a diamond material by contacting a fluorinated precursor with a hydrocarbon in a reactor and forming a combination in the absence of a metal catalyst; increasing the pressure of the reactor to a first pressure; heating the combination under pressure to form a material precursor; cooling the material precursor; and forming a diamond material.
    Type: Grant
    Filed: August 5, 2011
    Date of Patent: February 3, 2015
    Assignee: University of Houston System
    Inventors: Valery N. Khabashesku, Valery A. Davydov, Alexandra V. Rakhmanina
  • Patent number: 8894765
    Abstract: A PIN-PMN-PT ferroelectric single crystal and a method of manufacture are disclosed. The PIN-PMN-PT ferroelectric single crystal is oriented and polarized along a single crystallographic direction. The PIN-PMN-PT ferroelectric single crystal ferroelectric has increased remnant polarization.
    Type: Grant
    Filed: November 12, 2010
    Date of Patent: November 25, 2014
    Assignee: TRS Technologies, Inc.
    Inventors: Wesley S. Hackenberger, Edward F. Alberta
  • Publication number: 20140283734
    Abstract: The present disclosure relates to a heat treatment method of performing a single crystallization of amorphous silicon formed on a substrate to be processed by irradiating the substrate with a microwave. The heat treatment method includes: irradiating the substrate with a microwave to increase a temperature of the substrate to a first temperature such that the amorphous silicon formed on the substrate becomes a single crystal at an interface between the substrate and the amorphous silicon and a nucleation does not occur in a region except the interface; irradiating the substrate with a microwave to heat the substrate at the first temperature for a predetermined period; irradiating the substrate with the microwave to increase the first temperature to a second temperature, which is higher than the first temperature; and irradiating the substrate with the microwave to heat the substrate at the second temperature.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 25, 2014
    Inventors: Taichi MONDEN, Junichi KITAGAWA, Seokhyoung HONG, Yoshiro KABE
  • Patent number: 8840720
    Abstract: An apparatus for manufacturing a polycrystalline silicon thin film, including a crystallization container filled with silicon oil, crystallization electrodes spaced apart from the crystallization container, and a conductive plate positioned between the crystallization electrodes and connected with the crystallization electrodes. Because an insulating layer between the amorphous silicon thin film and the conductive plate is formed by using silicon oil filled within the crystallization container, Joule-heating induced crystallization (JIC) can be performed through a simpler manufacturing process.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: September 23, 2014
    Assignee: Samsung Display Co., Ltd.
    Inventor: Cheol-Su Kim
  • Patent number: 8734583
    Abstract: One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment, a fin of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy (SPE) process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The fin has a cross-sectional thickness in at least one direction less than a minimum feature size. The transistor body is formed in the crystallized semiconductor pillar between a first source/drain region and a second source/drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.
    Type: Grant
    Filed: April 4, 2006
    Date of Patent: May 27, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Leonard Forbes
  • Patent number: 8715412
    Abstract: Systems for processing thin films having variable thickness are provided. A crystalline film includes a first crystalline region having a first film thickness and a first crystalline grain structure; and a second crystalline region having a second film thickness and a second crystalline grain structure. The first film thickness is greater than the second film thickness and the first and second film thicknesses are selected to provide a crystalline region having the degree and orientation of crystallization that is desired for a device component.
    Type: Grant
    Filed: January 14, 2013
    Date of Patent: May 6, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 8696808
    Abstract: Each region, which should be left on a substrate after patterning, of a semiconductor film is grasped in accordance with a mask. Then, each region to be scanned with laser light is determined so that at least the region to be obtained through the patterning is crystallized, and a beam spot is made to hit the region to be scanned, thereby partially crystallizing the semiconductor film. Each portion with low output energy of the beam spot is shielded by a slit. In the present invention, the laser light is not scanned and irradiated onto the entire surface of the semiconductor film but is scanned such that at least each indispensable portion is crystallized to a minimum. With the construction described above, it becomes possible to save time taken to irradiate the laser light onto each portion to be removed through the patterning after the crystallization of the semiconductor film.
    Type: Grant
    Filed: September 5, 2006
    Date of Patent: April 15, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hisashi Ohtani, Masaaki Hiroki, Koichiro Tanaka, Aiko Shiga, Satoshi Murakami, Mai Akiba
  • Publication number: 20140069323
    Abstract: A method for forming a metal chalcogenide includes: (a) providing a preliminary precursor solution including a first precursor for an elemental metal of Ag, Au, Al, In, Ga, or Tl, a second precursor for a chalcogen element of Se, S, or Te, and a liquid solvent; (b) heating the preliminary precursor solution under an inert ambient, such that the first precursor reacts with the second precursor to obtain a metal chalcogenide precursor that is in an amorphous phase; (c) removing the liquid solvent from the metal chalcogenide precursor; and (d) heating the metal chalcogenide precursor under a hydrogen-containing gas pressure so as to convert the metal chalcogenide precursor into a single crystal phase metal chalcogenide.
    Type: Application
    Filed: September 12, 2012
    Publication date: March 13, 2014
    Applicant: Precision Machinery Research & Development Center
    Inventors: Yen-Chau WANG, Hsiao-Chun CHU, Wang-Lin LIU
  • Patent number: 8663387
    Abstract: A method and system for processing at least one portion of a thin film sample on a substrate, with such portion of the film sample having a first boundary and a second boundary. One or more first areas of the film sample are successively irradiated by first beamlets of an irradiation beam pulse so that the first areas are melted throughout their thickness and allowed to re-solidify and crystallize thereby having grains grown therein. Thereafter, one or more second areas of the film sample are irradiated by second beamlets so that the second areas are melted throughout their thickness. At least two of the second areas partially overlap a particular area of the re-solidified and crystallized first areas such that the grains provided in the particular area grow into each of the at least two second areas upon re-solidification thereof.
    Type: Grant
    Filed: March 9, 2006
    Date of Patent: March 4, 2014
    Assignee: The Trustees of Columbia University in the City of New York
    Inventor: James S. Im
  • Patent number: 8659023
    Abstract: A monocrystalline layer having a first lattice constant on a monocrystalline substrate having a second lattice constant at least in a near-surface region, wherein the second lattice constant is different from the first lattice constant. Lattice matching atoms are implanted into the near-surface region. The near-surface region is momentarily melted. A layer is epitaxially deposited on the near-surface region that has solidified in monocrystalline fashion.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: February 25, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Hans-Joachim Schulze
  • Patent number: 8617313
    Abstract: A system for preparing a semiconductor film, the system including: a laser source; optics to form a line beam, a stage to support a sample capable of translation; memory for storing a set of instructions, the instructions including irradiating a first region of the film with a first laser pulse to form a first molten zone, said first molten zone having a maximum width (Wmax) and a minimum width (Wmin), wherein the first molten zone crystallizes to form laterally grown crystals; laterally moving the film in the direction of lateral growth a distance greater than about one-half Wmax and less than Wmin; and irradiating a second region of the film with a second laser pulse to form a second molten zone, wherein the second molten zone crystallizes to form laterally grown crystals that are elongations of the crystals in the first region, wherein laser optics provide Wmax less than 2×Wmin.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: December 31, 2013
    Assignee: The Trustees of Columbia University in the City of New York
    Inventors: James S. Im, Paul C. Van Der Wilt
  • Patent number: 8613901
    Abstract: A titanium oxide nano tube material is configured so that crystal grains of a nano tube has a crystal structure oriented with the [001] direction of a tetragonal crystal system as a preferred direction. FWHM (Full Width at Half Maximum) of a rocking curve with respect to the (004) plane peak is 11.1 degrees to 20.3 degrees. The titanium oxide nano tube material has excellent photoelectric characteristics since the crystal grains of the nano tube are oriented with the (004) plane or the [001] direction of a tetragonal crystal system as a preferred direction.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: December 24, 2013
    Assignee: SNU R&DB Foundation
    Inventors: Sang-Wook Lee, Ik-Jae Park, Dong-Hoe Kim, Kug-Sun Hong, Gil-Sang Han, Hyun-Suk Jung
  • Publication number: 20130323534
    Abstract: There is provided a manufacturing method of a ferroelectric crystal film in which an orientation of a seed crystal film is transferred preferably and a film deposition rate is suitable for volume production. A seed crystal film is formed on a substrate in epitaxial growth by a sputtering method, an amorphous film including ferroelectric material is formed over the seed crystal film by a spin-coat coating method, the seed crystal film and the amorphous film are heated in an oxygen atmosphere for oxidation and crystallization of the amorphous film, and thereby a ferroelectric coated-and-sintered crystal film is formed.
    Type: Application
    Filed: November 30, 2012
    Publication date: December 5, 2013
    Applicants: SAE MAGNETICS (H.K.) LTD., YOUTEC CO., LTD.
    Inventors: Takeshi KIJIMA, Yuuji HONDA, Daisuke IITSUKA, Kenjirou HATA
  • Patent number: 8586488
    Abstract: A computer program product and system for configuring J electromagnetic radiation sources (J?2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1?S1|, |W2?S2|, |WI?SI| is about minimized with respect to Pj (j=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).
    Type: Grant
    Filed: August 23, 2010
    Date of Patent: November 19, 2013
    Assignee: International Business Machines Corporation
    Inventors: Brent Alan Anderson, Edward Joseph Nowak
  • Patent number: 8580031
    Abstract: A method of producing a three-dimensional photonic crystal by laminating a layer having a periodic structure, the method including the steps of forming a first structure and a second structure each including the layer having the periodic structure; and bonding a first bonding layer of the first structure and a second bonding layer of the second structure. The first bonding layer is one layer obtained by dividing a layer constituting the three-dimensional photonic crystal at a cross section perpendicular to a lamination direction, and the second bonding layer is the other layer obtained by dividing the layer constituting the three-dimensional photonic crystal at the cross section perpendicular to the lamination direction.
    Type: Grant
    Filed: April 6, 2010
    Date of Patent: November 12, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Aihiko Numata, Hikaru Hoshi, Kenji Tamamori
  • Publication number: 20130186455
    Abstract: A method for forming single crystal or large-crystal-grain thin-film layers deposits a thin-film amorphous, nanocrystalline, microcrystalline, or polycrystalline layer, and laser-heats a seed spot having size on the order of a critical nucleation size of the thin-film layer. The single-crystal seed spot is extended into a single-crystal seed line by laser-heating one or more crystallization zones adjacent to the seed spot and drawing the zone across the thin-film layer. The single-crystal seed line is extended across the thin-film material layer into a single-crystal layer by laser-heating an adjacent linear crystallization zone and drawing the crystallization zone across the thin-film layer. Photovoltaic cells may be formed in or on the single-crystal layer. Tandem photovoltaic devices may be formed using one or several iterations of the method. The method may also be used to form single-crystal semiconductor thin-film transistors, such as for display devices, or to form single-crystal superconductor layers.
    Type: Application
    Filed: February 21, 2012
    Publication date: July 25, 2013
    Inventors: Jifeng Liu, Xiaoxin Wang
  • Patent number: 8475588
    Abstract: A wafer structure and epitaxial growth method for growing the same. The method may include forming a mask layer having nano-sized areas on a wafer, forming a porous layer having nano-sized pores on a surface of the wafer by etching the mask layer and a surface of the wafer, and forming an epitaxial material layer on the porous layer using an epitaxial growth process.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: July 2, 2013
    Assignee: Samsung Corning Precision Materials Co., Ltd.
    Inventor: Sung-Soo Park
  • Patent number: 8470089
    Abstract: The invention relates to a process for manufacturing a single crystal comprising a rare-earth halide, having improved machining or cleavage behavior, comprising heat treatment in a furnace, the atmosphere of which is brought, for at least 1 hour, to between 0.70 times Tm and 0.995 times Tm of a single crystal comprising a rare-earth halide, Tm representing the melting point of said single crystal, the temperature gradient at any point in the atmosphere of the furnace being less than 15 K/cm for said heat treatment. After carrying out the treatment according to the invention, the single crystals may be machined or cleaved without uncontrolled fracture. The single crystals may be used in a medical imaging device, especially a positron emission tomography system or a gamma camera or a CT scanner, for crude oil exploration, for detection and identification of fissile or radioactive materials, for nuclear and high-energy physics, for astrophysics or for industrial control.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: June 25, 2013
    Assignee: Saint-Gobain Cristaux et Detecteurs
    Inventors: Dominique Richaud, Alain Iltis, Vladimir Ouspenski
  • Patent number: 8449671
    Abstract: A method of fabricating an SiC single crystal includes (a) physical vapor transport (PVT) growing a SiC single crystal on a seed crystal in the presence of a temperature gradient, wherein an early-to-grow portion of the SiC single crystal is at a lower temperature than a later-to-grow portion of the SiC single crystal. Once grown, the SiC single crystal is annealed in the presence of a reverse temperature gradient, wherein the later-to-grow portion of the SiC single crystal is at a lower temperature than the early-to-grow portion of the SiC single crystal.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: May 28, 2013
    Assignee: II-VI Incorporated
    Inventors: Ping Wu, Ilya Zwieback, Avinesh K. Gupta, Edward Semenas
  • Publication number: 20130065065
    Abstract: A thin film which comprises an organic metal salt or an an alkoxide salt or an amorphous thin film is formed on a substrate, wherein each of the thin films enables the formation of a Dion-Jacobson perovskite-type metal oxide represented by the composition formula A(Bn?1MnO3n+1) (wherein n is a natural number of 2 or greater; A represents one or more monovalent cations selected from Na, K, Rb and Cs; B comprises one or more components selected from a trivalent rare earth ion, Bi, a divalent alkaline earth metal ion and a monovalent alkali metal ion; and M comprises one or more of Nb and Ta; wherein a solid solution may be formed with Ti and Zr) on a non-oriented substrate. The resulting product is maintained at the temperature between room temperature and 600° C.; and crystallization is achieved while irradiating the amorphous thin film or the thin film comprising the organic metal salt or the alkoxide salt on the substrate with ultraviolet light such as ultraviolet laser.
    Type: Application
    Filed: April 12, 2011
    Publication date: March 14, 2013
    Inventors: Tomohiko Nakajima, Tetsuo Tsuchiya, Takaaki Manabe
  • Patent number: 8367550
    Abstract: A conductive layer may be fabricated on a semiconductor substrate by loading a silicon substrate in to a chamber whose inside temperature is at a loading temperature in the range of approximately 250° C. to approximately 300° C., increasing the inside temperature of the chamber from the loading temperature to a process temperature, and sequentially stacking a single crystalline silicon layer and a polycrystalline silicon layer over the silicon substrate by supplying a silicon source gas and an impurity source gas in to the chamber, where the chamber may be, for example, a CVD chamber or a LPCVD chamber.
    Type: Grant
    Filed: December 27, 2010
    Date of Patent: February 5, 2013
    Assignee: SK Hynix Inc.
    Inventors: Jong Bum Park, Chun Ho Kang, Young Seung Kim