Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/89)
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Patent number: 8394197Abstract: Enhanced corrosion resistance is achieved in a coating by using a germanium-containing precursor and hollow cathode techniques to form a first layer directly on the surface of a workpiece, prior to forming an outer layer, such as a layer of diamond-like carbon (DLC). The use of a germanium or germanium-carbide precursor reduces film stress and enables an increase in the thickness of the subsequently formed DLC. Germanium incorporation also reduces the porosity of the layer. In one embodiment, a cap layer containing germanium is added after the DLC in order to further reduce the susceptibility of the coating to chemical penetration from the top.Type: GrantFiled: July 11, 2008Date of Patent: March 12, 2013Assignee: Sub-One Technology, Inc.Inventors: Andrew W. Tudhope, Thomas B. Casserly, Karthik Boinapally, Deepak Upadhyaya, William J. Boardman
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Patent number: 8394196Abstract: Methods for formation epitaxial layers containing silicon and carbon doped with phosphorus are disclosed. The pressure is maintained equal to or above 100 torr during deposition. The methods result in the formation of a film including substitutional carbon. Specific embodiments pertain to the formation and treatment of epitaxial layers in semiconductor devices, for example, Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices.Type: GrantFiled: December 12, 2006Date of Patent: March 12, 2013Assignee: Applied Materials, Inc.Inventor: Yihwan Kim
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Publication number: 20130049014Abstract: Provided is an epitaxial silicon carbide single-crystal substrate in which a silicon carbide epitaxial film having excellent in-plane uniformity of doping density is disposed on a silicon carbide single-crystal substrate having an off angle that is between 1° to 6°. The epitaxial film is grown by repeating a dope layer that is 0.5 ?m or less and a non-dope layer that is 0.1 ?m or less. The dope layer is formed with the ratio of the number of carbon atoms to the number of silicon atoms (C/Si ratio) in a material gas being 1.5 to 2.0, and the non-dope layer is formed with the C/Si ratio being 0.5 or more but less than 1.5. The resulting epitaxial silicon carbide single-crystal substrate comprises a high-quality silicon carbide epitaxial film, which has excellent in-plane uniformity of doping density, on a silicon carbide single-crystal substrate having a small off angle.Type: ApplicationFiled: May 10, 2011Publication date: February 28, 2013Applicant: NIPPON STEEL CORPORATIONInventors: Takashi Aigo, Hiroshi Tsuge, Taizo Hoshino, Tatsuo Fujimoto, Masakazu Katsuno, Masashi Nakabayashi, Hirokatsu Yashiro
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Patent number: 8377205Abstract: The present disclosure relates to an apparatus for producing silicon nanocrystals, which can minimize plasma diffusion by finely adjusting a plasma region created by an ICP coil. The apparatus includes a reactor having an ICP coil wound around an outer wall thereof and a tube inserted into the reactor, wherein a primary gas for forming silicon nanocrystals and a secondary gas for surface reaction of the silicon nanocrystals are separately supplied to the reactor through an inner side and an outer side of the tube, respectively.Type: GrantFiled: October 26, 2009Date of Patent: February 19, 2013Assignee: Korea Institute of Energy ResearchInventors: Bo-Yun Jang, Chang-Hyun Ko, Jeong-Chul Lee, Joon-Soo Kim, Joo-Seok Park
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Publication number: 20130040103Abstract: To provide a method of manufacturing a single crystal 3C-SiC substrate that can dramatically reduce surface defects generated in a processing of epitaxial growth and can secure a quality as a semiconductor device while simplifying a post process. The method of manufacturing a single crystal 3C-SiC substrate where a single crystal 3C-SiC layer is formed on a base substrate by epitaxial growth is provided. A first growing stage of forming the single crystal 3C-SiC layer to have a surface state configured with a surface with high flatness and surface pits scattering in the surface is performed. A second growing stage of further epitaxially growing the single crystal 3C-SiC layer obtained in the first growing stage so as to fill the surface pits is performed.Type: ApplicationFiled: March 14, 2011Publication date: February 14, 2013Inventors: Hidetoshi Asamura, Keisuke Kawamura, Satoshi Obara
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Patent number: 8372197Abstract: A control system and method for controlling temperatures while performing a MBE deposition process, wherein the control system comprises a MBE growth structure; a heater adapted to provide heat for the MBE deposition process on the MBE growth structure; and a control computer adapted to receive a plurality of dynamic feedback control signals derived from the MBE growth structure; switch among a plurality of control modes corresponding with the plurality of dynamic feedback control signals; and send an output power signal to the heater to control the heating for the MBE deposition process based on a combination of the plurality of control modes. In one embodiment, the plurality of dynamic feedback control signals comprises thermocouple signals and pyrometer signals.Type: GrantFiled: August 29, 2011Date of Patent: February 12, 2013Assignee: The United States of America as represented by the Secretary of the ArmyInventor: Stefan P. Svensson
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Patent number: 8372198Abstract: A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.Type: GrantFiled: March 6, 2008Date of Patent: February 12, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jun Seo, Jong-Hyuk Kim, Jong-Heui Song, Yung-Jun Kim, Min-Chul Chae
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Publication number: 20130029158Abstract: Disclosed is a process for producing an epitaxial single-crystal silicon carbide substrate by epitaxially growing a silicon carbide film on a single-crystal silicon carbide substrate by chemical vapor deposition. The step of crystal growth in the process comprises a main crystal growth step, which mainly occupies the period of epitaxial growth, and a secondary crystal growth step, in which the growth temperature is switched between a set growth temperature (T0) and a set growth temperature (T2) which are respectively lower and higher than a growth temperature (T1) used in the main crystal growth step. The basal plane dislocations of the single-crystal silicon carbide substrate are inhibited from being transferred to the epitaxial film. Thus, a high-quality epitaxial film is formed.Type: ApplicationFiled: April 7, 2011Publication date: January 31, 2013Applicant: NIPPON STEEL CORPORATIONInventors: Takashi Aigo, Hiroshi Tsuge, Taizo Hoshino, Tatsuo Fujimoto, Masakazu Katsuno, Masashi Nakabayashi, Hirokatsu Yashiro
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Patent number: 8361551Abstract: In a method of forming a target layer having a uniform composition of constituent materials, a first precursor including a first central atom and a ligand is chemisorbed on a first reaction site of an object. The ligand or the first central atom is then removed to form a second reaction site. A second precursor including a second central atom is then chemisorbed on the second reaction site.Type: GrantFiled: December 29, 2009Date of Patent: January 29, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Jong-Cheol Lee, Ki-Yeon Park, Jun-Noh Lee
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Publication number: 20130014694Abstract: A method of growing a semiconductor epitaxial thin film and a method of fabricating a semiconductor light emitting device using the same are provided. The method of growing a semiconductor epitaxial thin film, includes: disposing a plurality of wafers loaded in a wafer holder in a reaction chamber; and jetting a reactive gas including a chlorine organic metal compound to the wafers through a gas supply unit provided to extend in a direction in which the wafers are loaded, to grow a semiconductor epitaxial thin film on a surface of each of the wafers.Type: ApplicationFiled: July 12, 2012Publication date: January 17, 2013Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jong Sun MAENG, Bum Joon KIM, Hyun Seok RYU, Jung Hyun LEE, Ki Sung KIM
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Patent number: 8349076Abstract: A method of fabricating a freestanding gallium nitride (GaN) substrate includes: preparing a GaN substrate within a reactor; supplying HCl and NH3 gases into the reactor to treat the surface of the GaN substrate and forming a porous GaN layer; forming a GaN crystal growth layer on the porous GaN layer; and cooling the GaN substrate on which the GaN crystal growth layer has been formed and separating the GaN crystal growth layer from the substrate. According to the fabrication method, the entire process including forming a porous GaN layer and a thick GaN layer is performed in-situ within a single reactor. The method is significantly simplified compared to a conventional fabrication method. The fabrication method enables the entire process to be performed in one chamber while allowing GaN surface treatment and growth to be performed using HVPE process gases, thus resulting in a significant reduction in manufacturing costs.Type: GrantFiled: October 11, 2006Date of Patent: January 8, 2013Assignee: Samsung Corning Precision Materials Co., Ltd.Inventors: In-Jae Song, Jai-yong Han
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Patent number: 8337614Abstract: The surface of a gallium nitride single crystal substrate is processed, e.g., comprising steps by planarizing the top side and the bottom side of a gallium nitride original substrate positioned on a support bed; radiating light having wavelengths ranging from 370 to 800 nanometers (nm) onto the planarized gallium nitride original substrate; measuring transmittance of the gallium nitride original substrate; and confirming whether the transmittance is within the range of 65 to 90%. A gallium nitride single crystal substrate obtained through the method of processing the surface has high transmittance ranging from 65 to 90% measured using light having wavelengths of 370 to 800 nm. The thickness ratio (DLa/DLb) of the damage layers on the both sides of the gallium nitride single crystal substrate can be obtained within the range of 0.99 to 1.01.Type: GrantFiled: October 29, 2007Date of Patent: December 25, 2012Assignee: Samsung Corning Precision Materials Co., Ltd.Inventors: Jin Suk Jeong, Ki Soo Lee, Kyoung Jun Kim, Ju Heon Lee, Chang Uk Jin
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Patent number: 8337945Abstract: A method for producing an element including a substrate having a plurality of nanocylinders deposited thereon includes providing the substrate. The substrate is covered with a nanoporous Al2O3 membrane so as to provide a covered substrate. The covered substrate is alternately vapor-deposited, at a vapor-deposition temperatures from 250° C. to 400° C., with atoms of a magnetic element and atoms of a non-magnetic element so as to provide the plurality of nanocylinders. Each nanocylinder includes at least four superposed layers including, alternatively, the atoms of the magnetic element and the atoms of the non-magnetic element. The nanoporous Al2O3 membrane is then removed so that the nanocylinders remain on the substrate.Type: GrantFiled: April 28, 2007Date of Patent: December 25, 2012Assignee: Forschungszentrum Karlsruhe GmbHInventors: Jens Ellrich, Lei Yong, Horst Hahn
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Patent number: 8334015Abstract: A combinatorial processing chamber and method are provided. In the method a fluid volume flows over a surface of a substrate with differing portions of the fluid volume having different constituent components to concurrently expose segregated regions of the substrate to a mixture of the constituent components that differ from constituent components to which adjacent regions are exposed. Differently processed segregated regions are generated through the multiple flowings.Type: GrantFiled: January 14, 2008Date of Patent: December 18, 2012Assignee: Intermolecular, Inc.Inventors: Tony P. Chiang, Sunil Shanker, Chi-I Lang
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Patent number: 8323407Abstract: The invention relates to a method and system for epitaxial deposition of a Group III-V semiconductor material that includes gallium. The method includes reacting an amount of a gaseous Group III precursor having one or more gaseous gallium precursors as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber; and supplying sufficient energy to the gaseous gallium precursor(s) prior to their reacting so that substantially all such precursors are in their monomer forms. The system includes sources of the reactants, a reaction chamber wherein the reactants combine to deposit Group III-V semiconductor material, and one or more heating structures for heating the gaseous Group III precursors prior to reacting to a temperature to decompose substantially all dimers, trimers or other molecular variations of such precursors into their component monomers.Type: GrantFiled: November 3, 2011Date of Patent: December 4, 2012Assignee: SoitecInventors: Chantal Arena, Christiaan Werkhoven
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Patent number: 8309439Abstract: The present invention relates to the growing of nitride semiconductors, applicable for a multitude of semiconductor devices such as diodes, LEDs and transistors. According to the method of the invention nitride semiconductor nanowires are grown utilizing a CVD based selective area growth technique. A nitrogen source and a metal-organic source are present during the nanowire growth step and at least the nitrogen source flow rate is continuous during the nanowire growth step. The V/III-ratio utilized in the inventive method is significantly lower than the V/III-ratios commonly associated with the growth of nitride based semiconductor.Type: GrantFiled: November 8, 2010Date of Patent: November 13, 2012Assignee: QuNano ABInventors: Werner Seifert, Damir Asoli, Zhaoxia Bi
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Patent number: 8298926Abstract: A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility.Type: GrantFiled: December 27, 2007Date of Patent: October 30, 2012Assignees: Siltron Inc., Hynix Semiconductor Inc.Inventors: Hyung-Kook Park, Jin-Kyun Hong, Kun Kim, Chung-Geun Koh
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Patent number: 8293628Abstract: Processes for forming quantum well structures which are characterized by controllable nitride content are provided, as well as superlattice structures, optical devices and optical communication systems based thereon.Type: GrantFiled: May 28, 2010Date of Patent: October 23, 2012Assignee: Technion Research & Development Foundation Ltd.Inventors: Asaf Albo, Gad Bahir, Dan Fekete
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Patent number: 8282733Abstract: The manufacturing method of a semiconductor apparatus has a step for carrying in the substrate into the processing chamber; a step for heating the processing chamber and the substrate to the predetermined temperature; and a gas supply and exhaust step for supplying and exhausting desired gas into and from the processing chamber, wherein the gas supply and exhaust step repeats by the predetermined times a first supply step for supplying silicon-type gas and hydrogen gas into the processing chamber; a first exhaust step for exhausting at least said silicon-type gas from the processing chamber; a second supply step for supplying chlorine gas and hydrogen gas into the processing chamber; and a second exhaust step for exhausting at least the chlorine gas from the processing chamber.Type: GrantFiled: April 1, 2008Date of Patent: October 9, 2012Assignee: Hitachi Kokusai Electric Inc.Inventor: Katsuhiko Yamamoto
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Patent number: 8273177Abstract: An apparatus and methods of forming the apparatus include a film of transparent conductive titanium-doped indium oxide for use in a variety of configurations and systems. The film of transparent conductive titanium-doped indium oxide may be structured as one or more monolayers. The film of transparent conductive titanium-doped indium oxide may be formed using atomic layer deposition.Type: GrantFiled: August 31, 2009Date of Patent: September 25, 2012Assignee: Micron Technology, Inc.Inventors: Kie Y. Ahn, Leonard Forbes
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Patent number: 8268076Abstract: SOI wafers are manufactured by forming on a silicon substrate a monocrystalline first, cubic 1a-3 metal or mixed metal oxide layer whose lattice constant differs from that of the substrate by 5% or less; forming a second cubic 1a-3 mixed metal oxide layer having a lattice constant within 2% of the lattice constant of the first metal or mixed metal oxide layer, and having a graded metal content to vary the lattice content in the second mixed metal oxide layer from that of the first layer, and thermally treating the layered product in an oxygen atmosphere to form an amorphous interlayer between the substrate and the first metal or mixed metal oxide layer.Type: GrantFiled: May 13, 2010Date of Patent: September 18, 2012Assignee: Siltronic AGInventors: Thomas Schroeder, Peter Storck, Hans Joachim Muessig
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Publication number: 20120228627Abstract: A method for producing a compound semiconductor crystal, includes; a sacrificial layer formation step of forming a sacrificial layer containing Cx1Siy1Gez1Sn1-x1-y1-z1 (0?x1<1, 0?y1?1, 0?z1?1, and 0<x1+y1+z1?1), on a base wafer whose surface is made of a silicon crystal; a crystal formation step of forming, on the sacrificial layer, a compound semiconductor crystal lattice-matching or pseudo lattice-matching the sacrificial layer; and a crystal removal step of removing the compound semiconductor crystal from the base wafer, by etching the sacrificial layer.Type: ApplicationFiled: March 15, 2012Publication date: September 13, 2012Applicant: SUMITOMO CHEMICAL COMPANY, LIMITEDInventor: Hiroyuki SAZAWA
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Patent number: 8252112Abstract: A method and apparatus for the unusually high rate deposition of thin film materials on a stationary or continuous substrate. The method includes delivery of a pre-selected precursor intermediate to a deposition chamber and formation of a thin film material from the intermediate. The intermediate is formed outside of the deposition chamber and includes a metastable species such as a free radical. The intermediate is pre-selected to include a metastable species conducive to the formation of a thin film material having a low defect concentration. By forming a low defect concentration material, deposition rate is decoupled from material quality and heretofore unprecedented deposition rates are achieved. In one embodiment, the pre-selected precursor intermediate is SiH3.Type: GrantFiled: September 12, 2008Date of Patent: August 28, 2012Assignee: Ovshinsky Innovation, LLCInventor: Stanford R. Ovshinsky
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Patent number: 8246746Abstract: The present invention is directed to new laser-related uses for single-crystal diamonds produced by chemical vapor deposition. One such use is as a heat sink for a laser; another such use is as a frequency converter. The invention is also directed to a ?(3) nonlinear crystalline material for Raman laser converters comprising single crystal diamond.Type: GrantFiled: January 28, 2008Date of Patent: August 21, 2012Assignee: Carnegie Institution of WashingtonInventors: Russell J. Hemley, Ho-Kwang Mao, Chih-Shiue Yan
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Patent number: 8241422Abstract: It is provided a method of growing gallium nitride single crystal of good quality with a high productivity, in the growth of gallium nitride single crystal by Na-flux method. Gallium nitride single crystal is grown using flux 8 containing at least sodium metal. Gallium nitride single crystal is grown in atmosphere composed of gases mixture “B” containing nitrogen gas at a pressure of 300 atms or higher and 2000 atms or lower. Preferably, the nitrogen partial pressure in the atmosphere is 100 atms or higher and 2000 atms or lower. Preferably, the growth temperature is 1000° C. or higher and 1500° C. or lower.Type: GrantFiled: March 30, 2005Date of Patent: August 14, 2012Assignee: NGK Insulators, Ltd.Inventors: Makoto Iwai, Katsuhiro Imai, Minoru Imaeda
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Patent number: 8236103Abstract: A method for producing a Group III nitride semiconductor crystal includes a first step of supplying a Group III raw material and a Group V raw material at a V/III ratio of 0 to 1,000 to form and grow a Group III nitride semiconductor on a heated substrate and a second step of vapor-phase-growing a Group III nitride semiconductor crystal on the substrate using a Group III raw material and a nitrogen raw material.Type: GrantFiled: February 14, 2003Date of Patent: August 7, 2012Assignee: Showa Denko K.K.Inventors: Hisayuki Miki, Tetsuo Sakurai, Mineo Okuyama
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Patent number: 8231728Abstract: An epitaxial growth method forming a semiconductor thin film including a heterojunction of a group III-V compound semiconductor by means of molecular beam epitaxy. The method is configured to include: a first step of irradiating a molecular beam of at least one of group III elements and a molecular beam of a first group V element to form a first compound semiconductor layer; a second step of stopping the irradiation of the molecular beam of the group III element and the molecular beam of the first group V element to halt growth until an amount of the first group V element supplied is reduced to 1/10 or less of a supply of the first group V element in the first step; and a third step of irradiating a molecular beam of at least one of the group III elements and a molecular beam of a second group V element to form a second compound semiconductor layer, which is different from the first compound semiconductor, on the first compound semiconductor layer.Type: GrantFiled: April 28, 2004Date of Patent: July 31, 2012Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Misao Takakusaki, Susumu Kanai
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Patent number: 8226767Abstract: “Super-hetero-epitaxial” combinations comprise epitaxial growth of one material on a different material with different crystal structure. Compatible crystal structures may be identified using a “Tri-Unity” system. New bandgap engineering diagrams are provided for each class of combination, based on determination of hybrid lattice constants for the constituent materials in accordance with lattice-matching equations. Using known bandgap figures for previously tested materials, new materials with lattice constants that match desired substrates and have the desired bandgap properties may be formulated by reference to the diagrams and lattice matching equations. In one embodiment, this analysis makes it possible to formulate new super-hetero-epitaxial semiconductor systems, such as systems based on group IV alloys on c-plane LaF3; group IV alloys on c-plane langasite; Group III-V alloys on c-plane langasite; and group II-VI alloys on c-plane sapphire.Type: GrantFiled: October 20, 2008Date of Patent: July 24, 2012Assignee: The United States of America as represented by the Administrator of the National Aeronautics and Space AdministrationInventors: Yeonjoon Park, Sang H. Choi, Glen C. King, James R. Elliott
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Patent number: 8216365Abstract: Objects of the invention are to further enhance crystallinity and crystallinity uniformity of a semiconductor crystal produced through the flux method, and to effectively enhance the production yield of the semiconductor crystal. The c-axis of a seed crystal including a GaN single-crystal layer is aligned in a horizontal direction (y-axis direction), one a-axis of the seed crystal is aligned in the vertical direction, and one m-axis is aligned in the x-axis direction. Thus, three contact points at which a supporting tool contacts the seed crystal are present on m-plane. The supporting tool has two supporting members, which extend in the vertical direction. One supporting member has an end part, which is inclined at 30° with respect to the horizontal plane ?. The reasons for supporting a seed crystal at m-plane thereof are that m-plane exhibits a crystal growth rate, which is lower than that of a-plane, and that desired crystal growth on c-plane is not inhibited.Type: GrantFiled: February 29, 2008Date of Patent: July 10, 2012Assignee: Toyoda Gosei Co., Ltd.Inventors: Seiji Nagai, Shiro Yamazaki, Takayuki Sato, Katsuhiro Imai, Makoto Iwai, Takatomo Sasaki, Yusuke Mori, Fumio Kawamura
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Patent number: 8197597Abstract: The present invention is related to the field of semiconductor processing equipment and methods and provides, in particular, methods and equipment for the sustained, high-volume production of Group III-V compound semiconductor material suitable for fabrication of optic and electronic components, for use as substrates for epitaxial deposition, for wafers and so forth. In preferred embodiments, these methods are optimized for producing Group III-N (nitrogen) compound semiconductor wafers and specifically for producing GaN wafers. Specifically, the method includes reacting an amount of a gaseous Group III precursor as one reactant with an amount of a gaseous Group V component as another reactant in a reaction chamber under conditions sufficient to provide sustained high volume manufacture of the semiconductor material on one or more substrates, with the gaseous Group III precursor continuously provided at a mass flow of 50 g Group III element/hour for at least 48 hours.Type: GrantFiled: November 15, 2007Date of Patent: June 12, 2012Assignee: SoitecInventors: Chantal Arena, Christiaan Werkhoven
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Patent number: 8197596Abstract: A crystal growth process comprising providing a reactor having a crucible with an injector apparatus and a seed holder. The injector apparatus has an inner gas conduit and an outer gas conduit wherein an inert gas is introduced into the outer conduit. The injector apparatus has an upper injector and a lower injector and a gap therebetween. The upper injector temperature is maintained at a higher temperature than the lower injector.Type: GrantFiled: July 27, 2007Date of Patent: June 12, 2012Assignee: Pronomic Industry ABInventors: Olof Claes Erik Kordina, Shailaja Rao
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Patent number: 8192543Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.Type: GrantFiled: July 1, 2008Date of Patent: June 5, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
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Publication number: 20120132962Abstract: A method of manufacturing a semiconductor device, in which a second semiconductor layer of AlxGa1-x-yInyN (wherein x, y, and x+y satisfy x>0, y?0, and x+y?1, respectively) on a first semiconductor layer of GaN by hetero-epitaxial growth using a MOCVD method, the method including the steps of: (a) supplying N source gas and Ga source gas to form the first semiconductor layer; (b) supplying the N source gas without supplying the Ga source gas and Al source gas, after step (a); (c) supplying the N source gas and the Al source gas without supplying the Ga source gas, after step (b); and (d) supplying the N source gas, the Ga source gas and the Al source gas to form the second semiconductor layer, after step (c).Type: ApplicationFiled: November 30, 2011Publication date: May 31, 2012Applicant: SANKEN ELECTRIC CO., LTDInventor: Ken Sato
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Publication number: 20120103249Abstract: A physical vapor transport growth system includes a growth chamber charged with SiC source material and a SiC seed crystal in spaced relation and an envelope that is at least partially gas-permeable disposed in the growth chamber. The envelope separates the growth chamber into a source compartment that includes the SiC source material and a crystallization compartment that includes the SiC seed crystal. The envelope is formed of a material that is reactive to vapor generated during sublimation growth of a SiC single crystal on the SiC seed crystal in the crystallization compartment to produce C-bearing vapor that acts as an additional source of C during the growth of the SiC single crystal on the SiC seed crystal.Type: ApplicationFiled: March 25, 2010Publication date: May 3, 2012Applicant: II-VI INCORPORATEDInventors: Avinash K. Gupta, Ilya Zwieback, Edward Semenas, Marcus L. Getkin, Patrick D. Flynn
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Patent number: 8168000Abstract: A method of fabricating a III-nitride power semiconductor device which includes selective prevention of the growth of III-nitride semiconductor bodies to selected areas on a substrate in order to reduce stresses and prevent cracking.Type: GrantFiled: June 14, 2006Date of Patent: May 1, 2012Assignee: International Rectifier CorporationInventors: Mike Briere, Robert Beach
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Patent number: 8164100Abstract: A semiconductor device is provided in which the contact resistance of the interface between an electrode and the semiconductor substrate is reduced. The semiconductor device includes a 4H polytype SiC substrate, and an electrode formed on a surface of the substrate. A 3C polytype layer, which extends obliquely relative to the surface of the substrate and whose end portion at the substrate surface is in contact with the electrode, is formed at the surface of the substrate. The 3C polytype layer has a lower bandgap than 4H polytype. Hence, electrons present in the 4H polytype region pass through the 3C polytype layer and reach the electrode. More precisely, the width of the passageway of the electrons is determined by the thickness of the 3C polytype layer. Consequently, with this semiconductor device, in which the passageway of the electrons is narrow, the electrons are able to reach the electrode at a speed close to the theoretical value, by the quantum wire effect.Type: GrantFiled: December 18, 2008Date of Patent: April 24, 2012Assignees: Toyota Jidosha Kabushiki Kaisha, Denso CorporationInventors: Hirokazu Fujiwara, Masaki Konishi, Eiichi Okuno
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Patent number: 8152918Abstract: Methods of cleaning substrates and growing epitaxial silicon thereon are provided. Wafers are exposed to a plasma for a sufficient time prior to epitaxial silicon growth, in order to clean the wafers. The methods exhibit enhanced selectivity and reduced lateral growth of epitaxial silicon. The wafers may have dielectric areas that are passivated by the exposure of the wafer to a plasma.Type: GrantFiled: June 29, 2006Date of Patent: April 10, 2012Assignee: Micron Technology, Inc.Inventors: Jingyan Zhang, Er-Xuan Ping
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Patent number: 8147612Abstract: There is provided a method for fabricating a gallium nitride crystal with low dislocation density, high crystallinity, and resistance to cracking during polishing of sliced pieces by growing the gallium nitride crystal using a gallium nitride substrate including dislocation-concentrated regions or inverted-polarity regions as a seed crystal substrate. Growing a gallium nitride crystal 79 at a growth temperature higher than 1,100° C. and equal to or lower than 1,300° C. so as to bury dislocation-concentrated regions or inverted-polarity regions 17a reduces dislocations inherited from the dislocation-concentrated regions or inverted regions 17a, thus preventing new dislocations from occurring over the dislocation-concentrated regions or inverted-polarity regions 17a. This also increases the crystallinity of the gallium nitride crystal 79 and its resistance to cracking during the polishing.Type: GrantFiled: April 24, 2007Date of Patent: April 3, 2012Assignee: Sumitomo Electric Industries, Ltd.Inventors: Tomoki Uemura, Takashi Sakurada, Shinsuke Fujiwara, Takuji Okahisa, Koji Uematsu, Hideaki Nakahata
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Patent number: 8142566Abstract: A Ga-containing nitride semiconductor single crystal characterized in that (a) the maximum reflectance measured by irradiating the Ga-containing nitride semiconductor single crystal with light at a wavelength of 450 nm is 20% or less and the difference between the maximum reflectance and the minimum reflectance is within 10%, (b) the ratio of maximum value to minimum value (maximum value/minimum value) of the dislocation density measured by a cathode luminescence method is 10 or less, and/or (c) the lifetime measured by a time-resolved photoluminescence method is 95 ps or more.Type: GrantFiled: August 5, 2005Date of Patent: March 27, 2012Assignee: Mitsubishi Chemical CorporationInventors: Kazumasa Kiyomi, Hirobumi Nagaoka, Hirotaka Oota, Isao Fujimura
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Patent number: 8143147Abstract: A method and apparatus for the deposition of thin films is described. In embodiments, systems and methods for epitaxial thin film formation are provided, including systems and methods for forming binary compound epitaxial thin films. Methods and systems of embodiments of the invention may be used to form direct bandgap semiconducting binary compound epitaxial thin films, such as, for example, GaN, InN and AlN, and the mixed alloys of these compounds, e.g., (In, Ga)N, (Al, Ga)N, (In, Ga, Al)N. Methods and apparatuses include a multistage deposition process and system which enables rapid repetition of sub-monolayer deposition of thin films.Type: GrantFiled: February 10, 2011Date of Patent: March 27, 2012Assignee: Intermolecular, Inc.Inventors: Philip A. Kraus, Sandeep Nijhawan, Thai Cheng Chua
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Patent number: 8137459Abstract: The inventive method for producing nanoparticles for ferrofluids by electron-beam evaporation and condensation in vacuum, consists in evaporating an initial solid material and in fixing nanoparticles to a cooled substrate by means of a solidifiable carrier during vapour condensation, wherein a solid inorganic material, which is selected from a group containing metals, alloys or oxides thereof, is used as an initial material and a solid liquid-soluble material is used as a magnetic carrier material for fixing nanoparticles. The method also consists in simultaneously evaporating the initial material and the carrier composition by electron-beam heating. The vapour is deposited on the substrate, the temperature which is lower than the melting point of the carrier material, and the condensate of the magnetic material nanoparticles, which have a size and are fixed in the carrier, is produced. The particle size is adjusted by setting the specified temperature of the substrate during vapour deposition.Type: GrantFiled: August 22, 2007Date of Patent: March 20, 2012Assignee: State Enterprise “International Center For Electron Beam Technologies of E.O. Paton Electric Welding Institute of National Academy of Sciences of Ukraine”Inventors: Boris Paton, Boris Movchan, Iurii Kurapov
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Patent number: 8137458Abstract: A ZnO crystal growth method has the steps of (a) preparing a substrate having a surface capable of growing ZnO crystal exposing a Zn polarity plane; (b) supplying Zn and O above the surface of the substrate by alternately repeating a Zn-rich condition period and an O-rich condition period; and (c) supplying conductivity type determining impurities above the surface of the substrate while Zn and O are supplied at the step (b).Type: GrantFiled: February 8, 2008Date of Patent: March 20, 2012Assignee: Stanley Electric Co., Ltd.Inventors: Hiroyuki Kato, Michihiro Sano
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Patent number: 8133320Abstract: A laser has a laser material in thermal contact with a diamond, such that the diamond is operable to carry heat away from the laser material. In further embodiments, the diamond has a reduced nitrogen content, is a reduced carbon-13 content, is a monocrystalline or multilayer low-strain diamond, or has a thermal conductivity of greater than 2200 W/mK.Type: GrantFiled: August 24, 2004Date of Patent: March 13, 2012Assignee: Apollo Diamond, Inc.Inventor: Robert Linares
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Patent number: 8123858Abstract: To provide a manufacturing method of a semiconductor device, comprising: loading a substrate, with a silicon surface exposed at a part of the substrate, into a processing chamber; heating an inside of said processing chamber; performing pre-processing of supplying at least silane-based gas, halogen-based gas, and hydrogen gas into said processing chamber, removing at least a natural oxide film or a contaminated matter that exist on a surface of said silicon surface, and growing an epitaxial film on said silicon surface; and supplying gas containing at least silicon into said processing chamber after said pre-processing, and further growing the epitaxial film on said epitaxial film.Type: GrantFiled: September 20, 2007Date of Patent: February 28, 2012Assignee: Hitachi Kokusai Electric Inc.Inventors: Jie Wang, Yasuhiro Ogawa, Katsuhiko Yamamoto, Takashi Yokogawa
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Patent number: 8123859Abstract: A method and apparatus for producing bulk single crystals of AlN having low dislocation densities of about 10,000 cm?2 or less includes a crystal growth enclosure with Al and N2 source material therein, capable of forming bulk crystals. The apparatus maintains the N2 partial pressure at greater than stoichiometric pressure relative to the Al within the crystal growth enclosure, while maintaining the total vapor pressure in the crystal growth enclosure at super-atmospheric pressure. At least one nucleation site is provided in the crystal growth enclosure, and provision is made for cooling the nucleation site relative to other locations in the crystal growth enclosure. The Al and N2 vapor is then deposited to grow single crystalline low dislocation density AlN at the nucleation site. High efficiency ultraviolet light emitting diodes and ultraviolet laser diodes are fabricated on low defect density AlN substrates, which are cut from the low dislocation density AlN crystals.Type: GrantFiled: July 22, 2010Date of Patent: February 28, 2012Assignee: Crystal IS, Inc.Inventors: Leo J. Schowalter, Glen A. Slack, J. Carlos Rojo
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Publication number: 20120037067Abstract: A method for manufacturing a cubic silicon carbide film includes: a first step of introducing a carbon-containing gas onto a silicon substrate and rapidly heating the silicon substrate to an epitaxial growth temperature of cubic silicon carbide so as to carbonize a surface of the silicon substrate and form a cubic silicon carbide film; and a second step of introducing a carbon-containing gas and a silicon-containing gas onto the cubic silicon carbide film while maintaining the cubic silicon carbide film at the epitaxial growth temperature of cubic silicon carbide, so as to allow further epitaxial growth of the cubic silicon carbide film.Type: ApplicationFiled: July 25, 2011Publication date: February 16, 2012Applicant: SEIKO EPSON CORPORATIONInventor: Yukimune WATANABE
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Patent number: 8110041Abstract: A method of producing a single crystal CVD diamond of a desired color which includes the steps of providing single crystal CVD diamond which is colored and heat treating the diamond under conditions suitable to produce the desired color. Colors which may be produced are, for example, in the pink-green range.Type: GrantFiled: April 1, 2009Date of Patent: February 7, 2012Inventors: Daniel James Twitchen, Philip Maurice Martineau, Geoffrey Alan Scarsbrook
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Patent number: 8101018Abstract: In a method for fabricating a semiconductor device and an apparatus for inspecting a semiconductor, laser processing is performed at different laser powers at different positions on a monitor substrate from a plurality of substrates having undergone an SPC step, to form polycrystalline silicon film over the entire area of the substrate. Thereafter, in an optimum power inspection/extraction step, the polycrystalline silicon film formed with varying film quality on the monitor substrate is inspected on inspection equipment to determine the optimum laser power. Then, in a laser processing step, the surface of the subsequent substrates having undergone the SPC step is irradiated with laser at the optimum laser power. Thus, high-quality polycrystalline silicon film is formed over the entire area of the substrate.Type: GrantFiled: March 2, 2005Date of Patent: January 24, 2012Assignee: Sharp Kabushiki KaishaInventor: Yasunobu Tagusa
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Patent number: 8062421Abstract: Shaped nanocrystal particles and methods for making shaped nanocrystal particles are disclosed. One embodiment includes a method for forming a branched, nanocrystal particle. It includes (a) forming a core having a first crystal structure in a solution, (b) forming a first arm extending from the core having a second crystal structure in the solution, and (c) forming a second arm extending from the core having the second crystal structure in the solution.Type: GrantFiled: October 9, 2007Date of Patent: November 22, 2011Assignee: The Regents of the University of CaliforniaInventors: A. Paul Alivisatos, Erik C. Scher, Liberato Manna
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Patent number: 8048224Abstract: Embodiments of the invention relate to a process for producing a III-N bulk crystal, wherein III denotes at least one element selected from group III of the periodic system, selected from Al, Ga and In, wherein the III-N bulk crystal is grown by vapor phase epitaxy on a substrate, and wherein the growth rate is measured in real-time. By actively measuring and controlling the growth rate in situ, i.e. during the epitaxial growth, the actual growth rate can be maintained essentially constant. In this manner, III-N bulk crystals and individualized III-N single crystal substrates separated therefrom, which respectively have excellent crystal quality both in the growth direction and in the growth plane perpendicular thereto, can be obtained.Type: GrantFiled: May 7, 2007Date of Patent: November 1, 2011Assignee: Freiberger Compound Materials GmbHInventors: Gunnar Leibiger, Frank Habel, Stefan Eichler