Including Change In A Growth-influencing Parameter (e.g., Composition, Temperature, Concentration, Flow Rate) During Growth (e.g., Multilayer Or Junction Or Superlattice Growing) Patents (Class 117/89)
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Patent number: 7481880Abstract: A method of crystallizing amorphous silicon includes forming an amorphous silicon layer on a substrate, placing a mask over the substrate including the amorphous silicon layer, and applying a laser beam onto the amorphous silicon layer through the mask to form a first crystallized region, the laser beam having an energy intensity high enough to completely melt the amorphous silicon layer, wherein the mask comprises a base substrate, a phase shift layer on the base substrate, having a plurality of first stripes having a first width separated by slits, and a blocking layer overlapping the phase shift layer, having a plurality of second stripes having a second width narrower than the first width, the second stripes being parallel to the first stripes.Type: GrantFiled: January 25, 2006Date of Patent: January 27, 2009Assignee: LG Display Co., Ltd.Inventor: Kwang-Jo Hwang
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Patent number: 7479443Abstract: A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 ?. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.Type: GrantFiled: October 4, 2007Date of Patent: January 20, 2009Assignee: ASM America Inc.Inventors: Matthias Bauer, Paul Brabant, Trevan Landin
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Patent number: 7479187Abstract: A silicon epitaxial wafer manufacturing method, in which a vapor phase growth of a silicon epitaxial layer is performed on a front surface of a silicon single crystal substrate (W) arranged in the reaction chamber (12). A silicon deposit deposited in the reaction chamber (12) is removed by etching an inside of the reaction chamber (12) with a hydrogen chloride gas in a state that a silicon crystal substrate (W) is not introduced, and thereafter, a primary cooling is performed in the reaction chamber (12). Subsequently, a secondary cooling is performed after heating an inside of the reaction chamber (12), and thereafter, the vapor phase growth is performed to manufacture a silicon epitaxial wafer.Type: GrantFiled: August 19, 2003Date of Patent: January 20, 2009Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Toru Otsuka
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Patent number: 7473316Abstract: What is described here is a process for the initial growth of nitrogenous semiconductor crystal materials in the form AXBYCZNVMW wherein A, B, C is an element of group II or III, N is nitrogen, M represents an element of group V or VI, and X, Y, Z, W denote the molar fraction of each element of this compound, using a, which are deposited on sapphire, SiC or Si, using various ramp functions permitting a continuous variation of the growth parameters during the initial growth.Type: GrantFiled: July 24, 2000Date of Patent: January 6, 2009Assignee: Aixtron AGInventors: Bernd Schottker, Michael Heuken, Holger Jürgensen, Gerd Strauch, Bernd Wachtendorf
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Patent number: 7465499Abstract: A boron phosphide-based semiconductor device enhanced in properties includes a substrate (11) composed of a {111}-Si single crystal having a surface {111} crystal plane and a boron phosphide-based semiconductor layer formed on the surface of the substrate and composed of a polycrystal layer (12) that is an aggregate of a plurality of a triangular pyramidal single crystal entities (13) of the boron phosphide-based semiconductor crystal, where in each single crystal entity has a twining interface that forms an angle of 60° relative to a <110> crystal direction of the substrate.Type: GrantFiled: January 28, 2003Date of Patent: December 16, 2008Assignee: Showa Denko K.K.Inventors: Takashi Udagawa, Tamotsu Yamashita
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Patent number: 7465353Abstract: It is to provide a method for growing an epitaxial crystal in which the doping conditions are set when an epitaxial crystal having a desired carrier concentration is grown. A method for growing an epitaxial crystal while a dopant is added to a compound semiconductor substrate, comprises: obtaining a relation between an off angle and a doping efficiency with regards to the same type of compound semiconductor substrate in advance; and setting a doping condition for carrying out an epitaxial growth on the compound semiconductor substrate based on the obtained relation and a value of the off angle of the subtrate.Type: GrantFiled: June 6, 2005Date of Patent: December 16, 2008Assignee: Nippon Mining & Metals Co., Ltd.Inventors: Manabu Kawabe, Ryuichi Hirano
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Publication number: 20080302298Abstract: A semiconductor structure is disclosed that includes a silicon carbide wafer having a diameter of at least 100 mm with a Group III nitride heterostructure on the wafer that exhibits high uniformity in a number of characteristics. These include: a standard deviation in sheet resistivity across the wafer less than three percent; a standard deviation in electron mobility across the wafer of less than 1 percent; a standard deviation in carrier density across the wafer of no more than about 3.3 percent; and a standard deviation in conductivity across the wafer of about 2.5 percent.Type: ApplicationFiled: May 12, 2008Publication date: December 11, 2008Applicant: CREE, INC.Inventors: Adam William Saxler, Edward Lloyd Hutchins
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Patent number: 7462239Abstract: Methods are provided for low temperature, rapid baking to remove impurities from a semiconductor surface prior to in-situ deposition. Advantageously, a short, low temperature process consumes very little of the thermal budget, such that the process is suitable for advanced, high density circuits with shallow junctions. Furthermore, throughput is greatly improved by the low temperature bake, particularly in combination with low temperature plasma cleaning and low temperature wafer loading prior to the bake, and deposition after the bake at temperatures lower than conventional epitaxial deposition. The process enables epitaxial deposition of silicon-containing layers over semiconductor surfaces, particularly enabling epitaxial deposition over a silicon germanium base layer. By use of a low-temperature bake, the silicon germanium base layer can be cleaned to facilitate further epitaxial deposition without relaxing the strained crystal structure of the silicon germanium.Type: GrantFiled: May 12, 2006Date of Patent: December 9, 2008Assignee: ASM America, Inc.Inventors: Paul D. Brabant, Joe P. Italiano, Jianqing Wen
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Patent number: 7459024Abstract: Synthetic monocrystalline diamond compositions having one or more monocrystalline diamond layers formed by chemical vapor deposition, the layers including one or more layers having an increased concentration of one or more impurities (such as boron and/or isotopes of carbon), as compared to other layers or comparable layers without such impurities. Such compositions provide an improved combination of properties, including color, strength, velocity of sound, electrical conductivity, and control of defects. A related method for preparing such a composition is also described, as well as a system for use in performing such a method, and articles incorporating such a composition.Type: GrantFiled: October 29, 2004Date of Patent: December 2, 2008Assignee: Apollo Diamond, Inc.Inventors: Robert C. Linares, Patrick J. Doering
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Patent number: 7455730Abstract: A method for producing a single crystal includes supplying a vapor gas from silicon carbide as a raw material to a seed crystal formed of a silicon carbide single crystal to grow the seed crystal. The seed crystal is disposed in a part of crystal growth, with a crystal face of the seed crystal inclined relative to a (0001) plane or (000-1) plane, thereby making crystal growth.Type: GrantFiled: June 15, 2004Date of Patent: November 25, 2008Assignee: Showa Denko K.K.Inventor: Naoki Oyanagi
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Patent number: 7442253Abstract: The present invention is directed to a process for producing a silicon wafer which, during the heat treatment cycles of essentially any arbitrary electronic device manufacturing process, may form an ideal, non-uniform depth distribution of oxygen precipitates and may additionally contain an axially symmetric region which is substantially free of agglomerated intrinsic point defects. The process either comprises exposing the wafer's front and back surfaces to different atmospheres, or thermally annealing two wafers in a face-to-face arrangement.Type: GrantFiled: May 24, 2007Date of Patent: October 28, 2008Assignee: MEMC Electronic Materials, Inc.Inventors: Robert J. Falster, Joseph C. Holzer, Marco Cornara, Daniela Gambaro, Massimiliano Olmo, Steve A. Markgraf, Paolo Mutti, Seamus A. McQuaid, Bayard K. Johnson
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Patent number: 7442252Abstract: The present invention provides methods for producing a multi-element oxide single crystal which contains Bi, which has high crystallinity independently of a preparation process, and which is represented by the formula (Bi2O2)Am?1BmO3m+1, wherein A is Sr, Ba, Ca, or Bi and B is Ti, Ta, or Nb. A flux layer, containing a composition satisfying the inequality 0<CuO/Bi2O3<2 and/or 0?TiO/Bi2O3<7/6 on a molar basis is deposited on a wafer and a single-crystalline thin-film is then deposited on the flux layer placed on the wafer. A melt of a composition which contains raw materials and a flux and which satisfies the above inequality is prepared and the melt is cooled such that a single crystal is grown. A CuO flux layer is deposited on a wafer and Bi—Ti—O is supplied to the flux layer using a Bi6Ti3O12, Bi7Ti3O12, or Bi8Ti3O12 target of which the Bi content is greater than that of an object film such that a Bi4Ti3O12 single-crystalline thin-film is formed above the wafer.Type: GrantFiled: May 21, 2004Date of Patent: October 28, 2008Assignee: Japan Science and Technology AgencyInventors: Hideomi Koinuma, Yuji Matsumoto, Ryota Takahashi
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Patent number: 7438762Abstract: A manufacture method that can manufacture ZnO based compound semiconductor crystal of good quality. A ZnO substrate is prepared to have a principal surface made of a plurality of terraces of (0001) planes arranged stepwise along an m-axis direction, the envelop of the principal surface being inclined relative to the (0001) plane by about 2 degrees or less. ZnO based compound semiconductor crystal is grown on the principal surface.Type: GrantFiled: August 24, 2006Date of Patent: October 21, 2008Assignee: Stanley Electric Co., Ltd., Tokyo Denpa Co., Ltd., and Tohoku UniversityInventors: Hiroyuki Kato, Michihiro Sano, Katsumi Maeda, Hiroshi Yoneyama, Takafumi Yao, Meoung Whan Cho
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Patent number: 7438760Abstract: Methods of making Si-containing films that contain relatively high levels of substitutional dopants involve chemical vapor deposition using trisilane and a dopant precursor. Extremely high levels of substitutional incorporation may be obtained, including crystalline silicon films that contain 2.4 atomic % or greater substitutional carbon. Substitutionally doped Si-containing films may be selectively deposited onto the crystalline surfaces of mixed substrates by introducing an etchant gas during deposition.Type: GrantFiled: January 30, 2006Date of Patent: October 21, 2008Assignee: ASM America, Inc.Inventors: Matthias Bauer, Keith Doran Weeks, Pierre Tomasini, Nyles Cody
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Patent number: 7435297Abstract: A method for growing Group III nitride materials using a molten halide salt as a solvent to solubilize the Group-III ions and nitride ions that react to form the Group III nitride material. The concentration of at least one of the nitride ion or Group III cation is determined by electrochemical generation of the ions.Type: GrantFiled: April 8, 2005Date of Patent: October 14, 2008Assignee: Sandia CorporationInventors: Karen E. Waldrip, Jeffrey Y. Tsao, Thomas M. Kerley
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Patent number: 7431767Abstract: An improved apparatus and method for substrate layer deposition in which substrate layers are grown by carrier gas delivery of sequential pulses of reactants to the substrate surface. At least one of the reactants comprises excited species, e.g., radicals. In a specific embodiment, the apparatus of this invention provides sequential repeated pulses of reactants in a flow of carrier gas for reaction at a substrate surface. The reactant pulses are delivered with sufficient intervening delay times to minimize undesirable reaction between reactants in adjacent pulses in the gas phase or undesired uncontrolled reactions on the substrate surface.Type: GrantFiled: November 27, 2006Date of Patent: October 7, 2008Assignee: ASM America, Inc.Inventor: Ivo Raaijmakers
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Patent number: 7427326Abstract: A method of forming a bipolar device includes forming at least one p-type layer of single crystal silicon carbide and at least one n-type layer of single crystal silicon carbide on a substrate. Stacking faults that grow under forward operation of the device are segregated from at least one of the interfaces between the active region and the remainder of the device. The method of forming bipolar devices includes growing at least one of the epitaxial layers to a thickness greater than the minority carrier diffusion length in that layer. The method also increases the doping concentration of epitaxial layers surrounding the drift region to decrease minority carrier lifetimes therein.Type: GrantFiled: November 16, 2006Date of Patent: September 23, 2008Assignee: Cree, Inc.Inventors: Joseph J. Sumakeris, Ranbir Singh, Michael James Paisley, Stephan Georg Mueller, Hudson M. Hobgood, Calvin H. Carter, Jr., Albert Augustus Burk, Jr.
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Publication number: 20080213158Abstract: A manufacturing apparatus of Group III nitride crystals and a method for manufacturing Group III nitride crystals are provided, by which high quality crystals can be manufactured. For instance, crystals are grown using the apparatus of the present invention as follows. A crystal raw material (131) and gas containing nitrogen are introduced into a reactor vessel (120), to which heat is applied by a heater (110), and crystals are grown in an atmosphere of pressure applied thereto. The gas is introduced from a gas supplying device (180) to the reactor vessel (120) through a gas inlet of the reactor vessel, and then is exhausted to the inside of a pressure-resistant vessel (102) through a gas outlet of the reactor vessel. Since the gas is introduced directly to the reactor vessel (120) without passing through the pressure-resistant vessel (102), the mixture of impurities attached to the pressure-resistant vessel (102) and the like into the site of the crystal growth can be prevented.Type: ApplicationFiled: April 14, 2008Publication date: September 4, 2008Applicants: Matsushita Electric Industrial Co., Ltd.Inventors: Hisashi Minemoto, Yasuo Kitaoka, Isao Kidoguchi, Yusuke Mori, Fumio Kawamura, Takatomo Sasaki, Hidekazu Umeda, Yasuhito Takahashi
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Patent number: 7416605Abstract: An anneal of an epitaxially grown crystalline semiconductor layer comprising a combination of group-IV elements. The layer contains at least one of the group of carbon and tin. The layer of epitaxially grown material is annealed at a temperature substantially in a range of 1,000 to 1,400 degrees Celsius for a period not to exceed 100 milliseconds within 10% of the peak temperature. The anneal is performed for example with a laser anneal or a flash lamp anneal. The limited-time anneal may improve carrier mobility of a transistor.Type: GrantFiled: January 8, 2007Date of Patent: August 26, 2008Assignee: Freescale Semiconductor, Inc.Inventors: Stefan Zollner, Veeraraghavan Dhandapani, Paul A. Grudowski, Gregory S. Spencer
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Patent number: 7416606Abstract: The invention relates to a method of forming a layer of silicon carbide on a silicone wafer. The method includes the following steps: depositing an anti-carburation mask on the wafer using an essentially-check pattern; performing a carburation step under conditions such that the residual stress takes the form of extension and compression respectively; removing the mask; and form of extension and compression respectively; removing the mask; and performing a carburation step under conditions such that the residual stress takes form of compression and extension respectively.Type: GrantFiled: May 5, 2004Date of Patent: August 26, 2008Assignee: Centre National de la Recherche ScientifiqueInventor: André Leycuras
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Patent number: 7416604Abstract: A nitride crystal is characterized in that, in connection with plane spacing of arbitrary specific parallel crystal lattice planes of the nitride crystal obtained from X-ray diffraction measurement performed with variation of X-ray penetration depth from a surface of the crystal while X-ray diffraction conditions of the specific parallel crystal lattice planes are satisfied, a uniform distortion at a surface layer of the crystal represented by a value of |d1?d2|/d2 obtained from the plane spacing d1 at the X-ray penetration depth of 0.3 ?m and the plane spacing d2 at the X-ray penetration depth of 5 ?m is equal to or lower than 2.1×10?3.Type: GrantFiled: June 23, 2006Date of Patent: August 26, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Keiji Ishibashi, Tokiko Kaji, Seiji Nakahata, Takayuki Nishiura
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Patent number: 7413608Abstract: A crystallization apparatus includes an illumination system which applies illumination light for crystallization to a non-single-crystal semiconductor film, and a phase shifter which includes first and second regions disposed to form a straight boundary and transmitting the illumination light from the illumination system by a first phase retardation therebetween, and phase-modulates the illumination light to provide a light intensity distribution having an inverse peak pattern that light intensity falls in a zone of the non-single-crystal semiconductor film containing an axis corresponding to the boundary. The phase shifter further includes a small region which extends into at least one of the first and second regions from the boundary and transmits the illumination light by a second phase retardation with respect to the at least one of the first and second regions.Type: GrantFiled: September 13, 2005Date of Patent: August 19, 2008Assignee: Advanced LCD Technologies Development Center Co., Ltd.Inventors: Yukio Taniguchi, Masakiyo Matsumura, Hirotaka Yamaguchi, Mikihiko Nishitani, Susumu Tsujikawa, Yoshinobu Kimura, Masayuki Jyumonji
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Patent number: 7404858Abstract: A method for epitaxial growth of silicon carbide using chemical vapor deposition (CVD) is provided. This method utilizes halogenated carbon precursors and control of the gas-phase interaction of halogen-containing intermediate chemical products involving silicon and carbon, which ensures quality and homogeneity across the silicon carbide crystals. It also ensures a possibility to achieve device-quality epitaxial layers at lower growth temperatures as well as on on-axis or low off-angle substrate surfaces. The growth method can be applied to forming SiC device regions of desirable shape and dimensions by restricting the growth into windows formed in non-silicon carbide region on the top of SiC substrate. Application of the methods described herein will greatly benefit the production of high quality silicon carbide materials and devices.Type: GrantFiled: September 15, 2006Date of Patent: July 29, 2008Assignee: Mississippi State UniversityInventor: Yaroslav Koshka
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Patent number: 7393412Abstract: A method for manufacturing a compound semiconductor epitaxial substrate with few concave defects is provided. The method for manufacturing a compound semiconductor epitaxial substrate comprises a step of epitaxially growing an InGaAs layer on an InP single crystal substrate or on an epitaxial layer lattice-matched to the InP single crystal substrate under conditions of ratio of V/: 10-100, growth temperature: 630° C.-700° C., and growth rate: 0.6 ?m/h-2 ?m/h.Type: GrantFiled: November 8, 2004Date of Patent: July 1, 2008Assignee: Sumitomo Chemical Company, LimitedInventors: Kenji Kohiro, Tomoyuki Takada
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Publication number: 20080149020Abstract: A method and a device to grow from the vapor phase, a single crystal of either SiC, a group III-nitride, or alloys thereof, at a growth rate and for a period of time sufficient to produce a crystal of preferably several centimeters length. The diameter of the growing crystal may be controlled. To prevent the formation of undesirable polycrystalline deposits on surfaces in the downstream vicinity of the single crystal growth area, the local supersaturation of at least one component of the material grown is lowered by introducing a separate gas flow comprising at least one halogen element or a combination of said halogen and hydrogen species.Type: ApplicationFiled: February 29, 2008Publication date: June 26, 2008Applicant: NORSTEL ABInventors: Erik Janzen, Peter Raback, Alexandre Ellison
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Patent number: 7387678Abstract: A GaN substrate comprises a GaN single crystal substrate, an AlxGa1-xN intermediate layer (0<x?1) epitaxially grown on the substrate, and an GaN epitaxial layer grown on the intermediate layer. The intermediate layer is made of AlGaN and this AlGaN grows over the entire surface of the substrate with contaminants thereon and high dislocation regions therein. Thus, the intermediate layer is normally grown on the substrate, and a growth surface of the intermediate layer can be made flat. Since the growth surface is flat, a growth surface of the GaN epitaxial layer epitaxially grown on the intermediate layer is also flat.Type: GrantFiled: June 25, 2004Date of Patent: June 17, 2008Assignee: Sumitomo Electric Industries, Ltd.Inventors: Katsushi Akita, Eiryo Takasuka, Masahiro Nakayama, Masaki Ueno, Kouhei Miura, Takashi Kyono
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Patent number: 7384479Abstract: An optical semiconductor device operable in a 0.6 ?m band includes an active layer of GaInNP sandwiched by a pair of GaInP layer with a thickness of about 2 molecular layers or less.Type: GrantFiled: March 16, 2005Date of Patent: June 10, 2008Assignee: Ricoh Company, Ltd.Inventors: Naoto Jikutani, Shunichi Sato, Takashi Takahashi
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Patent number: 7377976Abstract: A method is provided for growing thin oxide films on the surface of a substrate by alternatively reacting the surface of the substrate with a metal source material and an oxygen source material. The oxygen source material is preferably a metal alkoxide. The metal source material may be a metal halide, hydride, alkoxide, alkyl, a cyclopentadienyl compound, or a diketonate.Type: GrantFiled: August 22, 2005Date of Patent: May 27, 2008Inventors: Mikko Ritala, Antti Rahtu, Markku Leskela, Kaupo Kukli
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Patent number: 7377978Abstract: It is to provide a method for producing a silicon epitaxial wafer, which can prevent fine unevenness from occurring on a rear main surface of a silicon epitaxial wafer and which suppresses the haze level of the whole rear main surface to 50 ppm or less. A method for producing a silicon epitaxial wafer, includes: a hydrogen heat treatment step of arranging within a reactor a susceptor capable of mounting a silicon single crystal substrate and subjecting the silicon single crystal substrate mounted on the susceptor to heat treatment in a hydrogen atmosphere, and a vapor phase epitaxy step of epitaxially growing a silicon epitaxial layer after the hydrogen heat treatment step, wherein the silicon single crystal substrate is separated from the susceptor during the hydrogen heat treatment step, and the silicon single crystal substrate is mounted on the susceptor during the vapor phase epitaxy step.Type: GrantFiled: June 21, 2004Date of Patent: May 27, 2008Assignee: Shin-Etsu Handotai Co., Ltd.Inventor: Tsuyoshi Nishizawa
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Patent number: 7377977Abstract: A method of growing a crystal on a substrate disposed in a reactor, that provides a reactor chamber in which the substrate is disposed, includes flowing reactive gases inside the reactor chamber toward the substrate, the reactive gases comprising components that are able to bond to each other to form the crystal, and flowing buffer gas in the reactor chamber between the reactive gases and a wall of the reactor, where the flowing buffer gas inhibits at least one of a first material at least one of in and produced by the reactive gases from reaching the reactor wall and a second material produced by the reactor wall from reaching the reactive gases in the reactor chamber before the reactive gases reach the substrate.Type: GrantFiled: May 30, 2006Date of Patent: May 27, 2008Assignee: Cape Simulations, Inc.Inventors: Shariar Motakef, Aniruddha S. Worlikar
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Patent number: 7374617Abstract: The invention includes atomic layer deposition methods and chemical vapor deposition methods. In a particular aspect of the invention, a source of microwave radiation is provided proximate a reaction chamber. At least a fragment of a precursor material is chemisorbed on a substrate within the reaction chamber while not exposing the precursor material to microwave radiation from the source. Excess precursor material is removed from the chamber, and the chemisorbed material is subsequently exposed to microwave radiation from the source within the reaction chamber.Type: GrantFiled: April 25, 2002Date of Patent: May 20, 2008Assignee: Micron Technology, Inc.Inventor: Brian A. Vaartstra
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Publication number: 20080113186Abstract: A method is provided for growing Si—Ge materials on Si(100) with Ge-rich contents (Ge>50 at. %) and precise stoichiometries SiGe, SiGe2, SiGe3 and SiGe4. New hydrides with direct Si—Ge bonds derived from the family of compounds (H3Ge)xSiH4-x (x=1-4) are used to grow uniform, relayed and highly planar films with low defect densities at unprecedented low temperatures between about 300-450° C., circumventing entirely the need of thick compositionally graded buffer layer and lift off technologies. At about 500-700° C., SiGex quantum dots are grown with narrow size distribution, defect-free microstructures and highly homogeneous elemental content at the atomic level. The method provides precise control of morphology, composition, structure and strain via the incorporation of the entire Si/Ge framework of the gaseous precursor into the film.Type: ApplicationFiled: April 8, 2005Publication date: May 15, 2008Inventors: John Kouvetakis, Ignatius S.T. Tsong, Changwu Hu, John Tolle
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Patent number: 7371282Abstract: A substrate and method for growing a semi-conductive crystal on an alloy film such as (AIN)x(SiC)(1-x) without any buffer layer is disclosed. The (AIN)x(SiC)(1-x) alloy film can be formed on a SiC substrate by a vapor deposition process using AlN and SiC powder as starting materials. The (AIN)x(SiC)(1-x) alloy film provides a better lattice match for GaN or SiC epitaxial growth and reduces defects in epitaxially grown GaN with better lattice match and chemistry.Type: GrantFiled: July 12, 2006Date of Patent: May 13, 2008Assignee: Northrop Grumman CorporationInventors: Narsingh Bahadur Singh, Brian Wagner, Mike Aumer, Darren Thomson, David Kahler, Andre Berghmans, David J. Knuteson
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Patent number: 7371281Abstract: A growth crucible (2) for depositing on a seed crystal substrate (5) a silicon carbide single crystal (6) using a sublimate gas of a silicon carbide raw material (11) is disposed inside of an outer crucible (1). During the course of silicon carbide single crystal, a silicon raw material (22) is continuously fed from outside into a space between the growth crucible and the outer crucible for the purpose of vaporizing the silicon raw material. An atmosphere gas surrounding the growth crucible is constituted of a silicon gas. The pressure of the atmosphere silicon gas is controlled to suppress a variation in the composition of the sublimate gas within the growth crucible to thereby grow a large-sized silicon carbide single crystal with few crystal defects on the seed crystal substrate reliably at a high growth rate.Type: GrantFiled: September 18, 2003Date of Patent: May 13, 2008Assignee: Showa Denko K.K.Inventors: Yasuyuki Sakaguchi, Atsushi Takagi, Naoki Oyanagi
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Patent number: 7368014Abstract: A deposition method may include, at a first temperature, contacting a substrate with a first precursor and chemisorbing a first layer at least one monolayer thick over the substrate. At a second temperature different from the first temperature, the first layer may be contacted with a second precursor, chemisorbing a second layer at least one monolayer thick on the first layer. Temperature may be altered by adding or removing heat with a thermoelectric heat pump. The altering the substrate temperature may occur from the first to the second temperature. The second layer may be reacted with the first layer by heating to a third temperature higher than the second temperature. A deposition method may also include atomic layer depositing a first specie of a substrate approximately at an optimum temperature for the first specie deposition.Type: GrantFiled: August 9, 2001Date of Patent: May 6, 2008Assignee: Micron Technology, Inc.Inventor: Trung Tri Doan
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Patent number: 7364617Abstract: A silicon carbide seeded sublimation method is disclosed. The method includes the steps of nucleating growth on a seed crystal growth face that is between about 1° and 10° off-axis from the (0001) plane of the seed crystal while establishing a thermal gradient between the seed crystal and a source composition that is substantially perpendicular to the basal plane of the off-axis crystal.Type: GrantFiled: February 5, 2007Date of Patent: April 29, 2008Assignee: Cree, Inc.Inventors: Stephan Mueller, Adrian Powell, Valeri F. Tsvetkov
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Patent number: 7361220Abstract: The present invention provides a method of manufacturing a gallium nitride single crystal that can suppress the decomposition of gallium nitride and improve production efficiency in a sublimation method. According to the manufacturing method, a material (GaN powder) for the gallium nitride (GaN) single crystal is placed inside a crucible, sublimed or evaporated by heating, and cooled on a substrate surface to return to a solid again, so that the gallium nitride single crystal is grown on the substrate surface. The growth of the single crystal is performed under pressure. The pressure is preferably not less than 5 atm (5×1.013×105 Pa). The single crystal is grown preferably in a mixed gas atmosphere containing NH3 and N2.Type: GrantFiled: March 25, 2004Date of Patent: April 22, 2008Assignees: Matsushita Electric Industrial Co., Ltd.Inventors: Takatomo Sasaki, Yusuke Mori, Fumio Kawamura, Masashi Yoshimura, Yasunori Kai, Mamoru Imade, Yasuo Kitaoka, Hisashi Minemoto, Isao Kidoguchi
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Patent number: 7351285Abstract: A method and system for forming a variable thickness seed layer on a substrate for a subsequent metal electrochemical plating process, where the seed layer thickness profile improves uniformity of the electroplated metal layer compared to when using a constant thickness seed layer. The method includes providing a substrate in a process chamber containing a showerhead, with the center of the substrate generally aligned with an inner gas delivery zone of the showerhead and the edge of the substrate generally aligned with an outer gas delivery zone of the showerhead. The method further includes depositing a seed layer on the substrate by exposing the substrate to a first gas containing a metal-containing precursor flowed through the inner gas delivery zone, and exposing the substrate to a second gas flowed through the outer gas delivery zone, whereby the seed layer is deposited with a thickness at the edge of the substrate that is less than the thickness at the center of the substrate.Type: GrantFiled: March 29, 2005Date of Patent: April 1, 2008Assignee: Tokyo Electron LimitedInventor: Tsukasa Matsuda
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Patent number: 7341944Abstract: Methods for synthesizing metal nanowires are provided. A metalorganic layer is deposited on a substrate as a thin film. The thermal decomposition of the metalorganic thin film in the presence of air synthesizes metal nanowires. The metal can be varied to produce nanowires with different properties.Type: GrantFiled: September 15, 2005Date of Patent: March 11, 2008Assignee: Honda Motor Co., LtdInventor: Avetik Harutyunyan
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Patent number: 7335259Abstract: The present invention provides nanowires which are substantially straight and substantially free of nanoparticles and methods for making the same The nanowires can be made by seeded approaches, wherein nanocrystals bound to a substrate are used to promote growth of the nanowire. Nanocrystals in solution may also be used to make the nanowires of the present invention. Supercritical fluid reaction conditions can be used in a continuous or semi-batch process.Type: GrantFiled: July 6, 2004Date of Patent: February 26, 2008Inventors: Tobias Hanrath, Xianmao Lu, Keith Johnston, Brian Korgel
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Patent number: 7329593Abstract: A method comprises, in a reaction chamber, depositing a seed layer of germanium over a silicon-containing surface at a first temperature. The seed layer has a thickness between about one monolayer and about 1000 ?. The method further comprises, after depositing the seed layer, increasing the temperature of the reaction chamber while continuing to deposit germanium. The method further comprises holding the reaction chamber in a second temperature range while continuing to deposit germanium. The second temperature range is greater than the first temperature.Type: GrantFiled: February 25, 2005Date of Patent: February 12, 2008Assignee: ASM America, Inc.Inventors: Matthias Bauer, Paul Brabant, Trevan Landin
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Patent number: 7329364Abstract: A method for manufacturing a bonded wafer with ultra-thin single crystal ferroelectric film is provided, comprising the following steps: providing a single crystal ferroelectric wafer and a carrier wafer while activating the surfaces of the single crystal ferroelectric wafer and the carrier wafer; bonding the activated surface of the single crystal ferroelectric wafer to the activated surface of the carrier wafer; and thinning the single crystal ferroelectric wafer for forming an ultra-thin single crystal ferroelectric film. Wherein, the thinning process in the aforesaid preferred embodiment is the method of polishing, grinding, chemical mechanical polishing, or etching. And the bonding force generated in the bonding process is strong enough to resist the shearing force.Type: GrantFiled: November 2, 2004Date of Patent: February 12, 2008Assignee: Industrial Technology Research InstituteInventors: Shih-Shian Ho, Hung-Yin Tsai, Chia-Jen Ting, Chun-Fa Lan, Chii-Chang Chen
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Patent number: 7326295Abstract: The present invention relates to a fabrication method for polycrystalline silicon thin film in which amorphous silicon is crystallized by laser using a mask having a mixed structure of laser transmission pattern group and laser non-transmission pattern group, wherein the mask comprises two or more of dot pattern groups in which the non-transmission pattern group is perpendicular to a scan directional axis, and the dot pattern groups are formed in a certain shape and comprise first non-transmission patterns that are not respectively arranged in a row in an axis direction perpendicular to the scan directional axis, and second non-transmission patterns that are formed in the same arrangement as the first non-transmission patterns, but are positioned in such a manner that the second non-transmission patterns are parallel to the first non-transmission patterns and vertical axis of the scan directional axis.Type: GrantFiled: September 30, 2004Date of Patent: February 5, 2008Assignee: Samsung SDI Co., Ltd.Inventors: Ji-Yong Park, Hye-Hyang Park
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Patent number: 7323400Abstract: A plasma processing method includes providing a substrate in a processing chamber, the substrate having a surface, and generating a plasma in the processing chamber. The plasma provides at least two regions that exhibit different plasma densities. The method includes exposing at least some of the surface to both of the at least two regions. Exposing the surface to both of the at least two regions may include rotating the plasma and may cyclically expose the surface to the plasma density differences. Exposing to both of the at least two regions may modify a composition and/or structure of the surface. The plasma may include a plasmoid characterized by a steady state plasma wave providing multiple plasma density lobes uniformly distributed about an axis of symmetry and providing plasma between the lobes exhibiting lower plasma densities. Depositing the layer can include ALD and exposure may remove an ALD precursor ligand.Type: GrantFiled: August 30, 2004Date of Patent: January 29, 2008Assignee: Micron Technology, Inc.Inventor: Neal R. Rueger
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Patent number: 7323052Abstract: An apparatus and method for growing bulk single crystals of silicon carbide is provided. The apparatus includes a sublimation chamber with a silicon vapor species phase outlet that allows the selective passage of atomic silicon vapor species while minimizing the concurrent passage of other vapor phase species. The apparatus can provide control of vapor phase stoichiometry within the sublimation chamber, which in turn can allow the production of bulk silicon carbide single crystals with reduced intrinsic point defects concentration.Type: GrantFiled: March 24, 2005Date of Patent: January 29, 2008Assignee: Cree, Inc.Inventors: Valeri F. Tsvetkov, David Phillip Malta, Jason Ronald Jenny
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Patent number: 7320732Abstract: A method for preparing film oxides deposited on a substrate with a resulting grain boundary junction that is atomistically straight. A bicrystal substrate having a straight grain boundary is prepared as a template. The Miller indices h1, k1, h2, k2 of the two grains of the substrate are chosen such that the misorientation angle of the film is equal to arctan k1/h1+arctan k2/h2. The film is grown on the substrate using a layer-by-layer growth mode.Type: GrantFiled: July 27, 2005Date of Patent: January 22, 2008Assignee: The Trustees of Columbia University in the City of New YorkInventor: Siu-Wai Chan
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Publication number: 20080011223Abstract: A substrate and method for growing a semi-conductive crystal on an alloy film such as (AIN)x(SiC)(1-x) without any buffer layer is disclosed. The (AIN)x(SiC)(1-x) alloy film can be formed on a SiC substrate by a vapor deposition process using AlN and SiC powder as starting materials. The (AIN)x(SiC)(1-x) alloy film provides a better lattice match for GaN or SiC epitaxial growth and reduces defects in epitaxially grown GaN with better lattice match and chemistry.Type: ApplicationFiled: July 12, 2006Publication date: January 17, 2008Inventors: Narsingh Bahadur Singh, Brian Wagner, Mike Aumer, Darren Thomson, David Kahler, Andre Berghmans, David J. Knuteson
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Patent number: 7316746Abstract: A method for a growing solid-state, spectrometer grade II-VI crystal using a high-pressure hydrothermal process including the following steps: positioning seed crystals in a growth zone of a reactor chamber; positioning crystal nutrient material in the nutrient zone of the chamber; filling the reactor with a solvent fluid; heating and pressuring the chamber until at least a portion of the nutrient material dissolves in the solvent and the solvent becomes supercritical in the nutrient zone; transporting supercritical from the nutrient zone to the growth zone, and growing the seed crystals as nutrients from the supercritical fluid deposit on the crystals.Type: GrantFiled: March 18, 2005Date of Patent: January 8, 2008Assignee: General Electric CompanyInventors: Mark Philip D'Evelyn, Dong-Sil Park, John Thomas Leman
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Patent number: 7311775Abstract: This method for heat-treating a silicon wafer includes: a step of subjecting a silicon wafer to a high-temperature heat treatment in an ambient gas atmosphere of hydrogen gas, argon gas or a mixture thereof; and a step of lowering a temperature at a rate of 2° C./min or less in a nitrogen-gas-containing ambient atmosphere in a portion or all of a process of lowering a temperature to a wafer removal temperature following said high-temperature heat treatment. This silicon wafer has a defect-free layer which is formed by a high-temperature heat treatment and is included in a surface thereof, wherein an average iron concentration in said surface is 1×1010 atoms/cm3 or less.Type: GrantFiled: August 4, 2005Date of Patent: December 25, 2007Assignee: Sumco CorporationInventors: Tatsumi Kusaba, Hidehiko Okuda, Yoshihisa Nonogaki
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Patent number: 7306675Abstract: A method for manufacturing a semiconductor substrate of the present invention includes the steps of: (a) providing a support substrate; (b) epitaxially growing a first semiconductor layer on the support substrate; (c) epitaxially growing a second semiconductor layer on the first semiconductor layer; and (d) forming a semiconductor substrate including the first semiconductor layer and the second semiconductor layer by removing the support substrate, wherein an interatomic distance of atoms of the support substrate to which atoms of the first semiconductor layer attach and an interatomic distance of atoms of the second semiconductor layer have the same magnitude relationship with respect to an interatomic distance of the atoms of the first semiconductor layer in an epitaxial growth plane.Type: GrantFiled: May 15, 2002Date of Patent: December 11, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Masaaki Yuri