Coating (e.g., Masking, Implanting) Patents (Class 117/95)
-
Patent number: 5497726Abstract: A surface acoustic wave element has a diamond layer, a piezoelectric thin film formed on the diamond layer, and a pair of electrodes for generating a surface acoustic wave having a specific wavelength and extracting the surface acoustic wave, wherein at least one electrode is a copper electrode epitaxially grown on the surface of the diamond layer. To manufacture this surface acoustic wave element, after the diamond layer is formed on a substrate by epitaxial growth, the copper electrodes each having the predetermined shape are formed on the surface of the diamond layer by epitaxial growth. Since the copper electrodes formed on the diamond layer consist of high-quality single crystal copper, resistances to electromigration and stress migrations can be increased. As a result, there is provided an excellent surface acoustic wave element free from electrical defects caused by degradation and failure of the copper electrodes or free from degradation of the electrical characteristics.Type: GrantFiled: May 11, 1994Date of Patent: March 12, 1996Assignee: Sumitomo Electric Industries, Ltd.Inventors: Shinichi Shikata, Akihiro Hachigo, Hideaki Nakahata, Kenjiro Higaki
-
Patent number: 5495823Abstract: Disclosed is a semiconductor apparatus in which a single-crystalline thin film can be formed on a semiconductor substrate at a low temperature not higher than 800.degree. C. and a method of manufacturing such a semiconductor apparatus. In this semiconductor apparatus and the manufacturing method thereof, a silane gas is supplied onto a single-crystalline silicon substrate under condition of a temperature not higher than approximately 540.degree. C. and an amorphous silicon thin film is formed on a surface of the silicon substrate. At the same time, the amorphous silicon thin film is single-crystallized to form a single crystal silicon thin film, and single crystal silicon thin films are successively epitaxially grown. This enables those single crystal silicon thin films to be formed directly on the surface of the single-crystalline silicon substrate at a temperature lower than or equal to 800.degree. C.Type: GrantFiled: July 14, 1994Date of Patent: March 5, 1996Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Kiyoteru Kobayashi
-
Patent number: 5485804Abstract: A method for creating a uniform thin film of a high surface energy material on a substrate comprising the steps of providing an oppositely charged surface on the substrate, if such does not exist, from that of particles of the high surface energy material, exposing the substrate to an aqueous colloidal suspension of particles composed of the high surface energy material to adsorb seed particles onto the surface of the substrate, and then depositing a uniform thin film of the high surface energy material by chemical vapor deposition onto the seeded substrate.Type: GrantFiled: May 17, 1994Date of Patent: January 23, 1996Assignee: University of FloridaInventors: James J. Adair, Rajiv K. Singh
-
Patent number: 5482002Abstract: A microprobe is provided which comprises a single crystal provided on a part of one main surface of a substrate or a part of a thin film formed on one main surface of the substrate. The microprobe may have a single crystal having an apex portion surrounded by facets having a specific plane direction and comprising a specific crystal face. The method for preparing the microprobe and an electronic device employing the microprobe also provided which is useful for recording and reproducing.Type: GrantFiled: July 8, 1993Date of Patent: January 9, 1996Assignee: Canon Kabushiki KaishaInventors: Hisaaki Kawade, Haruki Kawada, Kunihiro Sakai, Hiroshi Matsuda, Yuko Morikawa, Yoshihiro Yanagisawa, Tetsuya Kaneko, Toshimitsu Kawase, Hideya Kumomi, Hiroyasu Nose, Eigo Kawakami
-
Patent number: 5459097Abstract: In accordance with the invention, aluminum-containing layers are grown by molecular beam processes using as an arsenic precursor phenylarsine (PhAs). Because PhAs is more reactive than arsine and less reactive than arsenic, it decomposes selectively on III-V surfaces but not on mask materials. Thus in contrast to conventional processes, growth using PhAs permits selective growth on unmasked gallium arsenide surfaces but inhibits growth on typical mask materials such as silicon nitride.Type: GrantFiled: October 7, 1993Date of Patent: October 17, 1995Assignee: AT&T Corp.Inventors: Cammy R. Abernathy, Stephen J. Pearton, Fan Ren, Patrick W. Wisk
-
Patent number: 5432120Abstract: For producing a laterally limited, single-crystal region on a substrate, for example the collector of a bipolar transistor or the active region of a MOS transistor, a mask layer having an opening is produced on the surface of a substrate. The surface of the substrate is exposed within the opening. The cross-section of the opening parallel to the surface of the substrate at the surface of the substrate projects laterally beyond that cross-section at the surface of the mask layer. The sidewall of the opening proceeds essentially perpendicularly relative to the surface of the substrate in the region of the surface of the mask layer and has a step-shaped profile in cross-section perpendicularly relative to the surface of the substrate. The single-crystal region is formed by selective epitaxy within the opening.Type: GrantFiled: November 19, 1993Date of Patent: July 11, 1995Assignee: Siemens AktiengesellschaftInventors: Thomas Meister, Reinhard Stengl
-
Patent number: 5425808Abstract: A process for selective formation of a III-V group compound film comprises applying a compound film forming treatment, in a gas phase including a starting material for supplying the group III atoms of Periodic Table and a starting material for supplying the group V atoms of Periodic Table, on a substrate having a non-nucleation surface (S.sub.NDS) with small nucleation density and a nucleation surface (S.sub.NDL) with a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said non-nucleation surface (S.sub.NDS) and a large area sufficient for a number of nuclei to be formed, and forming selectively a III-V group compound film only on said nucleation surface (S.sub.NDL).Type: GrantFiled: October 29, 1993Date of Patent: June 20, 1995Assignee: Canon Kabushiki KaishaInventors: Hiroyuki Tokunaga, Takao Yonehara
-
Patent number: 5423286Abstract: A method for forming a crystal comprises applying a crystal growth treatment to a substrate comprising:a non-nucleation surface; anda nucleation surface constituted of an amorphous material with a higher nucleation density than said non-nucleation surface, having a sufficiently small area so as to form only a single nucleus from which a single crystal is grown, and having regular anisotropy.Also a crystal article is formed by said method for forming a crystal.Type: GrantFiled: May 19, 1994Date of Patent: June 13, 1995Assignee: Canon Kabushiki KaishaInventor: Takao Yonehara
-
Patent number: 5422306Abstract: A method is disclosed of forming semiconductor hetero interfaces that will contribute to the performance improvement of devices having semiconductor hetero interfaces such as MOS transistors, quantum devices, capacitors and the like. The method comprises the steps of making the surface of a semiconductor substrate clean and flat in terms of atomic level by heating said semiconductor substrate in vacuum to a temperature at which reconstruction of the surface atoms of said semiconductor substrate takes place, then forming a structural buffer layer such as a native oxide layer and the like on said semiconductor substrate surface after the temperature of said semiconductor substrate was lowered to room temperature and finally subjecting the semiconductor substrate with said structural buffer layer formed on its surface to a thermal treatment performed in certain specified temperature and atmosphere.Type: GrantFiled: December 15, 1992Date of Patent: June 6, 1995Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masaaki Niwa, Masaharu Udagawa, Yoshihiko Hirai, Juurou Yasui
-
Patent number: 5397428Abstract: A method and apparatus for enhancing the nucleation of diamond by pretreating a substrate by electrically biasing a diamond film adjacent the substrate while exposing the substrate and the thus biased diamond film to a carbon-containing plasma. The bias pretreatment may be maintained for a time period in the range of about 1 hour to 2 hours to achieve a high diamond nucleation density. Alternatively, the biasing may be continued until diamond film formation is indicated by a change in reflectivity of the surface of the substrate. The biasing pretreating may be used to nucleate diamond heteroepitaxially on a substrate having a surface film formed of a material having a relatively close lattice match to diamond, such as .beta.-silicon carbide. The apparatus includes a laser reflection interferometer to monitor the surface of the substrate.Type: GrantFiled: August 28, 1992Date of Patent: March 14, 1995Assignees: The University of North Carolina at Chapel Hill, North Carolina State UniversityInventors: Brian R. Stoner, Jeffrey T. Glass, William M. Hooke, Bradley E. Williams
-
Patent number: 5388548Abstract: A method of fabricating a plurality of optoelectronic components on a semiconductor substrate, each optoelectronic component comprising several layers grown in a reactor. Every layer is being grown under a predetermined individual pressure. The active layers of all the components are lying substantially at the same height. Control of the pressure in the reactor during growth allows the thickness of the layer grown to be constant or to vary over the substrate area.Type: GrantFiled: April 11, 1994Date of Patent: February 14, 1995Assignee: Interuniversitair Micro-Elektronica VZWInventors: Geert F. M. Coudenys, Piet P. A. R. Demeester
-
Patent number: 5364815Abstract: A crystal article comprises;a substrate having i) a nonnucleation surface (S.sub.NDS) having a small nucleation density, ii) at least one single-nucleation surface (S.sub.NDL -S) provided adjacent to said nonnucleation surface (S.sub.NDS), having an area small enough for a crystal to grow from only a single nucleus and having a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said nonnucleation surface (S.sub.NDS), and iii) at least one multiple-nucleation surface (S.sub.NDL -M) having an area large enough for crystals to grow from plural nuclei and having a larger nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said nonnucleation surface (S.sub.NDS);at least one monocrystal grown from said single nucleus and extending over said single-nucleation surface (S.sub.NDL -S) to cover part of said nonnucleation surface (S.sub.NDS); anda polycrystalline film grown from said plural nuclei to cover said multiple-nucleation surface.Type: GrantFiled: February 17, 1993Date of Patent: November 15, 1994Assignee: Canon Kabushiki KaishaInventor: Yoshiyuki Osada
-
Patent number: 5363800Abstract: This invention is a method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.Type: GrantFiled: November 9, 1992Date of Patent: November 15, 1994Assignee: The United States of America as represented by the United States National Aeronautics and Space AdministrationInventors: David J. Larkin, Powell, J. Anthony
-
Patent number: 5356509Abstract: A method for growing a compound semiconductor, such as GaAs or InP, on a non-lattice matched substrate, such as Si, utilizes close-spaced vapor transport to deposit nucleation enhancing interlayer and liquid phase epitaxy to form the compound semiconductor. When used in conjunction with a growth mask, the method is also adapted to selective area epitaxy.Type: GrantFiled: October 16, 1992Date of Patent: October 18, 1994Assignee: AstroPower, Inc.Inventors: Nancy Terranova, Allen M. Barnett
-
Patent number: 5356510Abstract: A method according to which a layer of a semiconductor material is made on a substrate by growth in a confinement space defined by this substrate and by a confinement layer, this growth being achieved from a seed. The cross-section of the seed, substantially perpendicular to the general direction of growth, possesses a thick central part framed by two thinned lateral parts. The confinement space has the same cross-section as the seed.Type: GrantFiled: October 6, 1992Date of Patent: October 18, 1994Assignee: Thomson-CSFInventors: Daniel Pribat, Bruno Gerard, Pierre Legagneux
-
Patent number: 5316615Abstract: The present invention broadly concerns layered structures of substantially-crystalline materials and processes for making such structures. More particularly, the invention concerns epitaxial growth of a substantially-crystalline layer of a first material on a substantially-crystalline second material different from the first material.Type: GrantFiled: March 9, 1993Date of Patent: May 31, 1994Assignee: International Business Machines CorporationInventors: Matthew W. Copel, Rudolf M. Tromp
-
Patent number: 5308444Abstract: The invention is predicated upon the discovery by applicants that exposure of a Ge surface to arsenic produces a drastic change in the step structure of the Ge surface. Subsequent exposure to Ga and growth of GaAs produces three-dimensional growth and a high threading dislocation density at the GaAs/Ge interface. However exposure of the Ge surface to Ga does not substantially change the Ge step structure, and subsequent growth of GaAs is two-dimensional with little increase in threading dislocation density. Thus a high quality semiconductor heterostructure of gallium arsenide on germanium can be made by exposing a germanium surface in an environment substantially free of arsenic, depositing a layer of gallium on the surface and then growing a layer of gallium arsenide. The improved method can be employed to make a variety of optoelectronic devices such as light-emitting diodes.Type: GrantFiled: May 28, 1993Date of Patent: May 3, 1994Assignee: AT&T Bell LaboratoriesInventors: Eugene A. Fitzgerald, Jr., Jenn-Ming Kuo, Paul J. Silverman, Ya-Hong Xie