Coating (e.g., Masking, Implanting) Patents (Class 117/95)
  • Patent number: 6406981
    Abstract: A method of coupling a single crystal semiconductor layer on a surface of a substrate comprising a polycrystalline semiconductor material such that the single crystal layer and the polycrystalline material are in direct contact.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: June 18, 2002
    Assignee: Intel Corporation
    Inventor: Kramadhati V. Ravi
  • Patent number: 6393803
    Abstract: A process for blow-molding and coating plastic containers under conditions of positive control in a close-coupled, compact machine to enhance operational efficiency. According to one of the preferred methods, the containers are coated promptly after the containers are discharged from hot molds to take advantage of the residual heat of the freshly blown containers to enhance curing/drying of the coating and to enhance bonding of the coating to the container surface. According to another one of the preferred methods, the containers are aseptically filled and capped either before or after the containers are coated. Alternatively, the process can include hot-filling and capping of containers in which the containers are coated promptly after being hot-filled to take advantage of the elevated temperature of the hot-filled containers.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: May 28, 2002
    Assignee: Graham Packaging Company, L.P.
    Inventors: Gregory J. Luka, John W. Tobias
  • Patent number: 6375738
    Abstract: A process of producing a semiconductor article is disclosed which comprises the steps of epitaxially growing on at least one surface of a single-crystal substrate a plurality of single-crystal semiconductor layers differing from each other in at least one of the kind and the concentration of an impurity, making porous the plurality of single-crystal semiconductor layers so as to form a high porosity layer and a low porosity layer, forming a non-porous single-crystal layer on a surface of the single-crystal semiconductor layer as made porous, and bonding and single-crystal substrate and a support substrate to each other, wherein the bonded single-crystal substrate and support substrate are separated at at least one of a location in the high porosity layer and an interface of the high porosity layer with a layer adjacent thereto.
    Type: Grant
    Filed: March 24, 2000
    Date of Patent: April 23, 2002
    Assignee: Canon Kabushiki Kaisha
    Inventor: Nobuhiko Sato
  • Publication number: 20020043209
    Abstract: Disclosed is a method of fabricating a compound semiconductor device, which has an Al-based compound semiconductor layer and is suitable for producing, for example, a semiconductor laser device with a buried structure. The method comprises a first step of sequentially performing vapor growth of a plurality of compound semiconductor layers including an Al-based compound semiconductor layer formed on a semiconductor substrate by using a metalorganic chemical vapor deposition (MOCVD), thereby forming a semiconductor multilayer (epitaxial layer) having, for example, a double heterostructure; a second step of selectively etching a specific compound semiconductor layer in the semiconductor multilayer other than the Al-based compound semiconductor layer in the MOCVD using a bromine-based gas, thereby forming a mesa; and a third step of regrowing a predetermined compound semiconductor layer on the semiconductor multilayer in the MOCVD following the etching step.
    Type: Application
    Filed: August 27, 2001
    Publication date: April 18, 2002
    Applicant: The Furukawa Electric Co., Ltd.
    Inventors: Satoshi Arakawa, Akihiko Kasukawa
  • Patent number: 6372041
    Abstract: A method and apparatus for homoepitaxial growth of freestanding, single bulk crystal Gallium Nitride (GaN) are provided, wherein a step of nucleating GaN in a reactor results in a GaN nucleation layer having a thickness of a few monolayers. The nucleation layer is stabilized, and a single bulk crystal GaN is grown from gas phase reactants on the GaN nucleation layer. The reactor is formed from ultra low oxygen stainless steel.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: April 16, 2002
    Assignee: GAN Semiconductor Inc.
    Inventors: Hak Dong Cho, Sang Kyu Kang
  • Patent number: 6358313
    Abstract: A method of manufacturing a crystalline silicon base semiconductor thin film on a substrate, includes the steps of forming a thin film primarily made of silicon on the substrate by forming plasma of a film material gas containing at least a silicon base gas at the vicinity of the substrate; and crystallizing the silicon in the thin film primarily made of the silicon by emitting excited particles produced from an excited particle material gas to the substrate. At least one of the film material gas and the excited particle material gas contains an impurity gas for forming the silicon semiconductor, and thereby the crystalline silicon base semiconductor thin film is formed on the substrate.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: March 19, 2002
    Assignees: Sharp Kabushiki Kaisha, Nissin Electric Co., Ltd.
    Inventors: Shuhei Tsuchimoto, Hirohisa Tanaka, Kiyoshi Ogata, Hiroya Kirimura
  • Patent number: 6336970
    Abstract: A surface preparation method and semiconductor device constituted so as to enable the prevention of carrier accumulation resulting from Si acting as a donor, without making the constitution of a semiconductor manufacturing apparatus complex. When forming an epitaxial layer either on the surface of a substrate, or on the surface of a base layer, Si or an Si compound that exists on the surface of a substrate, or on the surface of a base layer, is removed in accordance with a thermal cleaning process that uses an As hydride gas as the cleaning gas.
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: January 8, 2002
    Assignee: Dowa Mining Co., Ltd.
    Inventors: Ryo Sakamoto, Ryuichi Toba, Hiroyuki Ikeda
  • Patent number: 6331209
    Abstract: An easy method of forming purified carbon nanotubes from which graphitic phase or carbon particles are removed, using a high-density plasma. Carbon nanotubes are grown on a substrate using a plasma chemical vapor deposition method at a high plasma density of 1011 cm−3 or more. The carbon nanotube formation includes: growing a carbon nanotube layer on a substrate to have a predetermined thickness by plasma deposition; purifying the carbon nanotube layer by plasma etching; and repeating the growth and the purification of the carbon nanotube layer. For the plasma etching, a halogen-containing gas, for example, a carbon tetrafluoride gas, is used as a source gas.
    Type: Grant
    Filed: April 21, 2000
    Date of Patent: December 18, 2001
    Assignees: Iljin Nanotech Co., Ltd.
    Inventors: Jin Jang, Suk-jae Chung
  • Publication number: 20010047751
    Abstract: A method of forming a semiconductor structure including providing a single crystal semiconductor substrate of GaP, and fabricating a graded composition buffer including a plurality of epitaxial semiconductor Inx(AlyGa1-y)1-xP alloy layers. The buffer includes a first alloy layer immediately contacting the substrate having a lattice constant that is nearly identical to that of the substrate, subsequent alloy layers having lattice constants that differ from adjacent layers by less than 1%, and a final alloy layer having a lattice constant that is substantially different from the substrate. The growth temperature of the final alloy layer is at least 20° C. less than the growth temperature of the first alloy layer.
    Type: Application
    Filed: November 24, 1999
    Publication date: December 6, 2001
    Inventors: ANDREW Y. KIM, EUGENE A. FITZGERALD
  • Patent number: 6325850
    Abstract: The invention concerns a method for producing a gallium nitride (GaN) epitaxial layer characterised in that it consists in depositing on a substrate a dielectric layer acting as a mask and depositing on the masked gallium nitride, by epitaxial deposit, so as to induce the deposit of gallium nitride patterns and the anisotropic lateral growth of said patterns, the lateral growth being pursued until the different patterns coalesce. The deposit of the gallium nitride patterns can be carried out ex-situ by dielectric etching or in-situ by treating the substrate for coating it with a dielectric film whereof the thickness is of the order of one angstrom. The invention also concerns the gallium nitride layers obtained by said method.
    Type: Grant
    Filed: July 7, 2000
    Date of Patent: December 4, 2001
    Assignee: Centre National de la Recherché Scientifique (CNRS)
    Inventors: Bernard Beaumont, Pierre Gibart, Jean-Claude Guillaume, Gilles Nataf, Michel Vaille, Soufien Haffouz
  • Patent number: 6315826
    Abstract: Disclosed are a structure of a semiconductor substrate and a method of manufacturing the semiconductor substrate preventing a reduction of gettering capability due to a high-temperature heat treatment. In a semiconductor substrate containing a highly concentrated impurity having a polysilicon layer to be a gettering site on a rear surface side and an epitaxial layer 6 on a front surface side, an impurity concentration is lower near the rear and front surfaces and higher at the center in a cross section of the semiconductor substrate. The method of manufacturing the semiconductor substrate comprises the steps of: performing the heat treatment of a silicon substrate at a temperature of 1100° C. or more and a melting temperature or less of the silicon substrate before forming the polysilicon layer 4 and the epitaxial layer 6; forming the polysilicon layer 4 on the rear surface side of the silicon substrate; and forming the epitaxial layer 6 on the front surface side of the silicon substrate.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: November 13, 2001
    Assignee: NEC Corporation
    Inventor: Satoru Muramatsu
  • Patent number: 6306213
    Abstract: An electro-optical device and a method for manufacturing the same are disclosed. The device comprises a pair of substrates and an electro-optical modulating layer (e.g. a liquid crystal layer having sandwiched therebetween, said pair of substrates consisting of a first substrate having provided thereon a plurality of gate wires, a plurality of source (drain) wires, and a pixel matrix comprising thin film transistors, and a second substrate facing the first substrate, wherein, among the peripheral circuits having established on the first substrate and being connected to the matrix wirings for the X direction and the Y direction, only a part of said peripheral circuits is constructed from thin film semiconductor devices fabricated by the same process utilized for an active device, and the rest of the peripheral circuits is constructed from semiconductor chips.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: October 23, 2001
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 6296701
    Abstract: The present invention provides a biaxially textured laminate article having a polycrystalline biaxially textured metallic substrate with an electrically conductive oxide layer epitaxially deposited thereon and methods for producing same. In one embodiment a biaxially texture Ni substrate has a layer of LaNiO3 deposited thereon. An initial layer of electrically conductive oxide buffer is epitaxially deposited using a sputtering technique using a sputtering gas which is an inert or forming gas. A subsequent layer of an electrically conductive oxide layer is then epitaxially deposited onto the initial layer using a sputtering gas comprising oxygen. The present invention will enable the formation of biaxially textured devices which include HTS wires and interconnects, large area or long length ferromagnetic and/or ferroelectric memory devices, large area or long length, flexible light emitting semiconductors, ferroelectric tapes, and electrodes.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: October 2, 2001
    Assignee: UT-Battelle, LLC
    Inventors: David K. Christen, Qing He
  • Patent number: 6294018
    Abstract: The specification describes a lithographic technique in which alignment marks are defined in a first semiconductor layer and the alignment marks are then covered with a protective SiO2 layer. After subsequent semiconductor layer growth steps, which selectively deposit on the former semiconductor layer but not on the protective layer, the alignment marks remain undistorted and visible to the exposure tool for subsequent processing.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: September 25, 2001
    Assignee: Lucent Technologies
    Inventors: Robert Alan Hamm, Rose Fasano Kopf, Christopher James Pinzone, Robert William Ryan, Alaric Tate
  • Patent number: 6280523
    Abstract: Light emitting devices having a vertical optical path, e.g. a vertical cavity surface emitting laser or a resonant cavity light emitting or detecting device, having high quality mirrors may be achieved using wafer bonding or metallic soldering techniques. The light emitting region interposes one or two reflector stacks containing dielectric distributed Bragg reflectors (DBRs). The dielectric DBRs may be deposited or attached to the light emitting device. A host substrate of GaP, GaAs, InP, or Si is attached to one of the dielectric DBRs. Electrical contacts are added to the light emitting device.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: August 28, 2001
    Assignee: LumiLeds Lighting, U.S., LLC
    Inventors: Carrie Carter Coman, Fred A. Kish, Jr., R. Scott Kern, Michael R. Krames, Paul S. Martin
  • Publication number: 20010015170
    Abstract: A method for manufacturing a device of silicon carbide (SiC) and a single crystal thin film, which are wide band gap semiconductor materials and can be applied to semiconductor devices such as high power devices, high temperature devices, and environmentally resistant devices, is provided by heating a silicon carbide crystal in an oxygen atmosphere to form a silicon (di)oxide thin film on a silicon carbide crystal surface, and etching the silicon (di)oxide thin film formed on the silicon carbide crystal surface to prepare a clean SiC surface. The above SiC device comprises a clean surface having patterned steps and terraces, has a surface defect density of 108 cm−2 or less, or has at least a layered structure in which an n-type silicon carbide crystal is formed on an n-type Si substrate surface.
    Type: Application
    Filed: January 2, 2001
    Publication date: August 23, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Makoto Kitabatake
  • Patent number: 6277194
    Abstract: A method of removing contaminants from a surface in a silicon substrate processing chamber. The method includes coating the surface which has been exposed to contaminants including metal particles with a material preferably including silicon. During coating, contaminants are collected by the material being applied. The method further includes removing the material and any contaminants that have been collected by the material during coating. The method can be performed after the surface has been exposed to contaminants from ambient air or moisture during cleaning or preventive maintenance procedures, for example. Also, the method is preferably performed before any baking procedures or before the chamber is heated to drive out any moisture that has been introduced to the chamber.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: August 21, 2001
    Assignee: Applied Materials, Inc.
    Inventors: AnnaLena Thilderkvist, Paul B. Comita, Ann P. Waldhauer
  • Patent number: 6273950
    Abstract: A method for manufacturing a device of silicon carbide (SiC) and a single crystal thin film, which are wide band gap semiconductor materials and can be applied to semiconductor devices such as high power devices, high temperature devices, and environmentally resistant devices, is provided by heating a silicon carbide crystal in an oxygen atmosphere to form a silicon (di)oxide thin film on a silicon carbide crystal surface, and etching the silicon (di)oxide thin film formed on the silicon carbide crystal surface to prepare a clean SiC surface. The above SiC device comprises a clean surface having patterned steps and terraces, has a surface defect density of 108 cm−2 or less, or has at least a layered structure in which an n-type silicon carbide crystal is formed on an n-type Si substrate surface.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: August 14, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Makoto Kitabatake
  • Patent number: 6273949
    Abstract: A method for fabricating gallium arsenide (GaAs) based structure groups with inverted crystallographic orientation to form wavelength converters that utilizes germanium as a crystallographic neutral template layer deposited on a GaAs substrate. A crystallographic inverted gallium arsenide layer is grown on top of the template layer. In a selective trench etching process areas of the substrate are exposed again for a consecutive collective deposition of GaAs.
    Type: Grant
    Filed: September 10, 1999
    Date of Patent: August 14, 2001
    Assignee: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Loren A. Eyres, Martin M. Fejer, Christopher B. Ebert, James S. Harris
  • Patent number: 6270573
    Abstract: A silicon carbide thin film is epitaxially grown by an MBE or the like method with silicon atoms 2 being maintained to be in excess of carbon atoms on a growth surface 1a of a silicon carbide crystal in a substrate 1. A silicon carbide substrate with a good crystallinity is thereby achieved at a low temperature with a good reproducibility. This crystal growth is possible at a low temperature of 1300° C. or lower, and the productions of a high-concentration doped film, a selectively grown film, and a grown film of a cubic silicon carbide on a hexagonal crystal are achieved. In crystallizing a cubic silicon carbide on a hexagonal crystal, the use of an off-cut surface inclined towards a <1{overscore (1)}00> direction is effective to prevent an occurrence of twin.
    Type: Grant
    Filed: April 26, 1999
    Date of Patent: August 7, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Makoto Kitabatake, Masao Uchida, Kunimasa Takahashi
  • Patent number: 6267817
    Abstract: The invention encompasses methods of treating semiconductive material wafers and ingots to alleviate slippage within monocrystalline lattices of the wafers and ingots. The invention further encompasses monocrystalline semiconductive material wafers and monocrystalline semiconductive ingots which are treated to alleviate slippage within a crystalline lattice of the wafers and ingots. In one aspect, the invention includes a method of forming a semiconductive material wafer comprising: a) forming an ingot of semiconductive material, said ingot comprising an outer periphery; b) forming a wafer from the ingot, the wafer comprising said outer periphery; and c) doping said outer periphery with strength-enhancing dopant atoms.
    Type: Grant
    Filed: April 12, 2000
    Date of Patent: July 31, 2001
    Assignee: Micron Technology, Inc.
    Inventor: Fernando Gonzalez
  • Publication number: 20010007242
    Abstract: A gallium nitride semiconductor layer is fabricated by masking an underlying gallium nitride layer with a mask that includes an array of openings therein, and growing the underlying gallium nitride layer through the array of openings and onto the mask, to thereby form an overgrown gallium nitride semiconductor layer. Although dislocation defects may propagate vertically from the underlying gallium nitride layer to the grown gallium nitride layer through the mask openings, the overgrown gallium nitride layer is relatively defect free. The overgrown gallium nitride semiconductor layer may be overgrown until the overgrown gallium nitride layer coalesces on the mask, to form a continuous overgrown monocrystalline gallium nitride semiconductor layer. The gallium nitride semiconductor layer may be grown using metalorganic vapor phase epitaxy. Microelectronic devices may be formed in the overgrown gallium nitride semiconductor layer.
    Type: Application
    Filed: February 9, 2001
    Publication date: July 12, 2001
    Inventors: Robert F. Davis, Ok-Hyun Nam, Tsvetanka Zheleva, Michael D. Bremser
  • Patent number: 6254676
    Abstract: A method for manufacturing a metal oxide semiconductor transistor having a raised source/drain is described. A first spacer is formed on a sidewall of a gate electrode. An epitaxial layer is then formed on the exposed surface of the substrate and a top surface of the gate electrode. A light implantation step is then performed on the substrate while using the gate electrode and the first spacer as a first mask. Thereafter, a second spacer is formed on the sidewall of the gate electrode. A heavy implantation step is then performed on the substrate while using the gate electrode, the first spacer and the second spacer as a second mask. The epitaxial layer is then formed before the forming of the extension structure of the source/drain. Therefore, dopants in a source/drain extension structure avoid suffering the high temperature needed to form the epitaxial layer so that the redistribution of the dopants is prevented.
    Type: Grant
    Filed: June 28, 1999
    Date of Patent: July 3, 2001
    Assignee: United Microelectronics Corp.
    Inventors: Gwo-Shii Yang, Michael W C Huang, Chien Chao Huang, Hsien-Ta Chung, Tri-Rung Yew
  • Patent number: 6251183
    Abstract: The invention provides a process for depositing an epitaxial layer on a crystalline substrate, comprising the steps of providing a chamber having an element capable of heating, introducing the substrate into the chamber, heating the element at a temperature sufficient to decompose a source gas, passing the source gas in contact with the element; and forming an epitaxial layer on the substrate.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: June 26, 2001
    Assignee: Midwest Research Institute
    Inventors: Eugene Iwancizko, Kim M. Jones, Richard S. Crandall, Brent P. Nelson, Archie Harvin Mahan
  • Publication number: 20010003269
    Abstract: A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. For example, a cantilever can be made of this etch-stop material system, then released from its substrate and surrounding material, i.e., “micromachined”, by exposure to one of these etchants. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e.
    Type: Application
    Filed: April 9, 1999
    Publication date: June 14, 2001
    Inventors: KENNETH C. WU, EUGENE A. FITZGERALD, JEFFREY T. BORENSTEIN
  • Patent number: 6214108
    Abstract: Micropipe defects existing in a silicon carbide single crystal are closed within the single crystal. At least a portion of the micropipe defects opened on the surface of the silicon carbide single crystal (SiC substrate) is sealed up with a coating material. Then heat treatment is performed so as to saturate the inside of the micropipe defects with silicon carbide vapors. By this, the micropipe defects existing in the SiC substrate can be closed within the SiC substrate, not in a newly grown layer. Further, the micropipe defects can be efficiently closed by filling the micropipe defects with a silicon carbide material by preliminarily using super critical fluid and the like.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: April 10, 2001
    Assignees: Kabushiki Kaisha Toyota Chuo Kenkyusho, Denso Corporation
    Inventors: Atsuto Okamoto, Naohiro Sugiyama, Toshihiko Tani, Nobuo Kamiya, Hiroaki Wakayama, Yoshiaki Fukushima, Kazukuni Hara, Fusao Hirose, Shoichi Onda, Kunihiko Hara, Takashi Onoda, Haruyoshi Kuriyama, Takeshi Hasegawa
  • Patent number: 6214107
    Abstract: A method for manufacturing a device of silicon carbide (SiC) and a single crystal thin film, which are wide band gap semiconductor materials and can be applied to semiconductor devices such as high power devices, high temperature devices, and environmentally resistant devices, is provided by heating a silicon carbide crystal in an oxygen atmosphere to form a silicon (di)oxide thin film on a silicon carbide crystal surface, and etching the silicon (di)oxide thin film formed on the silicon carbide crystal surface to prepare a clean SiC surface. The above SiC device comprises a clean surface having patterned steps and terraces, has a surface defect density of 108 cm−2 or less, or has at least a layered structure in which an n-type silicon carbide crystal is formed on an n-type Si substrate surface.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: April 10, 2001
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Makoto Kitabatake
  • Patent number: 6176925
    Abstract: An n-doped, high quality gallium nitride substrate suitable for further device or epitaxial processing, and method for making the same. The nitride substrate is produced by epitaxial deposition of first metal nitride layer on a non-native substrate followed by a second deposition of metal nitride. During the second deposition of metal nitride, a liquid metal layer is formed at the interface of the non-native substrate and the metal nitride layer form. The formed metal nitride layer may be detached from the non-native substrate to provide an metal nitride substrate with a high quality inverse surface. A epitaxial metal nitride layer may be deposited on the inverse surface of metal nitride substrate. The metal nitride substrate and the epitaxial metal nitride layer thereon may be deposited using the same hydride vapor-phase epitaxy system.
    Type: Grant
    Filed: May 7, 1999
    Date of Patent: January 23, 2001
    Assignees: CBL Technologies, Inc., Matsushita Electronics Corporation
    Inventors: Glenn S. Solomon, David J. Miller, Tetsuzo Ueda
  • Patent number: 6171966
    Abstract: An improved delineation pattern for epitaxial depositions is created by forming a mask on a single-crystal silicon substrate which leaves an area (10) of the substrate exposed, doping the area with a dopant to create a doped region defined by a periphery, anisotropically, vertically etching the doped region to create a delineation pattern corresponding to the periphery, and then forming an epitaxial layer over the substrate and doped region. The periphery of the delineation pattern has a squared-off delineation step including a first step wall generally perpendicular to the surface of the substrate and a second step wall generally parallel to the surface of the substrate. The squared-off delineation step helps prevent wash-out of the delineation pattern as one or more epitaxial layers are deposited on the substrate.
    Type: Grant
    Filed: August 15, 1996
    Date of Patent: January 9, 2001
    Assignee: Applied Materials, Inc.
    Inventors: Thomas E. Deacon, Norma B. Riley
  • Patent number: 6165264
    Abstract: The invention provides a method for selective growth of semiconductor crystals, including the step of forming a semiconductor layer in a selected region of a semiconductor substrate by using a mask, the semiconductor layer being controlled with respect to atomic ordering or natural super lattice (NSL). It is possible by the invention to control the energy gap, optical anisotropy and electrically conductive anisotropy of a semiconductor layer, and also possible by the invention to carry out two-dimensional control of material properties in a substrate in accordance with a pattern of a mask.
    Type: Grant
    Filed: February 19, 1997
    Date of Patent: December 26, 2000
    Assignee: NEC Corporation
    Inventors: Kikuo Makita, Akiko Gomyo
  • Patent number: 6162293
    Abstract: A method for manufacturing a ferroelectric thin film having a layered perovskite crystal structure of the general formula: Bi.sub.2 A.sub.m-1 B.sub.m O.sub.3m+3, wherein A is selected from the group consisting of Na.sup.1+, K.sup.1+, Pb.sup.2+, Ca.sup.2+, Sr.sup.2+, Ba.sup.2+ and Bi.sup.3+, B is selected from the group consisting of Fe.sup.3+, Ti.sup.4+, Nb.sup.5+, Ta.sup.5+, W.sup.6+ and Mo.sup.6+, and m represents an integer of 1 or larger, which comprises introducing into a film formation chamber where a substrate is set, gaseous starting materials inclusive of oxygen gas for forming the ferroelectric thin film in which the flow rate of oxygen gas as one component of the gaseous starting materials is controlled to an arbitrary value necessary for the formation of the ferroelectric thin film having a desired orientation while the pressure inside the film formation chamber and the total flow rate of the gaseous starting materials and an optionally introduced carrier gas are maintained constant.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: December 19, 2000
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takeshi Kijima, Akira Okutoh, Maho Ushikubo, Hironori Matsunaga
  • Patent number: 6153010
    Abstract: A method of growing a nitride semiconductor crystal which has very few crystal defects and can be used as a substrate is disclosed. This invention includes the step of forming a first selective growth mask on a support member including a dissimilar substrate having a major surface and made of a material different from a nitride semiconductor, the first selective growth mask having a plurality of first windows for selectively exposing the upper surface of the support member, and the step of growing nitride semiconductor portions from the upper surface, of the support member, which is exposed from the windows, by using a gaseous Group 3 element source and a gaseous nitrogen source, until the nitride semiconductor portions grown in the adjacent windows combine with each other on the upper surface of the selective growth mask.
    Type: Grant
    Filed: December 9, 1998
    Date of Patent: November 28, 2000
    Assignee: Nichia Chemical Industries Ltd.
    Inventors: Hiroyuki Kiyoku, Shuji Nakamura, Tokuya Kozaki, Naruhito Iwasa, Kazuyuki Chocho
  • Patent number: 6146457
    Abstract: A method for producing thick, high quality GaN substrates uses an epitaxially deposited film is used as a substrate material for further device or epitaxial processing. The film is deposited using an epitaxial technique on a thin substrate called the disposable substrate. The deposited film is thick enough so that upon cooling the thermal mismatched strain is relieved through cracking of the lower disposable substrate and not the newly deposited epitaxy. The epitaxial film now becomes a platform for either further epitaxial deposition or device processing.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: November 14, 2000
    Assignee: CBL Technologies, Inc.
    Inventor: Glenn S. Solomon
  • Patent number: 6123767
    Abstract: A liquid raw material is heated to its boiling point or higher at a vaporizer to mix the vaporized ingredient gas and a carrier gas at a mixer at predetermined concentrations. The flow of the mixed gas is adjusted while the mixed gas is heated to over its condensing point and the temperature thereof is kept. Subsequently, the mixed gas is fed to a reactor for epitaxial growth while the mixed gas is heated to over its condensing point and the temperature thereof is kept. When the temperature of a heating medium is kept constant at the vaporizer to vaporize the liquid raw material and the feeding amount of the liquid into the vaporizer is adjusted by the pressure of the gas inside the vaporizer, the liquid surface level can be controlled to be constant.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: September 26, 2000
    Assignees: Mitsubishi Materials Silicon Corporation, Mitsubishi Materials Polycrystalline Silicon Corporation
    Inventors: Yoshiharu Toyama, Akikazu Kuroda, Tokuji Kiyama, Sumio Kida, Shunji Yoshida, Takashi Yamamoto, Tetsuya Atsumi
  • Patent number: 6113685
    Abstract: An improved method for growing a first layer on a second layer in which the first and second layers have different thermal indices of expansion and/or a mismatch of the lattice constants and the deposition being carried out at a temperature above ambient. The first layer includes a material that decomposes upon beating above a decomposition temperature. One of the first and second layers absorbs light in a first frequency range and the other of the first and second layers is transparent to the light in the first frequency range. In the method of the present invention, the one of the first and second layers that absorbs light in the first frequency range is exposed to light in the first frequency range by passing the light through the other of the first and second layers. This exposure heats the first layer to a temperature above the decomposition temperature at the interface of the first and second layers after the first layer has been deposited on the second layer.
    Type: Grant
    Filed: September 14, 1998
    Date of Patent: September 5, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Shih-Yuan Wang, Yong Chen
  • Patent number: 6114287
    Abstract: The present invention provides methods and biaxially textured articles having a deformed epitaxial layer formed therefrom for use with high temperature superconductors, photovoltaic, ferroelectric, or optical devices. A buffer layer is epitaxially deposited onto biaxially-textured substrates and then mechanically deformed. The deformation process minimizes or eliminates grooves, or other irregularities, formed on the buffer layer while maintaining the biaxial texture of the buffer layer. Advantageously, the biaxial texture of the buffer layer is not altered during subsequent heat treatments of the deformed buffer. The present invention provides mechanical densification procedures which can be incorporated into the processing of superconducting films through the powder deposit or precursor approaches without incurring unfavorable high-angle grain boundaries.
    Type: Grant
    Filed: September 30, 1998
    Date of Patent: September 5, 2000
    Assignee: UT-Battelle, LLC
    Inventors: Dominic F. Lee, Donald M. Kroeger, Amit Goyal
  • Patent number: 6110278
    Abstract: A template for seeding growth of a desired single-crystal material (e.g., Si, GaAs) is created by passing through a monocrystalline channelizing mask, in a channelizing direction thereof, at least one of a nucleation-friendly species (e.g., Si, Ga) and a knock-off species (e.g., Ar, F) for respective implant of a nucleation-friendly species within or removal of a nucleation-unfriendly material (e.g., SiO.sub.2) of a supplied substrate. The desired single-crystal material is then grown in epitaxial-like manner from the thus-formed seeding-template. In one embodiment, silicon ions are projected through a monocrystalline silicon mask of a selected crystal orientation ((100), or (111)) in its channelizing direction so as to implant the silicon ions in a silicon dioxide layer of a supplied substrate according to the selected crystal orientation of the channelizing mask. Monocrystalline silicon is then epitaxially grown on top of the silicon dioxide layer with the same crystal orientation.
    Type: Grant
    Filed: August 10, 1998
    Date of Patent: August 29, 2000
    Inventor: Arjun N. Saxena
  • Patent number: 6110277
    Abstract: A process for the fabrication on a monocrystal silicon substrate of epitaxial layers of a III-V nitride compound semi-conductor having the structure In.sub.x Al.sub.y Ga.sub.1-x-y N (0.ltoreq.x, 0.ltoreq.y, x+y.ltoreq.1). The process consists of the following steps. A parcel-like structure is created on the surface of a monocrystal silicon substrate. The silicon surface within the parcels is uncovered and the edges of the parcels are covered by a masking material. By means of epitaxial growth of the nitride compound semiconductor exclusively within the parcels on the silicon surface, local islands are created on whose edges the dislocations generated by the lattice mismatches are able to break down. Finally, components are fabricated in and on the parcels.
    Type: Grant
    Filed: April 14, 1998
    Date of Patent: August 29, 2000
    Assignee: Temic Telefunken microelectronic GmbH
    Inventor: Matthias Braun
  • Patent number: 6103072
    Abstract: A piezoelectric thin-film device includes: a substrate; and a piezoelectric thin film formed on the substrate, wherein a thickness of the piezoelectric thin film is 1 to 10 .mu.m, a crystal grain size of the piezoelectric thin film is 0.05 to 1 .mu.m, and a surface roughness (Rmax) of the piezoelectric thin film is no more than 1 .mu.m.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: August 15, 2000
    Assignee: Seiko Epson Corporation
    Inventors: Tsutomu Nishiwaki, Kouji Sumi, Masami Murai, Masato Shimada
  • Patent number: 6103009
    Abstract: A process for fabricating a SOI substrate efficiently removes a non-porous Si region on a porous Si region, and solves the problem of etching of glass substrates and the problem that a relatively thick porous Si region is necessary.
    Type: Grant
    Filed: December 9, 1996
    Date of Patent: August 15, 2000
    Assignee: Canon Kabushiki Kaisha
    Inventor: Tadashi Atoji
  • Patent number: 6103019
    Abstract: A method for producing a pattern of regularly spaced-apart nucleation sites and corresponding devices are disclosed. The method enables formation of a device having an amorphous or otherwise non-single crystal surface from which single crystal layers of a desired orientation may be grown using the regularly spaced nucleation sites as a growth template. The method can be used to produce a single crystal semiconductor layer of a desired orientation (e.g., <100> or <111>) on an amorphous insulating layer (e.g. of SiO.sub.2 or Si.sub.3 N.sub.4). For example, single crystal Si of a <100> orientation may be grown on an SiO.sub.2 layer. Monocrystalline semiconductor films may be similarly grown on amorphous glass substrates or the like for producing solar cells of high efficiency and low cost.
    Type: Grant
    Filed: February 18, 1998
    Date of Patent: August 15, 2000
    Inventor: Arjun Saxena
  • Patent number: 6074478
    Abstract: A flat selective silicon epitaxial thin film in which facet formation and loading effect are suppressed is grown by using a conventional LPCVD system which does not require an ultrahigh vacuum environment. Raw material gases for film formation and atomic hydrogen formed in an atomic hydrogen formation chamber 2 installed separately from a reaction chamber is introduced into the reaction chamber, at a growth temperature in the range of 750-900.degree. C. and under a reaction chamber pressure in the range of 1-30 Torr.
    Type: Grant
    Filed: January 14, 1998
    Date of Patent: June 13, 2000
    Assignee: NEC Corporation
    Inventor: Shizuo Oguro
  • Patent number: 6059879
    Abstract: The invention encompasses methods of treating semiconductive material wafers and ingots to alleviate slippage within monocrystalline lattices of the wafers and ingots. The invention further encompasses monocrystalline semiconductive material wafers and monocrystalline semiconductive ingots which are treated to alleviate slippage within a crystalline lattice of the wafers and ingots. In one aspect, the invention includes a method of forming a semiconductive material wafer comprising: a) forming an ingot of semiconductive material, said ingot comprising an outer periphery; b) forming a wafer from the ingot, the wafer comprising said outer periphery; and c) doping said outer periphery with strength-enhancing dopant atoms.
    Type: Grant
    Filed: August 22, 1997
    Date of Patent: May 9, 2000
    Assignee: Micron Technology, Inc.
    Inventor: Fernando Gonzalez
  • Patent number: 6046465
    Abstract: A buried reflector 50 in an epitaxial lateral growth layer forms a part of a light emitting device and allows for the fabrication of a semiconductor material that is substantially low in dislocation density. The laterally grown material is low in dislocation defect density where it is grown over the buried reflector making it suitable for high quality optical light emitting devices, and the embedded reflector eliminates the need for developing an additional reflector.
    Type: Grant
    Filed: April 17, 1998
    Date of Patent: April 4, 2000
    Assignee: Hewlett-Packard Company
    Inventors: Shih-Yuan Wang, Yong Chen, Scott W. Corzine, R. Scott Kern, Carrie C. Coman, Michael R. Krames, Frederick A. Kish, Jr., Yawara Kaneko
  • Patent number: 6036772
    Abstract: A method for making a semiconductor device comprises: depositing at least one Group II-VI compound semiconductor layer comprising at least one Group II element selected from the group consisting of zinc, magnesium, manganese, beryllium, cadmium and mercury and at least one Group VI element selected from the group consisting of oxygen, sulfur, selenium and tellurium onto a Group III-V compound semiconductor layer comprising at least one Group III element selected from the group consisting of gallium, aluminum, boron and indium and at least one Group V element selected from the group consisting of nitrogen, phosphorus, arsenic, antimony and bismuth; whereinbefore depositing the Group II-VI compound semiconductor layer, a particle beam composed of at least one Group II element selected from the group consisting of zinc, magnesium, beryllium, cadmium and mercury is radiated onto the Group III-V compound semiconductor layer in a dose of 8.times.10.sup.-4 Torr.multidot.sec or more.
    Type: Grant
    Filed: December 29, 1997
    Date of Patent: March 14, 2000
    Assignee: Sony Corporation
    Inventors: Tomonori Hino, Satoshi Taniguchi, Satoshi Ito
  • Patent number: 6030661
    Abstract: A method for epitaxially growing objects of SiC, a Group III-nitride or alloys thereof by Chemical Vapor Deposition on a substrate received in a susceptor having circumferential walls, the method comprises heating the circumferential susceptor walls, and thereby the substrate and a gas mixture led to the substrate for the growth, above a temperature level at which sublimination of the material grown starts to considerably increase, and feeding the gas mixture into the susceptor with a composition and at a rate that ensures a positive growth.
    Type: Grant
    Filed: August 25, 1997
    Date of Patent: February 29, 2000
    Assignees: ABB Research Ltd., Okmetic Ltd.
    Inventors: Olle Kordina, Christer Hallin, Erik Janzen
  • Patent number: 6024794
    Abstract: By applying the method, the critical film thickness of a compound semiconductor layer is determined, and a semiconductor device having a compound semiconductor layer with an optimized film thickness excellent in emitting performance is manufactured.The relationship between film thickness of a compound semiconductor layer and photoluminescence (PL) corresponding to the film thickness is obtained by measurement, the film thickness where PL exhibits a peak is designated as critical film thickness. The semiconductor layer comprises II-VI group compound semiconductor layer containing at least cadmium. The relationship between the critical film thickness and cadmium composition ratio is obtained by measurement. An equation which approximates the relationship between the critical film thickness and cadmium composition ratio is formulated.
    Type: Grant
    Filed: September 18, 1997
    Date of Patent: February 15, 2000
    Assignee: Sony Corporation
    Inventors: Koshi Tamamura, Hironori Tsukamoto, Masaharu Nagai
  • Patent number: 6007623
    Abstract: A method for producing a horizontal magnetic recording medium that has as its magnetic film a granular film with grains of a chemically-ordered FePt or FePtX (or CoPt or CoPtX) alloy in the tetragonal L1.sub.0 structure uses an etched seed layer beneath the granular film. The granular magnetic film reveals a very high magnetocrystalline anisotropy within the individual grains. The film is produced by sputtering from a single alloy target or cosputtering from several targets. The granular structure and the chemical ordering are controlled by means of sputter parameters, e.g., temperature and deposition rate, and by the use of the etched seed layer that provides a structure for the subsequently sputter-deposited granular magnetic film. The structure of the seed layer is obtained by sputter etching, plasma etching, ion irradiation, or laser irradiation. The magnetic properties, i.e., H.sub.c and areal moment density M.sub.
    Type: Grant
    Filed: August 29, 1997
    Date of Patent: December 28, 1999
    Assignee: International Business Machines Corporation
    Inventors: Jan-Ulrich Thiele, Dieter Klaus Weller
  • Patent number: 6007624
    Abstract: A method for controlling the autodoping during epitaxial silicon deposition. First, the substrate (10) is cleaned to remove any native oxide. After being cleaned, the substrate (10) is transferred to the deposition chamber in an inert or vacuum atmosphere to inhibit the growth of a native oxide on the surface of the wafers. A lower temperature (i.e., 500-850.degree. C.) capping layer (14) is deposited to prevent autodoping. Then, the temperature is increased to the desired deposition temperature and the remainder of the epitaxial layer (18) is deposited.
    Type: Grant
    Filed: August 30, 1996
    Date of Patent: December 28, 1999
    Assignee: Texas Instruments Incorporated
    Inventor: Rick L. Wise
  • Patent number: 5993770
    Abstract: An SiC film having an excellent strength and thermal characteristics. The SiC film is prepared by a CVD process (i.e. CVD-SiC fabrication) and has a thermal conductivity along the direction of the SiC crystal growth between 100 and 300 W/m.multidot.K, and an average grain diameter of the internal structure between 4 to 12 .mu.m. It is preferred that the ratio of the thermal conductivity along the direction of the SiC crystal growth to the thermal conductivity in the perpendicular direction is in a range of 1.10 to 1.40.
    Type: Grant
    Filed: August 26, 1998
    Date of Patent: November 30, 1999
    Assignee: Tokai Carbon Company, Ltd.
    Inventors: Akihiro Kuroyanagi, Tomiya Yasunaka, Yuji Ushijima, Kenichi Kanai