Coating (e.g., Masking, Implanting) Patents (Class 117/95)
  • Patent number: 5993544
    Abstract: A non-linear optical thin film layer system (10) is provided for integrated optics applications where a non-linear optical thin film layer (18) is integrated with a gallium-arsenide substrate (12). A first encapsulating layer (20) is deposited on lower surface (26), peripheral sides (30), and an upper surface peripheral region (28) of said gallium-arsenide substrate (12). A second encapsulating and buffer layer (14) is epitaxially grown on an upper surface of said gallium-arsenide substrate (12) and on the encapsulated upper surface peripheral region (28) of said gallium-arsenide substrate (12). A perovskite layer (16) is epitaxially grown on an upper surface of the layer (14). A non-linear optical thin film layer (18) is epitaxially grown on an upper surface of the perovskite layer (16) and is lattice matched to this layer.
    Type: Grant
    Filed: March 30, 1998
    Date of Patent: November 30, 1999
    Assignee: Neocera, Inc.
    Inventors: Lee A. Knauss, Kolagani S. Harshavardhan
  • Patent number: 5985026
    Abstract: A seed crystal assembly for producing monocrystals and a method for producing SiC monocrystals or monocrystalline SiC layers include a seed crystal with a surface having a first partial region intended as a crystallization surface for a monocrystal grown out of a gas phase and a second partial region with a coating that is chemically resistant to the seed crystal and to the gas phase and does not melt at the growth temperatures. As a result, thermal degradation of the seed crystal is avoided and the quality of the monocrystals which are produced is increased.
    Type: Grant
    Filed: February 17, 1998
    Date of Patent: November 16, 1999
    Assignee: Siemens Aktiengesellschaft
    Inventors: Johannes Volkl, Rene Stein
  • Patent number: 5980632
    Abstract: A process for producing a Group III--V compound semiconductor represented by the general formula In.sub.x Ga.sub.y Al.sub.z N (provided that x+y+z=1, 0.ltoreq.x.ltoreq.1, 0.ltoreq.y.ltoreq.1, and 0.ltoreq.z.ltoreq.1) employs a support member for forming the semiconductor, wherein the member constitutes SiC which is obtained by converting a graphite base material into SiC. In another embodiment, the member comprises a graphite-SiC composite wherein at least a surface layer part of a graphite substrate is converted into SiC. The member of the invention has superior chemical and mechanical stability, thereby making it useful in high-productivity production devices for making compound semiconductors.
    Type: Grant
    Filed: December 23, 1998
    Date of Patent: November 9, 1999
    Assignee: Sumitomo Chemical Company, Limited
    Inventors: Yasushi Iyechika, Toshihisa Katamime, Yoshinobu Ono, Tomoyuki Takada
  • Patent number: 5961718
    Abstract: The present invention provides a process for selectively depositing diamond films, which includes two stages of diamond deposition and the gas source used is a mixture of C.sub.x H.sub.y plus CO.sub.2 or C.sub.x H.sub.y O.sub.z plus CO.sub.2. In the period between the first and second stage, the substrate is immersed in an aqueous solution of HF plus HNO.sub.3. The obtained diamond films exhibit good crystallinity and selectivity and the growth rate is fast.
    Type: Grant
    Filed: October 16, 1995
    Date of Patent: October 5, 1999
    Assignee: National Science Council
    Inventors: Chia-Fu Chen, Sheng-Hsiung Chen, Tsao-Ming Hong
  • Patent number: 5948161
    Abstract: In fabricating a semiconductor device, a semiconductor layer containing Al and a cap layer not containing Al are successively grown on a semiconductor substrate and are placed in a halogen gas environment where a chemical reaction between a halogen and an oxide film naturally formed on the cap layer removes the oxide film. Then, without exposing the layer to the atmosphere, the halogen gas environment is replaced with a dry-etching environment and the cap layer is dry-etched to a desired depth. Then, without exposing a semiconductor layer to the atmosphere, the dry-etching environment is replaced with a crystal growth environment. Subsequently, another semiconductor layer is grown on the semiconductor layer. A regrowth interface of excellent cleanliness is realized and the crystallinity of the regrown semiconductor layer is improved.
    Type: Grant
    Filed: March 24, 1995
    Date of Patent: September 7, 1999
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hirotaka Kizuki
  • Patent number: 5938838
    Abstract: A head drum is coated with double films, each having different characteristics, by forming a first diamond-like hard carbon film of high degree of hardness and then forming a second diamond-like hard carbon film of a lower degree of hardness thereon. The degree of hardness of the second film is lower than that of the first film. The double coating is performed by means of a synthesizing apparatus which comprises a reactor consisting of a power supply electrode, a workpiece support and and an annular ground electrode spaced from the stacked head drums by a predetermined distance.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: August 17, 1999
    Assignee: Korea Institute of Science and Technology
    Inventors: Kwang-Ryeol Lee, Kwang-Yong Eun, Keun-Mo Kim
  • Patent number: 5935323
    Abstract: Articles with a tenaciously adherent diamond coating are made by forming a diamond coating on a base material by vapor-phase synthesis without causing any warpage of the coating. The diamond coating layer is formed on the surface of a base material having a number of pores formed by electric discharge or laser beams and having a depth of 0.0001-0.2 mm and a diameter of 0.001-0.02 mm. The pores may be connected to one another to form a groove. Suitable examples of the base material include molybdenum, tungsten, silicon, tungsten carbide, silicon carbide, silicon nitride, and cemented carbide mainly comprising tungsten carbide and cobalt and/or nickel.
    Type: Grant
    Filed: March 20, 1998
    Date of Patent: August 10, 1999
    Assignee: Toyo Kohan Co., Ltd.
    Inventors: Michifumi Tanga, Takahiro Kitagawa
  • Patent number: 5919305
    Abstract: A concept and process is disclosed by which an epitaxially deposited film is removed from its substrate at elevated temperatures to inhibit thermal mismatch strain induced defect generation in the epitaxial layer. The process occurs by gas phase reactions of an intermediate layer purposely deposited to react with a component in the gas stream during or after epitaxial growth. While the concept of an intermediate layer has been used extensively to improve the crystal quality of the epitaxial layer this is not the purpose of this interlayer. Although this interlayer may aid in nucleation of the epitaxial layer, the objective is to separate the epitaxial material on top of the interlayer from the substrate below the interlayer at or near the growth temperature to reduce the effects of the thermal mismatch between the substrate and epitaxial layers. An application is an addition to the above invention. A thick epitaxially deposited film can now be removed from its substrate at elevated temperatures.
    Type: Grant
    Filed: July 2, 1998
    Date of Patent: July 6, 1999
    Assignee: CBL Technologies, Inc.
    Inventor: Glenn S. Solomon
  • Patent number: 5893949
    Abstract: A new process to form a polycrystalline silicon film using a polycrystalline silicon-germanium (poly-Si.sub.1-x Ge.sub.x) capping film to "seed" crystallization of an amorphous silicon film on an upper surface of a substrate. The polycrystalline silicon film has no nucleation sites and a greater number of grain boundaries in the region near the polycrystalline silicon upper surface than in the region near the polycrystalline silicon and substrate upper surface interface. This indicates that crystallization and crystal growth occurred from the polycrystalline silicon upper surface and proceeded in a direction towards the substrate upper surface.
    Type: Grant
    Filed: December 26, 1995
    Date of Patent: April 13, 1999
    Assignee: Xerox Corporation
    Inventors: Tsu-Jae King, Jackson H. Ho
  • Patent number: 5882401
    Abstract: A method for manufacturing a silicon single crystal substrate for use of an epitaxial layer growth. The method comprises the steps of: growing a CVD film on a rear surface and a peripheral side portion, of the silicon single crystal substrate; removing a portion of the CVD film on the peripheral side portion in the vicinity of a main surface of the silicon single crystal substrate, which was grown over an end of the peripheral side portion, by an abrasive tape grinding; and thereafter mirror-polishing the main surface of the silicon single crystal substrate.
    Type: Grant
    Filed: August 8, 1997
    Date of Patent: March 16, 1999
    Assignee: Shin-Etsu Handotai Co., Ltd.
    Inventors: Tamotsu Maruyama, Hiroki Ose
  • Patent number: 5863324
    Abstract: Provided is a process for economically producing single crystal diamond film with a large surface area by gas-phase synthesis. The process comprises depositing platinum film or platinum alloy film containing more than 50 atomic % of platinum on a basal substrate with (111) or (001) surface while keeping the substrate temperature at 300.degree. C. or above, annealing the platinum or platinum alloy film at 1000.degree. C. or above, and performing the gas-phase synthesis of diamond using said platinum or platinum alloy film as the substrate.
    Type: Grant
    Filed: July 11, 1996
    Date of Patent: January 26, 1999
    Assignee: Kabushiki Kaisha Kobe Seiko Sho
    Inventors: Koji Kobashi, Takeshi Tachibana, Yoshihiro Shintani
  • Patent number: 5861058
    Abstract: A composite structure for electronic components, having a base substrate with a flat side provided with a depression, and having a cover layer which is disposed on the flat side structured by the depression, and the depression being covered to form a hollow structure. The depression in the base substrate is created prior to the deposition of the cover layer and has a clear width measured parallel to the flat side that is less than one-half of its clear depth measured before the cover layer is applied. The vapor phase deposited cover layer is formed from a material which has a sufficiently high surface tension to promote three-dimensional growth of the vapor phase deposited layer.
    Type: Grant
    Filed: April 22, 1996
    Date of Patent: January 19, 1999
    Assignee: Daimler-Benz Aktiengesellschaft
    Inventors: Hans-Juergen Fuesser, Reinhard Zachai, Wolfram Muench, Tim Gutheit, Mona Ferguson, Reiner Schaub, Karl-Heinrich Greeb
  • Patent number: 5853478
    Abstract: A method for forming a crystal, which comprises applying a crystal forming treatment on a substrate having a free surface on which a deposition surface (S.sub.NDS) with a small nucleation density and a deposition surface (S.sub.NDL) having a sufficiently small area for crystal growth only from a single nucleus and having a greater nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said deposition surface (S.sub.NDS) are arranged adjacent to each other, thereby growing a single crystal from said single nucleus.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 29, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Yasuhiro Naruse
  • Patent number: 5849077
    Abstract: A method of growing epitaxial regions comprising the steps of providing a silicon substrate, forming a patterned oxide layer having a planar upper surface on the substrate, the oxide layer having an aperture therein extending to the substrate, forming a layer of silicon in the aperture extending above the surface of the oxide layer and removing the portion of the layer of silicon extending above the surface of the oxide layer. The sidewalls of the oxide layer defining the aperture are outwardly sloped in the direction of the upper surface. The layer of silicon is formed by a procedure which forms crystalline silicon in the aperture and forms no silicon over the oxide layer. The portion of the layer of silicon extending above the surface of the oxide layer is removed by a chemical-mechanical polishing operation. In addition, to provide auto-alignment, the layer of oxide is selectively etched relative to the layer of silicon to provide a step at the interface of the layer of oxide and the layer of silicon.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: December 15, 1998
    Assignee: Texas Instruments Incorporated
    Inventor: Danny J. Kenney
  • Patent number: 5849673
    Abstract: A lanthanum aluminate (LaAlO.sub.3) substrate on which thin films of layered perovskite copper oxide superconductors are formed. Lanthanum aluminate, with a pseudo-cubic perovskite crystal structure, has a crystal structure and lattice constant that closely match the crystal structures and lattice constants of the layered perovskite superconductors. Therefore, it promotes epitaxial film growth of the superconductors, with the crystals being oriented in the proper direction for good superconductive electrical properties, such as a high critical current density. In addition, LaAlO.sub.3 has good high frequency properties, such as a low loss tangent and low dielectric constant at superconductive temperatures. Finally, lanthanum aluminate does not significantly interact with the superconductors. Lanthanum aluminate can also be used to form thin insulating films between the superconductor layers, which allows for the fabrication of a wide variety of superconductor circuit elements.
    Type: Grant
    Filed: November 7, 1994
    Date of Patent: December 15, 1998
    Assignee: TRW Inc.
    Inventors: Randy Wayne Simon, Christine Elizabeth Platt, Alfred Euinam Lee, Gregory Steven Lee
  • Patent number: 5846320
    Abstract: A method for forming a crystal comprises applying a crystal forming treatment on a substrate having a free surface comprising a nonnucleation surface (S.sub.NDS) with small nucleation density and a nucleation surface (S.sub.NDL) exposed from said nonnucleation surface having a sufficiently small area for a crystal growing only from a single nucleus and having a greater nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said non-nucleation surface (S.sub.NDS), thereby growing a single crystal from said single nucleus.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 8, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Jinsho Matsuyama, Yutaka Hirai, Masao Ueki, Akira Sakai
  • Patent number: 5843224
    Abstract: The invention relates to a composite structure including a semiconductor layer arranged on a diamond layer and/or a diamond-like layer, for subsequent processing to produce electronic components and/or groups of components and to a process for producing such a composite structure. In order to improve the quality of the subsequent components, the diamond layer is deposited underneath the component source zones from which the components are subsequently produced, and the diamond or diamond-like layer is provided at the margins of the component source zones and/or outside of the component source zones with edges where the thickness of the layer changes abruptly such that the edges have an edge height amounting to at least 1O%, preferably at least 50%, of the layer thickness of the diamond layer.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: December 1, 1998
    Assignee: Daimler-Benz Aktiengesellschaft
    Inventors: Reinhard Zachai, Tim Gutheit, Kenneth Goodson
  • Patent number: 5821200
    Abstract: A lattice matching device includes a substrate having thereon monocrystal regions having different lattice mismatches with respect to a LnBa.sub.2 Cu.sub.3 O.sub.x superconductor. A superconducting thin film is formed on the substrate, which film consists essentially of a superconductor of LnBa.sub.2 Cu.sub.3 O.sub.x wherein Ln represents yttrium or a lanthanide, and 6<x<7. The first and second superconducting thin film portions have different axes of orientation perpendicular to a main surface of the substrate, and arranged in contact with each other or at a distance which allows transmission of electron pairs from one to another.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: October 13, 1998
    Assignee: Nippon Telegraph and Telephone Corporation
    Inventors: Masashi Mukaida, Shintaro Miyazawa, Junya Kobayashi
  • Patent number: 5807433
    Abstract: The present invention concerns a novel multilayer system comprising a diamond layer, and the method of manufacturing this multilayer system.The invention concerns a multilayer system comprising a metallic substrate, an interphase and a diamond layer, the interphase being composed of the product of thermal decomposition of at least one metallocene compound.This multilayer system, capable of being used as an electrode, has improved adhesion between the substrate and the diamond layer.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: September 15, 1998
    Assignee: Eastman Kodak Company
    Inventors: Olivier Jean Christian Poncelet, Jean-Jacques Edgar Garenne
  • Patent number: 5792270
    Abstract: A method and apparatus for producing a pattern of nucleation sites is disclosed. The method enables the growth of single crystal layers of a desired orientation on a suitable amorphous and/or non-single crystal surface. The method can be used to produce single crystal Si layers of a desired orientation on an amorphous layer, e.g. of SiO.sub.2 or Si.sub.3 N.sub.4. The method can provide for growth of (100) crystal orientation on SiO.sub.2. Semiconductor films may be accordingly grown on amorphous glass substrates for producing solar cells of high efficiency. A pattern of nucleation sites is created in amorphous layers, e.g. SiO.sub.2 on an IC wafer, by high-dose implantation through a single crystal mask having appropriate channeling directions at the desired lattice constants. Such implantation may be performed in a conventional ion implanter. Subsequent to creation of spaced-apart nucleation sites, epitaxial Si may be grown on such an SiO.sub.2 surface by CVD of Si.
    Type: Grant
    Filed: October 21, 1993
    Date of Patent: August 11, 1998
    Inventor: Arjun Saxena
  • Patent number: 5792257
    Abstract: A method for protecting a susceptor when SiC, a Group III-nitride or alloys thereof, is epitaxially grown by chemical vapor deposition on a substrate arranged on a surface of the susceptor includes the steps of heating the susceptor and thus the substrate and a gas mixture fed to the substrate for the growth, placing a plate made of SiC, an alloy of SiC and the material grown, or the material grown, on the susceptor and arranging the substrate on the plate.
    Type: Grant
    Filed: April 14, 1995
    Date of Patent: August 11, 1998
    Assignee: ABB Research Ltd.
    Inventors: Olle Kordina, Christer Hallin, Erik Janzen
  • Patent number: 5788766
    Abstract: A window material, which has a high thermal conductivity material layer having a thermal conductivity of at least 10 W/cm.multidot.K and which has a cooling medium flow path on or in the high thermal conductivity material layer, has a high heat-dissipating property and a high transmittance.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: August 4, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiyuki Yamamoto, Keiichiro Tanabe, Katsuko Harano, Takashi Tsuno, Nobuhiro Ota, Naoji Fujimori
  • Patent number: 5785754
    Abstract: A substrate, which has a high thermal conductivity material layer having a thermal conductivity of at least 10 W/cm.multidot.K and which has a cooling medium flow path on or in the high thermal conductivity material layer, has a high heat-dissipating property.
    Type: Grant
    Filed: November 30, 1995
    Date of Patent: July 28, 1998
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Yoshiyuki Yamamoto, Keiichiro Tanabe, Katsuko Harano, Nobuhiro Ota, Naoji Fujimori
  • Patent number: 5753038
    Abstract: A method is disclosed for producing large single crystals. According to the initial steps of this method, a plurality of single crystal wafers are crystallographically oriented to form a seed plate which is patterned. The patterned seed plate is selectively etched to expose the bare surface of the seed plate. The exposed, patterned bare surface of the seed plate is etched to form a plurality of nucleation structures. Each of the nucleation structures protrude outwardly from the underlying surface of the seed plate and provide ideal structures for the growth of large, single crystals. The resulting large, single crystals can be separated from the seed crystals by etching, physical or chemical means.
    Type: Grant
    Filed: March 21, 1997
    Date of Patent: May 19, 1998
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Miroslav Vichr, David Samuel Hoover
  • Patent number: 5739086
    Abstract: A biaxially textured article includes a rolled and annealed, biaxially textured substrate of a metal having a face-centered cubic, body-centered cubic, or hexagonal close-packed crystalline structure; and an epitaxial superconductor or other device epitaxially deposited thereon.
    Type: Grant
    Filed: May 22, 1996
    Date of Patent: April 14, 1998
    Assignee: Lockheed Martin Energy Systems, Inc.
    Inventors: Amit Goyal, John D. Budai, Donald M. Kroeger, David P. Norton, Eliot D. Specht, David K. Christen
  • Patent number: 5733369
    Abstract: A method for forming a crystal, which comprises applying a crystal forming treatment on a substrate having a free surface on which a deposition surface (S.sub.NDS) with a small nucleation density and a deposition surface (S.sub.NDL) having a sufficiently small area for crystal growth only from a single nucleus and having a greater nucleation density (ND.sub.L) than the nucleation density (ND.sub.S) of said deposition surface (S.sub.NDS) are arranged adjacent to each other, thereby growing a single crystal from said single nucleus.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 31, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takao Yonehara, Yasuhiro Naruse
  • Patent number: 5730798
    Abstract: A method of masking semiconductor substrates during fabrication of semiconductor devices includes positioning an oxide mask on the substrate so as to define a growth area and an unmasked portion the surface. A dense oxide layer is grown on the unmasked portion and the oxide mask is removed to expose the growth area. The substrate is introduced into a growth chamber and heated to approximately 580.degree.-600.degree. C. to desorb any native oxide in the exposed growth area. Crystalline material is selectively grown on the exposed growth area and the substrate is heated to approximately 640.degree. C. under high arsenic flux to desorb the dense oxide layer, without removing the substrate from the chamber.
    Type: Grant
    Filed: August 7, 1995
    Date of Patent: March 24, 1998
    Assignee: Motorola
    Inventor: Kumar Shiralagi
  • Patent number: 5718761
    Abstract: A method of forming a crystalline compound semiconductor film comprises introducing into a crystal forming space housing a substrate on which a non-nucleation surface (S.sub.NDS) having a smaller nucleation density and a nucleation surface (S.sub.NDL) having a fine surface area sufficient for crystal growth only from a single nucleus and having a larger nucleation density (ND.sub.L) than the nucleation density (NDs) of the non-nucleation surface (S.sub.NDS) are arranged adjacent to each other an organometallic compound (VI) for supplying an element belonging to the group VI of Periodic Table represented by the general formula R.sub.1 --X.sub.n --R.sub.2 wherein n is an integer of 2 or more; R.sub.1 and R.sub.
    Type: Grant
    Filed: April 17, 1996
    Date of Patent: February 17, 1998
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroyuki Tokunaga, Jun-ichi Hanna, Isamu Shimizu
  • Patent number: 5709744
    Abstract: A method of masking surfaces during fabrication of semiconductor devices is disclosed, which includes providing a gallium arsenide substrate. The surface can include a layer of native oxide or not, and a metal mask is positioned adjacent the surface so as to define a growth area and an unmasked portion on the surface. Ultraviolet light is directed at the unmasked area, by exposing the surface to a bright light, so as to grow an oxide film on the unmasked portion of the surface. The metal mask is removed and the oxide film then serves as a mask for further operations and can be easily removed in situ by heating. If native oxide is included, it can be removed in situ by heating the substrate to a lower temperature.
    Type: Grant
    Filed: March 1, 1996
    Date of Patent: January 20, 1998
    Assignee: Motorola
    Inventor: Shiralagi Kumar
  • Patent number: 5690736
    Abstract: A crystal is formed by applying crystal forming treatment to a substrate, the surface of the substrate being divided into nonnucleation surface exhibiting a small nucleation density and nucleation surface having a sufficeintly small area to allow crystal growth from a single nucleus and exhibiting a larger nucleation density than the nonnucleation surface and the nonnucleation surface being constituted of the surface of a buffer layer to alleviate generation of stress in the crystal formed.
    Type: Grant
    Filed: January 31, 1996
    Date of Patent: November 25, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Hiroyuki Tokunaga
  • Patent number: 5676752
    Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.
    Type: Grant
    Filed: August 16, 1994
    Date of Patent: October 14, 1997
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl O. Bozler, John C. C. Fan, Robert W. McClelland
  • Patent number: 5661074
    Abstract: A green-blue to ultraviolet light-emitting optical device, e.g. a green-blue to ultraviolet emitting laser or a green-blue to ultraviolet emitting diode, comprising a green-blue to ultraviolet light emitting gallium nitride material on a base structure including a silicon carbide substrate, which preferably consists of 2H--SiC, 4H--SiC, or a-axis oriented 6H--SiC. The carrier mobility and the transparency of the silicon carbide substrate are optimized by the selection of orientation and polytype, thus enhancing device performance. The light-emitting diodes may incorporate a structural modification to increase the light output comprising a dielectric Bragg mirror beneath the LED structure, made of alternating layers of AlN, GaN, InN or their alloys. Methods for making such light-emitting diodes are provided, including a technique for defining individual devices by mesa etching which avoids possible damage to the active area during dicing.
    Type: Grant
    Filed: May 24, 1995
    Date of Patent: August 26, 1997
    Assignee: Advanced Technology Materials, Inc.
    Inventor: Michael A. Tischler
  • Patent number: 5656076
    Abstract: In a method for growing a III-V group compound semiconductor crystal, as a Si dopant, a compound including a Si atom bonded to an alkyl group and a hydrogen atom is used. Also, a compound including two Si atoms in one molecule thereof, at least one of said Si atoms being bonded to a hydrogen atom, and at least the other of said Si atoms being bonded to an alkyl group can be used. Further, a compound including two Si atoms in one molecule thereof, at least one of said Si atoms being bonded to a hydrogen atom, and at least the other of said Si atoms being bonded to a phenyl group or a compound including a Si atom bonded to an organic amino group can be used. Si can be doped evenly at a high concentration at a low temperature with a safe operation by the invention.
    Type: Grant
    Filed: May 26, 1995
    Date of Patent: August 12, 1997
    Assignee: Fujitsu Limited
    Inventor: Toshihide Kikkawa
  • Patent number: 5653802
    Abstract: A method for forming a crystal comprises implanting ions on the surface of a substrate to change the ion concentration in the depth direction of said substrate surface by said ion implantation, subjecting a desired position of said substrate surface with a sufficient area for crystal growth from a single crystal to exposure treatment to/he depth where an exposed surface having larger nucleation density than the nucleation density of the surface of said substrate is exposed, thereby forming a nucleation surface comprising said exposed surface exposed by said exposure treatment and a nonnucleation surface comprising the surface of the substrate remaining without subjected to said exposure treatment, applying a crystal growth treatment for crystal growth from a single nucleus on said substrate to grow a single crystal from said single nucleus or form a polycrystal of a mass of single crystals grown from said single nucleus.
    Type: Grant
    Filed: May 30, 1995
    Date of Patent: August 5, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Kenji Yamagata
  • Patent number: 5651818
    Abstract: The invention concerns materials which exhibit photonic band gaps in the near infrared and visible regions of the optical spectrum and methods of preparation of such materials.The materials manufactured according to the invention are particularly suitable for use in the optical analog to semiconductor behavior, in which a photonic band gap material, or a plurality of such materials acting in concert, can be made to interact with and control light wave propagation in a manner analogous to the way that semiconductor materials can be made to interact with and control the flow of electrically charged particles, i.e., electricity, in both analog and digital applications.
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: July 29, 1997
    Inventors: Joseph B. Milstein, Ronald G. Roy
  • Patent number: 5637145
    Abstract: In a vapor phase epitaxial growth process, formation of a silicon nodule on a back side protective film on a wafer is prevented. In the process, a susceptor situated within a reaction chamber is provided with a depression portion for supporting a wafer at a back side peripheral portion thereof. A protection film on a back side peripheral portion of the wafer, which is to be in contact with the susceptor 4 is removed in advance, prior to epitaxial growth. In addition, it is also effective to apply a silicon coating on the surface of the depression portion, prior to the epitaxial growth process.
    Type: Grant
    Filed: January 3, 1996
    Date of Patent: June 10, 1997
    Assignee: Toshiba Machine Co., Ltd.
    Inventors: Yoshihiro Miyanomae, Nobuo Kashiwagi
  • Patent number: 5634974
    Abstract: A method of forming HSG is disclosed, in which a layer of starting material is formed on a wafer, the layer of starting material is seeded with a species and the seeded layer is annealed. The seeding and annealing steps can be performed under different conditions and can be varied independently of each other.
    Type: Grant
    Filed: November 3, 1995
    Date of Patent: June 3, 1997
    Assignee: Micron Technologies, Inc.
    Inventors: Ronald A. Weimer, Randhir P. S. Thakur, Avishai Kepten, Michael Sendler
  • Patent number: 5634973
    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: June 3, 1997
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
  • Patent number: 5632812
    Abstract: A diamond electronic device constituted of a diamond crystal formed on a substrate comprises a diamond crystal having the ratio (h/L) of length (h) of the diamond crystal in direction substantially perpendicular to the face of the substrate to length (L) of the diamond crystal in direction parallel to the face of the substrate ranging from 1/4 to 1/1000 and an upper face of the diamond crystal making an angle of from substantially 0.degree. to 10.degree. to the face of the substrate, and a semiconductor layer and an electrode layer provided on the diamond crystal, wherein the diamond crystal serves as a heat-radiating layer.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: May 27, 1997
    Assignee: Canon Kabushiki Kaisha
    Inventor: Keiji Hirabayashi
  • Patent number: 5631190
    Abstract: A method of producing light emitting diodes from silicon carbide with increased external efficiency is disclosed which includes directing a beam of laser light at one surface of a portion of silicon carbide, and in which the laser light is sufficient to vaporize the silicon carbide that it strikes to thereby define a cut in the silicon carbide portion; and then dry etching the silicon carbide portion to remove by-products generated when the laser light cuts the silicon carbide portion. The resulting wafer and diode structure are also disclosed.
    Type: Grant
    Filed: October 7, 1994
    Date of Patent: May 20, 1997
    Assignee: Cree Research, Inc.
    Inventor: Gerald H. Negley
  • Patent number: 5588994
    Abstract: A method of producing sheets of crystalline material is disclosed, as well as devices employing such sheets. In the method, a growth mask is formed upon a substrate and crystalline material is grown at areas of the substrate exposed through the mask and laterally over the surface of the mask to form a sheet of crystalline material. This sheet is optionally separated so that the substrate can be reused. The method has particular importance in forming sheets of crystalline semiconductor material for use in solid state devices.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: December 31, 1996
    Assignee: Massachusetts Institute of Technology
    Inventors: Carl O. Bozler, John C. C. Fan, Robert W. McClelland
  • Patent number: 5580380
    Abstract: A method for making a field emitter comprising the steps of providing a projection; electrically biasing the projection; and exposing the electrically biased projection to a hydrocarbon containing plasma to form a layer of diamond nuclei on the projection. The diamond nuclei are relatively inert and have a high nucleation density. The projection is preferably a material capable of forming a carbide, such as (111) oriented silicon. Refractory metals may also be used for the projection. The electrical biasing is preferably at a voltage in a range of about -150 to -250 volts. The hydrocarbon containing plasma preferably comprises a plasma including about 2 to 5% by weight of methane in hydrogen. An intervening carbide layer is preferably formed at a surface of the projection and underlying the layer of diamond nuclei. The field emitter produced by the method and having a relatively high diamond nucleation density is also disclosed.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: December 3, 1996
    Assignee: North Carolina State University
    Inventors: Jiang Liu, Scott Wolter, Michael T. McClure, Brian R. Stoner, Jeffrey T. Glass, John J. Hren
  • Patent number: 5578521
    Abstract: A silicon semiconductor substrate, on which an epitaxial layer is to be formed, is set in a reaction vessel having a heating mechanism, and a gas containing TMG and AsH.sub.3 is introduced into the reaction vessel with the substrate heated to 450.degree. C., thus forming, on the substrate, a low-temperature growth layer of amorphous or polycrystalline GaAs as a semiconductor substance having a different lattice constant from that of the substrate. Then, with the TMG removed from the introduced gas, the temperature of the semiconductor substrate is increased to 750.degree. C., to cause coagulation of atoms of the low-temperature growth layer, with a thermal treatment also being performed at this high temperature, to cause growth of island-like single crystal cores. Further, a high temperature growth process is conducted in a material gas atmosphere containing TMG, whereby a GaAs film is epitaxially grown on the semiconductor substrate surface.
    Type: Grant
    Filed: May 3, 1995
    Date of Patent: November 26, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yasutoshi Suzuki, Takamasa Suzuki, Kunihiko Hara, Hajime Inuzuka, Naomi Awano, Kouichi Hoshino
  • Patent number: 5565031
    Abstract: Epitaxial and polycrystalline layers of silicon and silicon-germanium alloys are selectively grown on a semiconductor substrate or wafer by forming over the wafer a thin film masking layer of an oxide of an element selected from scandium, yttrium, lanthanum, cerium, praseodymium, neodymium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, and lutetium; and then growing the epitaxial layer over the wafer at temperatures below 650.degree. C. The epitaxial and polycrystalline layers do not grow on the masking layer. The invention overcomes the problem of forming epitaxial layers at temperatures above 650.degree. C. by providing a lower temperature process.
    Type: Grant
    Filed: February 17, 1995
    Date of Patent: October 15, 1996
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Jack O. Chu, James M. E. Harper
  • Patent number: 5562769
    Abstract: A microelectronic structure including a plurality of spaced apart diamond structures on which a plurality of semiconductor devices may be formed. The semiconductor devices include a semiconducting diamond layer on each of the diamond structures. The diamond structures are preferably oriented relative to a single crystal nondiamond substrate so that the diamond structures have a (100)-oriented outer face for forming the semiconductor devices thereon. The microelectronic structure may be diced into discrete devices, or the devices interconnected, such as to form a higher powered device. One embodiment of the microelectronic structure includes the plurality of diamond structures, wherein each diamond structure is formed of a highly oriented textured diamond layer approaching single crystal quality, yet capable of fabrication on a single crystal nondiamond substrate.
    Type: Grant
    Filed: February 22, 1995
    Date of Patent: October 8, 1996
    Assignee: Kobe Steel USA, Inc.
    Inventors: David L. Dreifus, Brian R. Stoner, Jeffrey T. Glass
  • Patent number: 5562770
    Abstract: The present invention provides a method of global stress modification which results in reducing number of dislocations in an epitaxially grown semiconducting device layer on a semiconductor substrate where the device layer and the substrate have a lattice mismatch. The invention teaches a method of imparting a convex curvature to the substrate by removing layer(s) of thin film from or adding layers of thin film to the back side of the substrate, so as to achieve a reduced dislocation density in the device layer.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: October 8, 1996
    Assignee: International Business Machines Corporation
    Inventors: Bomy A. Chen, Terence B. Hook, Subhash B. Kulkarni
  • Patent number: 5556463
    Abstract: A method of forming a crystallographically oriented silicon layer over a glassy layer of, for example, SiO.sub.2. A templating layer of a layered perovskite, preferably Bi.sub.4 Ti.sub.3 O.sub.12, is deposited on the glassy layer under conditions favoring its crystallographic growth with its long c-axis perpendicular to the film. The silicon is then grown over the templating layer under conditions usually favoring monocrystalline growth. Thereby, it grows crystallographically aligned with the underlaying templating layer.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: September 17, 1996
    Inventor: Charles S. Guenzer
  • Patent number: 5549749
    Abstract: The invention provides a semiconductor substrate comprising a substrate of a first material and a crystal growth layer formed on the substrate, the crystal growth layer being made of compound semiconductors different from the first material wherein the substrate has a surface diffusion region being heavily doped with one or more elements of the compound semiconductors. A silicon substrate receives an ion-implantation of one or more elements constituting a compound semiconductor different except for silicon at a high impurity concentration for a heat treatment at a higher temperature than a growth temperature of the compound semiconductor and subsequent cooling down to the growth temperature of the compound semiconductor followed by crystal growth of the compound semiconductor on the substrate.
    Type: Grant
    Filed: April 24, 1995
    Date of Patent: August 27, 1996
    Assignee: NEC Corporation
    Inventor: Shuji Asai
  • Patent number: 5518953
    Abstract: A semiconductor device is manufactured by forming an epitaxial layer (22) insulated from a silicon substrate (2), and forming a device in the epitaxial layer (22). On the semiconductor substrate (2), a silicon dioxide layer (4) is formed (FIG. 2A). Then the silicon dioxide layer (4) is provided with openings (14) (FIG. 2D). Silicon carbide is grown until it protrudes from the openings (14) to thereby form a silicon carbide seed crystal layer (16) (FIG. 2E). Next, oxidation is carried out, allowing a field oxide layer (20) to be connected at the portion under the openings (14) and the silicon carbide seed crystal layer (16) to be insulated from the silicon substrate (2). Thereafter, epitaxial growth is effected from the silicon carbide seed crystal layer (16). The growth is stopped before silicon grown layers (22) connect to one another, thus obtaining epitaxially grown layers (22) having regions which are separate from one another. The MOS device is formed in this epitaxially grown layer (22).
    Type: Grant
    Filed: March 15, 1994
    Date of Patent: May 21, 1996
    Assignee: Rohm Co., Ltd.
    Inventor: Hidemi Takasu
  • Patent number: 5512375
    Abstract: High quality epitaxial layers can be grown on a multi-layer substrate which has a crystalline pseudomorphic layer with an exposed surface used for the epitaxial growth. The pseudomorphic layer of the substrate has a thickness at or below the pseudomorphic limit so it will be deformed as stress forces are developed during epitaxial growth of heteroepitaxial structures. A plastically deformable layer is bonded to the pseudomorphic layer, This plastically deformable layer is made of material that plastically flows at epitaxial growth temperatures.
    Type: Grant
    Filed: October 14, 1993
    Date of Patent: April 30, 1996
    Assignee: Intevac, Inc.
    Inventors: Roger T. Green, Gary A. Davis, Verle W. Aebi