Semiconductor Cleaning Patents (Class 134/1.2)
  • Patent number: 8097088
    Abstract: Methods for processing substrates in dual chamber processing systems comprising first and second process chambers that share resources may include performing a first internal chamber clean in each of the first process chamber and the second process chamber; and subsequently processing a substrate in one of the first process chamber or the second process chamber by: providing a substrate to one of the first process chamber or the second process chamber; providing a process gas to the first process chamber and the second process chamber; forming a plasma in only the one of the first process chamber or the second process chamber having the substrate contained therein; and providing an inert gas to the first process chamber and the second process chamber via one or more channels formed in a surface of respective substrate supports disposed in the first process chamber and the second process chamber while processing the substrate.
    Type: Grant
    Filed: April 18, 2011
    Date of Patent: January 17, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Eu Jin Lim, Adauto Diaz, Jr., Benjamin Schwarz, James P. Cruse, Charles Hardy
  • Patent number: 8097087
    Abstract: A method of cleaning a support plate according to which, while no waste solution is produced after cleaning the support plate, the support plate can be treated at low cost. The method of cleaning the support plate includes the step of removing an organic substance adhered to the support plate by putting the support plate in contact with oxygen plasma.
    Type: Grant
    Filed: July 16, 2010
    Date of Patent: January 17, 2012
    Assignee: Tokyo Ohka Kogyo Co., Ltd.
    Inventors: Tatsuhiro Mitake, Atsushi Miyanari, Yoshihiro Inao
  • Patent number: 8093154
    Abstract: In one embodiment of the invention, a method for finishing or treating a silicon-containing surface is provided which includes removing contaminants and/or smoothing the surface contained on the surface by a slow etch process (e.g., about <100 ?/min). The silicon-containing surface is exposed to an etching gas that contains an etchant and a silicon source. Preferably, the etchant is chlorine gas so that a relatively low temperature (e.g., <800° C.) is used during the process. In another embodiment, a method for etching a silicon-containing surface during a fast etch process (e.g., about >100 ?/min) is provided which includes removing silicon-containing material to form a recess in a source/drain (S/D) area on the substrate. In another embodiment, a method for cleaning a process chamber is provided which includes exposing the interior surfaces with a chamber clean gas that contains an etchant and a silicon source.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: January 10, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Ali Zojaji, Arkadii V. Samoilov
  • Patent number: 8083963
    Abstract: A substrate is processed in a process chamber comprising a substrate support having a receiving surface for receiving a substrate so that a front surface of the substrate is exposed within the chamber. An energized process gas is used to process the front surface of the substrate. A peripheral edge of the backside surface of the substrate is cleaned by raising the substrate above the receiving surface of the substrate support to a raised position, and exposing the backside surface of the substrate to an energized cleaning gas.
    Type: Grant
    Filed: April 3, 2007
    Date of Patent: December 27, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Gerardo A. Delgadino, Indrajit Lahiri, Teh-Tien Su, Sy-Yuan Brian Shieh, Ashok Sinha
  • Patent number: 8083959
    Abstract: In the present invention, a plurality of rounds of patterning are performed on a substrate. In a patterning system, the substrate on which a first round of patterning has been performed is transferred to a planarizing film forming unit, where a planarizing film is formed above the substrate. The substrate is then transferred to the patterning system and subjected to a second round of patterning. The time from the completion of the forming processing of the planarizing film to the start of the second round of patterning is managed to be constant among the substrates. According to the present invention, in the pattern forming processing of performing a plurality of rounds of patterning, a pattern with a desired dimension can be stably formed above the substrate.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: December 27, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Hideharu Kyouda, Junichi Kitano, Osamu Miyahara, Kenji Tsutsumi
  • Patent number: 8052799
    Abstract: An apparatus and a method for operating the same. The method includes providing an apparatus which includes a chamber, wherein the chamber includes first and second inlets, an anode and a cathode structures in the chamber, and a wafer on the cathode structure. A cleaning gas is injected into the chamber via the first inlet. A collecting gas is injected into the chamber via the second inlet. The cleaning gas when ionized has a property of etching a top surface of the wafer resulting in a by-product mixture in the chamber. The collecting gas has a property of preventing the by-product mixture from depositing back to the surface of the wafer.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: November 8, 2011
    Assignee: International Business Machines Corporation
    Inventors: Edward Crandal Cooney, III, William Joseph Murphy, Anthony Kendall Stamper, David Craig Strippe
  • Patent number: 8055365
    Abstract: A system for supplying a reagent to multiple tools in an electronics fabrication facility is configured using a demand probability distribution. In specific examples the reagent is a non-atmospheric or a specialty gas and the demand probability distribution is developed using Monte Carlo statistical techniques. In one embodiment, a method for configuring a reagent supply system for an electronic device manufacturing facility is provided. The method includes (a) collecting representative information for process tools within the fabrication facility which use the reagent; (b) creating a simulation of process tool operation to model an overall demand profile for the process tools; (c) creating a statistical probability distribution of the reagent demand by the process tools using data from the model; and (d) correlating data from the probability distribution with supply system characterization data to configure the supply system.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: November 8, 2011
    Assignee: Praxair Technology, Inc.
    Inventors: Jeremy Michael Cabral, Shrikar Chakravarti
  • Patent number: 8043434
    Abstract: A method and apparatus remove photoresist from a wafer. A process gas containing sulfur (S), oxygen (O), and hydrogen (H) is provided, and a plasma is generated from the process gas in a first chamber. A radical-rich ion-poor reaction medium is flown from the first chamber to a second chamber where the wafer is placed. The patterned photoresist layer on the wafer is removed using the reaction medium, and then the reaction medium flowing into the second chamber is stopped. Water vapor may be introduced in a salvation zone provided in a passage of the reaction medium flowing down from the plasma such that the water vapor solvates the reaction medium to form solvated clusters of species before the reaction medium reaches the wafer. The photoresist is removed using the solvated reaction medium.
    Type: Grant
    Filed: October 23, 2008
    Date of Patent: October 25, 2011
    Assignee: Lam Research Corporation
    Inventors: Robert P. Chebi, Jaroslaw W. Winniczek
  • Patent number: 8025736
    Abstract: Semiconductor device fabrication equipment performs a PEOX (physical enhanced oxidation) process, and includes a remote plasma generator for cleaning a process chamber of the equipment. After a PEOX process has been preformed, a purging gas is supplied into the process chamber to purge the process chamber, and the remote plasma generator produces plasma using a first cleaning gas. Accordingly, a reactor of the remote plasma generator is cleaned by the first cleaning gas plasma. Subsequently, the purging gas is supplied to purge the process chamber, and the remote plasma generator produces plasma using a second cleaning gas to remove the first cleaning gas plasma from the remote plasma generator and the process chamber. Finally, full flush operations are performed to remove any gases remaining in the process chamber.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: September 27, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kyoung-Hwan Chin, Kyoung-In Kim, Hak-Su Jung, Kyoung-Min An
  • Patent number: 8021717
    Abstract: A treatment gas is supplied to form a Ti-based film on a predetermined number of wafers W while setting a temperature of a susceptor 2 in a chamber 1 to a predetermined temperature. After this, the interior of the chamber 1 containing no wafers W is cleaned by discharging Cl2 gas as a cleaning gas from a shower head 10 into the chamber 1. During this cleaning, the temperature of each of the susceptor 2, the shower head 10, and the wall portion of the chamber 1 is independently controlled so that the temperature of the susceptor 2 is not lower than the decomposition start temperature of Cl2 gas and the temperature of the shower head 10 and the wall portion of the chamber 1 is not higher than the decomposition start temperature.
    Type: Grant
    Filed: January 12, 2009
    Date of Patent: September 20, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Seishi Murakami, Masaki Koizumi, Hiroaki Ashizawa, Masato Koizumi
  • Patent number: 8021565
    Abstract: A surface treatment method includes: removing a fluorocarbon-containing reaction product from a surface of a workpiece by oxygen gas plasma processing. The workpiece includes a plurality of layers. The fluorocarbon-containing reaction product is deposited by successively etching the layers of the workpiece. The method further includes after removing the reaction product, removing an oxide-containing reaction product from the surface of the workpiece using hydrogen fluoride gas.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: September 20, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuaki Aoki, Naoya Hayamizu, Kei Hattori, Yukihiro Oka, Hidemi Kanetaka, Makoto Hasegawa
  • Patent number: 8011116
    Abstract: A method is provided for removing a residual fluid remaining at a point of contact between a substrate support member and a back surface of a substrate being prepared by a proximity head. According to the method, the proximity head is applied onto the back surface of the substrate and the substrate support member being held by a carrier. The substrate support member is heated after the substrate support member passes the proximity head. The heating of the substrate support member is discontinued once the residual fluid has substantially evaporated.
    Type: Grant
    Filed: August 20, 2010
    Date of Patent: September 6, 2011
    Assignee: Lam Research Corporation
    Inventors: Katrina Mikhaylichenko, Kenneth C. Dodge, Mikhail Korolik, Michael Ravkin, John M. de Larios, Fritz C. Redeker
  • Patent number: 7994063
    Abstract: Disclosed is a method for cleaning a semiconductor substrate that can solve a problem of a conventional cleaning method which should include at least five steps for cleaning a substrate such as a semiconductor substrate. The method for cleaning a semiconductor substrate comprises a first step of cleaning a substrate with ultrapure water containing ozone, a second step of cleaning the substrate with ultrapure water containing a surfactant, and a third step of removing an organic compound derived from the surfactant, with a cleaning liquid containing ultrapure water and 2-propanol. After the third step, plasma of noble gas such as krypton is applied to the substrate to further remove the organic compound derived from the surfactant.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: August 9, 2011
    Assignees: National University Corporation Tohoku University, Stella Chemifa Corporation
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Rui Hasebe, Masayuki Miyashita
  • Patent number: 7989353
    Abstract: Method for operating a processing system and refurbishing a ceramic substrate holder within a process chamber of the processing system are described. The method includes plasma processing one or more substrates on the ceramic substrate holder, where the processing causes erosion of a nitride material of the ceramic substrate holder. The method further includes refurbishing the ceramic substrate holder in-situ without a substrate residing on the ceramic substrate holder, where the refurbishing includes exposing the ceramic substrate holder to a plasma-excited nitrogen-containing gas in the process chamber to at least partially reverse the erosion of the nitride material.
    Type: Grant
    Filed: January 2, 2008
    Date of Patent: August 2, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Tadahiro Ishizaka, Kentaro Asakura, Masanao Ando, Toshio Hasegawa
  • Publication number: 20110180097
    Abstract: An apparatus for treating a workpiece, the apparatus comprising a first chamber configured to treat the workpiece at an elevated temperature, the first chamber including an opening for receiving the workpiece; a second chamber in operative communication with the first chamber, the second chamber including an opening for transferring the workpiece to and from the first chamber, wherein the first chamber opening is aligned with the second chamber opening, and wherein a selected one of the first and the second chambers comprises a gate valve configured to selectively open and close access to the first and second chamber openings; and a thermal isolation plate formed of a material effective to substantially prevent heat transfer from the first chamber to the second chamber, wherein the thermal isolation plate is disposed about the first and second chamber openings in a sealing relationship.
    Type: Application
    Filed: January 27, 2010
    Publication date: July 28, 2011
    Applicant: AXCELIS TECHNOLOGIES, INC.
    Inventors: Armin Huseinovic, Ivan L. Berry
  • Patent number: 7977244
    Abstract: Disclosed is a semiconductor manufacturing process, in which a fluorine radical-containing plasma is used to etch a hard mask and a layer therebeneath; and a treatment is carried out using a gas reactive to fluorine radicals for reacting with residual fluorine radicals to form a fluorine-containing compound and remove it. Thus, precipitates formed by the reaction of fluorine radicals and titanium components existing in the hard mask to cause a process defect can be avoided.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: July 12, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Yu-Tsung Lai, Chun-Jen Huang, Jyh-Cherng Yau, Jiunn-Hsiung Liao
  • Patent number: 7975901
    Abstract: A bonding apparatus including a chamber for maintaining an inert gas atmosphere; a first plasma torch for performing a surface treatment on pads and electrodes, the first plasma torch being attached in the chamber, to apply gas plasma to a substrate and a semiconductor chip that is placed inside the chamber; a second plasma torch for performing a surface treatment on an initial ball and/or wire at a tip end of a capillary that is positioned inside the chamber, the second plasma torch being attached in the chamber, to apply gas plasma to the initial ball and/or wire; and a bonding unit for bonding the surface-treated initial ball and/or wire to the surface-treated pads and electrodes in the chamber, thereby cleaning of the surface of the electrodes and pads as well as the wire can be effectively performed.
    Type: Grant
    Filed: June 7, 2010
    Date of Patent: July 12, 2011
    Assignees: Shinkawa Ltd., Tohoku University
    Inventors: Toru Maeda, Tetsuya Utano, Akinobu Teramoto
  • Patent number: 7967913
    Abstract: A remote plasma process for removing unwanted deposition build-up from one or more interior surfaces of a substrate processing chamber after processing a substrate disposed in the substrate processing chamber. In one embodiment, the substrate is transferred out of the substrate processing chamber and a flow of a fluorine-containing etchant gas is introduced into a remote plasma source where reactive species are formed. A continuous flow of the reactive species from the remote plasmas source to the substrate processing chamber is generated while a cycle of high and low pressure clean steps is repeated. During the high pressure clean step, reactive species are flown into the substrate processing chamber while pressure within the substrate processing chamber is maintained between 4-15 Torr.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: June 28, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Zhong Qiang Hua, Sanjay Kamath, Young S. Lee, Ellie Y. Yieh, Hien-Minh Huu Le, Anjana M. Patel, Sudhir R. Gondhalekar
  • Patent number: 7964039
    Abstract: An improved reaction chamber cleaning process is provided for removing water residues that makes use of noble-gas plasma reactions. The method is easy applicable and may be combined with standard cleaning procedure. A noble-gas plasma (e.g. He) that emits high energy EUV photons (E>20 eV) which is able to destruct water molecules to form electronically excited oxygen atoms is used to remove the adsorbed water.
    Type: Grant
    Filed: September 5, 2008
    Date of Patent: June 21, 2011
    Assignees: IMEC, Katholieke Universiteit Leuven K.U. Leuven R&D
    Inventors: Adam Michal Urbanowicz, Mikhaïl Baklanov, Denis Shamiryan, Stefan De Gendt
  • Publication number: 20110139176
    Abstract: Improved methods for stripping photoresist and removing etch-related residues from dielectric materials are provided. In one aspect of the invention, methods involve removing material from a dielectric layer using a hydrogen-based etch process employing a weak oxidizing agent and fluorine-containing compound. Substrate temperature is maintained at a level of about 160° C. or less, e.g., less than about 90° C.
    Type: Application
    Filed: December 11, 2009
    Publication date: June 16, 2011
    Inventors: David Cheung, Ted Li, Anirban Guha, Kirk Ostrowski
  • Patent number: 7959820
    Abstract: According to the substrate processing method of the invention, a jet of droplets generated from a gas and a heated processing liquid is supplied to the surface of a substrate. A resist stripping liquid to strip off the resist from the surface of the substrate is then supplied to the surface of the substrate.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: June 14, 2011
    Assignee: Dainippon Screen Mfg. Co., Ltd.
    Inventor: Akio Hashizume
  • Publication number: 20110136346
    Abstract: Non-oxidizing plasma treatment devices for treating a semiconductor workpiece generally include a substantially non-oxidizing gas source; a plasma generating component in fluid communication with the non-oxidizing gas source; a process chamber in fluid communication with the plasma generating component, and an exhaust conduit centrally located in a bottom wall of the process chamber. In one embodiment, the process chamber is formed of an aluminum alloy containing less than 0.15% copper by weight; In other embodiments, the process chamber includes a coating of a non-copper containing material to prevent formation of copper hydride during processing with substantially non-oxidizing plasma. In still other embodiments, the process chamber walls are configured to be heated during plasma processing. Also disclosed are non-oxidizing plasma processes.
    Type: Application
    Filed: December 4, 2009
    Publication date: June 9, 2011
    Applicant: AXCELIS TECHNOLOGIES, INC.
    Inventors: Phillip Geissbühler, Ivan Berry, Armin Huseinovic, Shijian Luo, Aseem Kumar Srivastava, Carlo Waldfried
  • Publication number: 20110114115
    Abstract: A continuously variable microwave circuit capable of being tuned to operate under a plurality of distinct operating conditions, comprising: a waveguide comprising an adjustable tuning element having a core configured to protrude into the waveguide; an actuator in operative communication with the adjustable tuning element, wherein the actuator is operable to selectively vary a length of the core that is protruding into the waveguide so as to minimize reflected microwave power in the plasma asher; and a controller in operative communication with the actuator, wherein the controller is configured to selectively activate the actuator upon a change in the plurality of operating conditions.
    Type: Application
    Filed: November 18, 2009
    Publication date: May 19, 2011
    Applicant: AXCELIS TECHNOLOGIESM INC.
    Inventors: Aseem K. Srivastava, Robert P. Couilliard
  • Patent number: 7938976
    Abstract: A method for removing undesirable contaminants from a chip passivation layer surface without creating SiO2 particles on the passivation layer, wherein the undesirable contaminants include graphitic layers and fluorinated layers. The use of N2 plasma with optimized plasma parameters can remove through etching both the graphitic and fluorinated organic layers. The best condition for the N2 plasma treatment is to use a relatively low-power within the range of 100-200 W and a relatively high vacuum pressure of N2 in the range of 500-750 mTorr.
    Type: Grant
    Filed: February 27, 2007
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventor: Kang-Wook Lee
  • Patent number: 7914623
    Abstract: A combination of a dry oxidizing, wet etching, and wet cleaning processes are used to remove particle defects from a wafer after ion implantation, as part of a wafer bonding process to fabricate a SOI wafer. The particle defects on the topside and the backside of the wafer are oxidized, in a dry strip chamber, with an energized gas. In a wet clean chamber, the backside of the wafer is treated with an etchant solution to remove completely or partially a thermal silicon oxide layer, followed by exposure of the topside and the backside to a cleaning solution. The cleaning solution contains ammonium hydroxide, hydrogen peroxide, DI water, and optionally a chelating agent, and a surfactant. The wet clean chamber is integrated with the dry strip chamber and contained in a single wafer processing system.
    Type: Grant
    Filed: October 24, 2007
    Date of Patent: March 29, 2011
    Assignee: Applied Materials, Inc.
    Inventors: James S. Papanu, Han-Wen Chen, Brian J. Brown, Steven Verhaverbeke
  • Patent number: 7906032
    Abstract: A method of conditioning a processing chamber for a production process includes performing a conditioning step at a conditioning process recipe substantially different than a process recipe of the production process, and performing a warm-up process at a warm-up process recipe substantially the same as the process recipe of the production process. The method can be performed after a wet-cleaning process has been performed. The conditioning procedure can allow the maintenance time to be decreased and can cause the etched features to be more accurate.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: March 15, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Asao Yamashita
  • Patent number: 7897059
    Abstract: A method is provided for the removal of tin or tin alloys from substrates such as the removal of residual tin solder from the molds used in the making of interconnect solder bumps on a wafer or other electronic device. The method is particularly useful for the well-known C4NP interconnect technology and uses an etchant composition comprising cupric ions and HCl. Cupric chloride and cupric sulfate are preferred. A preferred method regenerates cupric ions by bubbling air or oxygen through the etchant solution during the cleaning process.
    Type: Grant
    Filed: November 9, 2007
    Date of Patent: March 1, 2011
    Assignee: International Business Machines Corporation
    Inventors: Richard F. Indyk, Krystyna W. Semkow
  • Patent number: 7879735
    Abstract: A cleaning solution and methods of fabricating semiconductor devices using the same are provided. A cleaning solution used for cleaning a silicon surface and methods of fabricating a semiconductor device using the same are also provided. The cleaning solution may include 0.01 to 1 wt % of fluoric acid, 20 to 50 wt % of oxidizer and 50 to 80 wt % of water. The cleaning solution may further include 1 to 20 wt % of acetic acid. The cleaning solution may be used to clean a silicon surface exposed during fabrication processes of a semiconductor device. The cleaning solution may reduce damage of other material layers (e.g., a tungsten layer or a silicon oxide layer) and enable the silicon surface to be selectively etched.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: February 1, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yong Kim, Chang-Ki Hong, Woo-Gwan Shim
  • Patent number: 7871471
    Abstract: It is intended to prevent an increase in the quantity of particles on a test-piece substrate having undergone processing executed at a low temperature equal to or lower than 0° C. In an inspection method adopted when inspecting the state inside a processing chamber by measuring the quantity of particles on a test-piece substrate, i.e., a test-piece wafer, the test-piece wafer W having undergone a specific type of test processing inside the processing chamber is carried out into a transfer chamber via a loadlock chamber after holding it in the loadlock chamber over a predetermined length of time while delivering a dried inert gas into the loadlock chamber. The predetermined length of time is set to a value at which the increase in the quantity of particles on the test-piece wafer can be kept down at least within an acceptable range.
    Type: Grant
    Filed: January 31, 2008
    Date of Patent: January 18, 2011
    Assignee: Tokyo Electron Limited
    Inventor: Yoshiyuki Kato
  • Patent number: 7851427
    Abstract: Resist stripping agents, useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits with reduced metal etch rates, particularly copper etch rates, are provided with methods for their use. The preferred stripping agents contain low concentrations of a copper salt with or without an added amine to improve solubility of the salt. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods.
    Type: Grant
    Filed: February 1, 2010
    Date of Patent: December 14, 2010
    Assignee: Dynaloy, LLC
    Inventors: Kimberly Dona Pollard, Michael T. Phenis
  • Patent number: 7846266
    Abstract: Cleaning and reclaiming nano-imprint templates using environment friendly methods and systems is disclosed. A template may be cleaned by a combination of exposure to activated gaseous species followed by rinsing with oxygenated or hydrogenated DI water and exposure to reactive plasma to remove organic contaminant. Contaminant may be removed by forming a coating film of a water soluble polymer on the template and then peeling off the coating film. Organic residue from the film may be removed using oxygenated plasma.
    Type: Grant
    Filed: February 17, 2006
    Date of Patent: December 7, 2010
    Assignee: KLA-Tencor Technologies Corporation
    Inventor: Tony Dibiase
  • Patent number: 7846257
    Abstract: The substrate processing apparatus includes a plurality of processing chambers. A given processing chamber is cleaned by first executing first processing during which voltage application control is executed to control a voltage applied to an electrostatic chuck based upon first processing voltage application information provided for the particular processing chamber while drawing an inert gas into the processing chamber and evacuating the processing chamber sustaining therein low pressure conditions therein and then executing second processing during which voltage application control is executed to control the voltage application to the electrostatic chuck based upon second processing voltage application information for the processing chamber while drawing in the inert gas and evacuating the processing chamber, the internal pressure of which is set to a high level.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: December 7, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Hiroshi Nakamura, Kiyohito Iijima
  • Patent number: 7838482
    Abstract: The present invention relates to a CMP polishing slurry, comprising cerium oxide particles, a dispersing agent, a water-soluble polymer and water, wherein the water-soluble polymer is a compound having a skeleton of any one of an N-mono-substituted product and an N,N-di-substituted product of any one selected from the group consisting of acrylamide, methacrylamide and ?-substituted products thereof. The amount of the water-soluble polymer is preferably in the range of 0.01 part or more by weight and 10 parts or less by weight for 100 parts by weight of the polishing slurry. Thus it is possible to provide a polishing slurry and a polishing method which make it possible to polish a film made of silicon oxide or the like effectively and rapidly and further control the process therefor easily in CMP technique for flattening an interlayer insulating film, a BPSG film, an insulator film for shallow trench isolation, and other films.
    Type: Grant
    Filed: January 30, 2004
    Date of Patent: November 23, 2010
    Assignee: Hitachi Chemical Co. Ltd.
    Inventors: Masato Fukasawa, Masato Yoshida, Naoyuki Koyama, Yuto Ootsuki, Chiaki Yamagishi, Kazuhiro Enomoto, Kouji Haga, Yasushi Kurata
  • Publication number: 20100288728
    Abstract: There are provided an apparatus and method for processing a substrate. By using the apparatus and method, plasma processing can be individually performed on each of edge and rear regions of a substrate in a single chamber. The apparatus includes a chamber providing a reaction space; a stage installed in the chamber; a plasma shielding unit installed opposite to the stage in the chamber; a support unit for supporting a substrate between the stage and the plasma shielding unit; a first supply pipe provided at the stage to supply a reaction or non-reaction gas to one surface of the substrate; and second and third supply pipes provided at the plasma shielding unit, the second supply pipe supplying a reaction gas to the other surface of the substrate, the third supply pipe supplying a non-reaction gas to the other surface.
    Type: Application
    Filed: December 10, 2008
    Publication date: November 18, 2010
    Applicant: CHARM ENGINEERING CO., LTD.
    Inventors: Young Ki Han, Young Soo Seo
  • Patent number: 7824505
    Abstract: A method of removing a mask and addressing interfacial carbon chemisorbed in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. The dry stripping process is performed to remove the mask on the semiconductor wafer. The semiconductor wafer is then subjected to a cleaning solution to perform a cleaning process to remove particles on the surface of the semiconductor wafer and to address the interfacial carbon. The cleaning solution being either water containing ozone (O3) and ammonia (NH3), or a solution of hot phosphoric acid (H3PO4).
    Type: Grant
    Filed: July 26, 2006
    Date of Patent: November 2, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Niraj Rana, Kevin R. Shea
  • Patent number: 7824499
    Abstract: The present invention provides a method for in-situ cleaning of walls of a reaction chamber, e.g. reactive ion etching chamber, to remove contamination, e.g. copper comprising contamination from the walls. The method comprises converting the contamination, e.g. copper comprising contamination into a halide compound, e.g. copper halide compound and exposing the halide compound, e.g. copper halide compound to a photon comprising ambient, thereby initiating formation of volatile halide products, e.g. volatile copper halide products. The method furthermore comprises removing the volatile halide products, e.g. volatile copper halide products from the reaction chamber to avoid saturation of the volatile halide products, e.g. volatile copper halide products in the reaction chamber in order to avoid re-deposition of the volatile halide products, e.g. volatile copper halide products to the walls of the reaction chamber.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: November 2, 2010
    Assignees: IMEC, Katholieke Universiteit Leuven
    Inventor: Dries Dictus
  • Patent number: 7819981
    Abstract: A method and apparatus for cleaning residue from components of an ion source region of an ion implanter used in the fabrication of microelectronic devices. To effectively remove residue, the components are contacted with a gas-phase reactive halide composition for sufficient time and under sufficient conditions to at least partially remove the residue. The gas-phase reactive halide composition is chosen to react selectively with the residue, while not reacting with the components of the ion source region or the vacuum chamber.
    Type: Grant
    Filed: October 26, 2004
    Date of Patent: October 26, 2010
    Assignee: Advanced Technology Materials, Inc.
    Inventors: Frank DiMeo, Jr., James Dietz, W. Karl Olander, Robert Kaim, Steven E. Bishop, Jeffrey W. Neuner, Jose I. Arno
  • Patent number: 7819979
    Abstract: A method and system for providing a magnetic structure that includes at least one magnetic material is disclosed. The method and system include defining the magnetic structure. The magnetic structure also includes a top layer that is insensitive to an istroropic carbonyl reactive ion etch. The defining of the magnetic structure results in at least one artifact. The method and system further includes cleaning the at least one artifact using at least one isotropic carbonyl reactive ion etch.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: October 26, 2010
    Assignee: Western Digital (Fremont), LLC
    Inventors: Benjamin Chen, Yun-Fei Li, Hugh C. Hiner, Wei Zhang, Yingjian Chen
  • Patent number: 7806988
    Abstract: A method of removing a mask and addressing interfacial carbon chemisbored in a semiconductor wafer starts with placing the semiconductor wafer into a dry strip chamber. The dry stripping process is performed to remove the mask on the semiconductor wafer. The semiconductor wafer is then subjected to a cleaning solution to perform a cleaning process to remove particles on the surface of the semiconductor wafer and to address the interfacial carbon. The cleaning solution being either water containing ozone (O3) and ammonia (NH3), or a solution of hot phosphoric acid (H3PO4).
    Type: Grant
    Filed: September 28, 2004
    Date of Patent: October 5, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Niraj Rana, Kevin R. Shea
  • Patent number: 7799138
    Abstract: The method and apparatus of the embodiments of the present invention employ an in-situ particle decontamination technique that allows for such decontamination while a wafer is a vacuum tool or deposition chamber, thereby eliminating the need for another device for performing decontamination. This in-situ decontamination is effective for particle contamination resulting, for example, from tool resident mechanical component. Furthermore, particle decontamination is performed in the presence of plasma, having a potential for helping to maximize a “self bias” voltage, under RF conditions, and is integrated into the vacuum process.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: September 21, 2010
    Assignee: Hitachi Global Storage Technologies Netherlands
    Inventors: Paul Alejon Fontejon, Jr., Yunxiao Gao, Yinshi Liu, Ning Shi
  • Patent number: 7789965
    Abstract: A method of cleaning a UV irradiation chamber includes steps of: (i) after completion of irradiating a substrate with UV light transmitted through an optical transmitted window provided in the UV irradiation chamber, generating radical species of a cleaning gas outside the UV irradiation chamber; and (ii) introducing the radical species from the outside of the UV irradiation chamber into the UV irradiation chamber, thereby cleaning the optical transmitted window.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: September 7, 2010
    Assignee: ASM Japan K.K.
    Inventors: Kiyohiro Matsushita, Hideaki Fukuda, Kenichi Kagami
  • Patent number: 7780793
    Abstract: Embodiments described herein provide methods for removing native oxide surfaces on substrates while simultaneously passivating the underlying substrate surface. In one embodiment, a method is provided which includes positioning a substrate containing an oxide layer within a processing chamber, adjusting a first temperature of the substrate to about 80° C. or less, generating a cleaning plasma from a gas mixture within the processing chamber, such that the gas mixture contains ammonia and nitrogen trifluoride having an NH3/NF3 molar ratio of about 10 or greater, and condensing the cleaning plasma onto the substrate. A thin film, containing ammonium hexafluorosilicate, is formed in part, from the native oxide during a plasma clean process. The method further includes heating the substrate to a second temperature of about 100° C. or greater within the processing chamber while removing the thin film from the substrate and forming a passivation surface thereon.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: August 24, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Haichun Yang, Xinliang Lu, Chien-Teh Kao, Mei Chang
  • Patent number: 7776755
    Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first etching process to the substrate to remove a polysilicon layer and a metal gate layer on the substrate; applying a diluted hydrofluoric acid (HF) to the substrate to remove polymeric residue; thereafter applying to the substrate with a cleaning solution including hydrochloride (HCl), hydrogen peroxide (H2O2) and water (H2O); applying a wet etching process diluted hydrochloride (HCl) to the substrate to remove a capping layer; and applying to the substrate with a second etching process to remove a high k dielectric material layer.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: August 17, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jr Jung Lin, Yih-Ann Lin, Ryan Chia-Jen Chen
  • Patent number: 7771541
    Abstract: A method of removing and/or reducing undesirable contaminants removes residues including graphitic layers, fluorinate layers, calcium sulfate (CaSO4) particles, tin oxides and organotin, from a chip passivation layer surface. The method uses a plasma process with an argon and oxygen mixture with optimized plasma parameters to remove both the graphitic and fluorinated layers and to reduce the level of the inorganic/tin oxides/organotin residue from an integrated circuit wafer while keeping the re-deposition of metallic compounds is negligible. This invention discloses the plasma processes that organics are not re-deposited from polymers to solder ball surfaces and tin oxide thickness does not increase on solder balls. The ratio of argon/oxygen is from about 50% to about 99% Ar and about 1% to about 50% O2 by volume. Incoming wafers, after treatment, are then diced to form individual chips that are employed to produce flip chip plastic ball grid array packages.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: August 10, 2010
    Assignee: International Business Machines Corporation
    Inventors: Claude Blais, Eric Duchesne, Kang-Wook Lee, Sylvain Ouimet, Gerald J. Scilla
  • Patent number: 7767024
    Abstract: In one embodiment, a method for removing native oxides from a substrate surface is provided which includes supporting a substrate containing silicon oxide within a processing chamber, generating a plasma of reactive species from a gas mixture within the processing chamber, cooling the substrate to a first temperature of less than about 65° C. within the processing chamber, and directing the reactive species to the cooled substrate to react with the silicon oxide thereon while forming a film on the substrate. The film usually contains ammonium hexafluorosilicate. The method further provides positioning the substrate in close proximity to a gas distribution plate, and heating the substrate to a second temperature of about 100° C. or greater within the processing chamber to sublimate or remove the film. The gas mixture may contain ammonia, nitrogen trifluoride, and a carrier gas.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 3, 2010
    Assignee: Appplied Materials, Inc.
    Inventors: Chien-Teh Kao, Jing-Pei (Connie) Chou, Chiukin (Steven) Lai, Sal Umotoy, Joel M. Huston, Son Trinh, Mei Chang, Xiaoxiong (John) Yuan, Yu Chang, Xinliang Lu, Wei W. Wang, See-Eng Phan
  • Publication number: 20100184294
    Abstract: In a method of manufacturing a semiconductor device, a substrate is loaded to a process chamber having, unit process sections in which unit processes are performed, respectively. The unit processes are performed on the substrate independently from one another at the unit process sections under a respective process pressure. The substrate sequentially undergoes the unit processes at the respective unit process section of the process chamber. Cleaning processes are individually performed to the unit process sections, respectively, when the substrate is transferred from each of the unit process sections and no substrate is positioned at the unit process sections. Accordingly, the process defects of the process units may be sufficiently prevented and the operation period of the manufacturing apparatus is sufficiently elongated.
    Type: Application
    Filed: January 15, 2010
    Publication date: July 22, 2010
    Inventors: Jin-Ho Park, Gil-Heyun CHOI, Byung-Lyul PARK, Jong-Myeong LEE, Zung-Sun CHOI, Hye-Kyung JUNG
  • Publication number: 20100170530
    Abstract: A method for cleaning a semiconductor equipment is provided. First, a first cleaning step is performed to the process chamber. The first cleaning step includes conducting a cleaning gas into the process chamber via a short processing gas injector for generating a plasma of the cleaning gas in the process chamber. Then, a cleaning step is performed to a long cleaning gas injector. The cleaning step performed to the long cleaning gas injector includes conducting the cleaning gas into the process chamber via the long processing gas injector. Then, a second cleaning step is performed to the process chamber. The second cleaning step includes conducting the plasma of the cleaning gas into the process chamber via the short processing gas injector.
    Type: Application
    Filed: January 6, 2009
    Publication date: July 8, 2010
    Applicant: United Microelectronics Corp.
    Inventors: Chong-Tat Lee, Jui-Lin Tang, Chee-Thim Loh, Kok-Poh Chong
  • Patent number: 7740768
    Abstract: A method and apparatus for cleaning a wafer. The wafer is heated and moved to a processing station within the apparatus that has a platen either permanently in a platen down position or is transferable from a platen up position to the platen down position. The wafer is positioned over the platen so as not to contact the platen and provide a gap between the platen and wafer. The gap may be generated by positioning the platen in a platen down position. A plasma flows into the gap to enable the simultaneous removal of material from the wafer front side, backside and edges. The apparatus may include a single processing station having the gap residing therein, or the apparatus may include a plurality of processing stations, each capable of forming the gap therein for simultaneously removing additional material from the wafer front side, backside and edges.
    Type: Grant
    Filed: October 12, 2006
    Date of Patent: June 22, 2010
    Assignee: Novellus Systems, Inc.
    Inventors: Haruhiro H Goto, David Cheung
  • Publication number: 20100139554
    Abstract: Methods and apparatus for forming gallium nitride and gallium aluminum nitride films, such as gallium nitride and gallium aluminum nitride epitaxial layers on a substrate are provided, including providing a substrate; and exposing the substrate to gallium vapor and an NH3 plasma so as to form a gallium nitride epitaxial layer on at least a portion of the substrate.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 10, 2010
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Morteza Farnia, Mehran Moalem
  • Patent number: 7732342
    Abstract: Compressive stress in a film of a semiconductor device may be controlled utilizing one or more techniques, employed alone or in combination. A first set of embodiments increase silicon nitride compressive stress by adding hydrogen to the deposition chemistry, and reduce defects in a device fabricated with a high compressive stress silicon nitride film formed in the presence of hydrogen gas. A silicon nitride film may comprise an initiation layer formed in the absence of a hydrogen gas flow, underlying a high stress nitride layer formed in the presence of a hydrogen gas flow. A silicon nitride film formed in accordance with an embodiment of the present invention may exhibit a compressive stress of 2.8 GPa or higher.
    Type: Grant
    Filed: April 5, 2006
    Date of Patent: June 8, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Mihaela Balseanu, Li-Qun Xia, Vladimir Zubkov, Mei-Yee Shek, Isabelita Rolfox, Hichem M'Saad