Abstract: A laminate comprising a substrate; and a plating-forming layer disposed on at least one surface of both surfaces of the substrate and containing a thermoplastic resin and a plating catalyst, wherein the plating-forming layer further satisfies conditions of the following (1) and/or (2), (1) the plating-forming layer contains a dispersing agent for dispersing the plating catalyst (2) an abundance of the plating catalyst on a surface side of the plating-forming layer is higher than an abundance of the plating catalyst on the substrate side of the plating-forming layer.

Abstract: The present disclosure relates to a fluororesin substrate laminate for a high-frequency circuit, the fluororesin substrate laminate including a fluororesin substrate and an adhesive layer provided on the fluororesin substrate, wherein the adhesive layer includes a resin composition containing: (A) a maleimide compound having a saturated or unsaturated divalent hydrocarbon group; and (B) an aromatic maleimide compound.

Abstract: A package circuit structure includes a multilayer circuit board, an electronic component, and an insulating layer. The multilayer circuit board includes a metal portion and an opening. The opening is extending from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side. A bottom of the opening is sealed by the metal portion. The electronic component is received in the opening and adhered to the metal portion. The electronic component is electrically connected to the multilayer circuit board and encapsulated in the opening by the insulating layer. A method for manufacturing the package circuit structure is also provided.

Abstract: A thermoelectric module includes: an electrode; a double layer stacked on a thermoelectric pellet; and a solder layer interposed between the double layer and the electrode to bond the double layer to the electrode, the solder layer containing a Sn—Cu-based alloy. The solder layer is formed to have an interface with one of the double layer and the electrode and has at least one ? layer having an ? phase (Cu3Sn).

Abstract: In a preparatory process of a method of manufacturing a multilayer substrate, an insulating substrate is prepared, with a conductor pattern formed only on one surface of the insulating substrate. At that time, the conductor pattern is constituted of the Cu element, a Ni layer is formed on the surface of the conductor pattern that is on the side of the insulating substrate. In a first forming process, a via hole having the conductor pattern as the bottom thereof is formed in the insulating substrate. At that time, the Ni layer that is in the area of the bottom is removed. In a filling process, a conductive paste is filled in the interior of the via hole. In a second forming process, a stacked body is formed by stacking a plurality of the insulating substrates. In a third forming process, the stacked body is heated while being subjected to pressure.

Abstract: A manufacturing apparatus of a wiring board includes: a fixed die; a movable die configured to abut with the fixed die so as to form a cavity in which a resin substrate having a wiring gutter is to be molded; and an injection machine configured to inject molten resin into the cavity via the fixed die. The movable die includes a movable main mold, and a movable core having a nested structure in which the movable core is slidably accommodated in the movable main mold. A wall surface of the movable core has a projection portion that molds the wiring gutter. An injector configured to inject molten metal into the wiring gutter via the projection portion is provided inside the movable core.

Abstract: A method of manufacturing a semiconductor package includes mounting and electrically connecting a semiconductor die to a substrate. The semiconductor die and the substrate are encapsulated to form an encapsulation. Via holes are laser-ablated through the encapsulation and conductive material is deposited within the via holes to form vias. A first buildup dielectric layer is formed on the encapsulation. Laser-ablated artifacts are laser-ablated in the first buildup layer. The laser-ablated artifacts in the first buildup layer are filled with a first metal layer to form a first electrically conductive pattern in the first build up layer. The operations of forming a buildup layer, forming laser-ablated artifacts in the buildup layer, and filling the laser-ablated artifacts with an electrically conductive material to form an electrically conductive pattern can be performed any one of a number of times to achieve the desired redistribution.

Abstract: A method of manufacturing an electronic device. For example and without limitation, various aspects of the present disclosure provide a method of manufacturing an electronic device that comprises a die comprising a circuit side and a second die side opposite the circuit side, a through hole in the die that extends between the second side of the die and the circuit side of the die, an insulating layer coupled to the inner wall of the through hole, a through electrode inside of the insulating layer, a dielectric layer coupled to the second side of the die, and a conductive pad coupled to the through electrode. The through electrode and the insulating layer may, for example, extend substantially the same distance from the second side of the die.

Abstract: A circuit board electrically connected to a chip includes a substrate and a circuit layer. A first conductive line of the circuit layer includes a main line and a branch lead connected with each other. The branch lead provided to increase lead quantity for bonding with the chip includes an extension part and a bonding part which is used for bonding a bump of the chip. During thermal compression, gaps existing between the extension part and the main line and between the bonding part and the main line can prevent solder on the main line from flowing toward the bump and overflowing from the branch lead.

Abstract: Optical protection devices are provided for protecting client equipment in an optical communication system. According to one implementation, a protection device includes a passive optical coupler configured to combine optical signals from a plurality of input paths, where the passive optical coupler is further configured to provide the output signals along an optical output path. The exemplary protection device further includes one or more interrupters configured to allow at most one input from a plurality of optical inputs via the plurality of input paths to be provided to the passive optical coupler at one time.

Abstract: A transmission line includes, in a stacked insulator in which insulator layers are stacked, a first transmission line portion including a first ground conductor pattern, a second ground conductor pattern, and a first signal conductor pattern, and a second transmission line portion including a third ground conductor pattern, a fourth ground conductor pattern, and a second signal conductor pattern. The first signal conductor pattern extends along the second signal conductor pattern. The first ground conductor pattern and the third ground conductor pattern are provided on different insulator layers and at least partially overlap each other in a plan view.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate, an electrical connection structure extending upwardly from an upper surface of the substrate by a first height, and a contact pad electrically disposed on the upper surface of the substrate. The contact pad has a solder-wettable surface with an area configured to support a solder ball having a second height at least twice the first height. The semiconductor device structure further includes a fuse element with a first end electrically coupled to the electrical connection structure and a second end electrically coupled to the contact pad.

Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.

Abstract: Disclosed herein is an electric double layer device including a urethane potting unit (50) for filling the gap between a portion of a first terminal (21) that is exposed out of a rubber cap (40) and a first through hole (41) and the gap between a portion of a second terminal (22) that is exposed out of the rubber cap and a second through hole (42), wherein an aluminum terminal (A) constituting each of the first terminal (21) and the second terminal (22) is anodized such that an aluminum oxide film (Al) is formed on the aluminum terminal, whereby the lifespan of the electric double layer device is relatively increased.

Abstract: A multilayer printed circuit board includes a first dielectric layer and a second dielectric layer, each layer having a top surface and a bottom surface. The first dielectric layer is positioned above the second dielectric layer with the bottom surface of the first dielectric layer facing the top surface of the second dielectric layer. The top surface of the second dielectric layer has a conductive trace. The second dielectric layer has a through-hole that extends through the conductive trace. The multilayer printed circuit board includes an inverted pad interface structure including an inverted pad provided on the bottom surface of the first dielectric layer, a first solder layer provided on a surface of the inverted pad, a second solder layer provided on the conductive trace, and a copper wire positioned within the through-hole to provide the vertical and electrical connection with the conductive trace.

Abstract: A PWB may be drilled forming a via. The via may expose one or more internal portions of a core layer, a prepreg layer, and an anti-plate coating. A seed material may then be applied from a top portion of the PWB to the via, forming a seed layer in the via, the seed material not adhering to the anti-plate coating. Electroless metal may then be applied from the top portion of the PWB to the via, forming an electroless plate layer that adheres to the seed layer. Electrolytic copper may then be applied from the top portion of the PWB to the via, forming a copper layer that adheres to the electroless plate layer. A bottom portion of the electroless plate layer may then be removed.

Abstract: The present invention is to provide an anisotropic conductive film that excels in dispersing conductive particles and trapping the particles, and maintains conduction reliability even between narrow-pitched terminals. By a method for manufacturing an anisotropic conductive film containing conductive particles, the conductive particles are buried in grooves in a sheet having the grooves regularly formed in the same direction, the conductive particles are arranged, a first resin film having a thermo-setting resin layer formed on a stretchable base film is laminated on the surface of the sheet on the side of the grooves to transfer and attach the conductive particles to the first resin film, the first resin film is uniaxially stretched in a direction other than the direction perpendicular to the array direction of the conductive particles, and a second resin film is laminated.

Abstract: A process of utilizing heat-shielding microcapsules to protect a temperature sensitive component includes applying a shielding layer including heat-shielding microcapsules to a temperature sensitive component disposed on a surface of a printed circuit board. The process also includes performing a processing operation on the printed circuit board according to a set of process parameters. The set of process parameters specify a particular period of time (tL) that a processing temperature (TP) is to be maintained in excess of a liquidous temperature (TL) for solder reflow. During the processing operation, the heat-shielding microcapsules absorb heat to reduce a time above liquidous (TAL) of the temperature sensitive component.

Abstract: An example device includes a silicon substrate having a first substrate surface and a second substrate surface; a plurality of layers associated with one or more electronic components of an integrated circuit (IC), where the plurality of layers are deposited on the second substrate surface; a lithium-based battery having a plurality of battery layers deposited on the first substrate surface of the silicon substrate, where the lithium-based battery includes an anode current collector and a cathode current collector; a first through-silicon via (TSV) passing through the silicon substrate and providing an electrical connection between the anode current collector and the plurality of layers associated with the one or more electronic components of the IC; and a second TSV passing through the silicon substrate and providing an electrical connection between the cathode current collector and the plurality of layers associated with the one or more electronic components of the IC.

Abstract: A display apparatus includes a substrate having a bending area between a first area and a second area, wherein the substrate is bent in the bending area, a display portion on an upper surface of the substrate and positioned in the first area, and a protective film on a lower surface of the substrate and including a protective film base and an adhesive layer. The protective film base includes a plurality of cavities.

Abstract: Disclosed is a resin composition, comprising the following components: (A) 100 parts by weight of an epoxy resin; (B) 10 to 60 parts by weight of a diamino diphenyl ether type benzoxazine resin having a softening point of 40° C. to 140° C.; (C) 10 to 40 parts by weight of a co-hardener; and (D) 10 to 40 parts by weight of a flame retardant which comprises (d1) a high melting point flame retardant with a melting point of greater than 260° C. or (d2) a metal phosphinate flame retardant, wherein the metal is selected from Group IIIA elements. Also disclosed is an article of manufacture obtained from the resin composition and a use thereof. Accordingly, the demands of high frequency application can be met, and a balance of low thermal expansion, high thermal resistance and low warpage in the system can be struck.

Abstract: This invention provides an electronic device with improved reliability. The electronic device has a wiring board with a back-surface ground pattern formed at the back surface of the board. The back-surface ground pattern is provided with a notch overlapping a region of an upper wiring layer at which a board member is exposed and which is encircled by a wide pattern, the notch permitting the release of water vapor from the region.

Abstract: [Problem] To allow an efficient sheet layout of a flexible printed circuit board having a plurality of cable sections extending in different directions and to improve a yield.

Abstract: Provided are an epoxy resin composition for manufacturing a fiber reinforced composite material having excellent curability allowing for curing in a short time, and excellent storage stability and heat resistance, and a prepreg and a fiber reinforced composite material using the same. The epoxy resin composition includes at least an epoxy resin [A], a curing agent [B] having an exothermic onset temperature higher than the exothermic onset temperature of a component [C], as measured by a differential scanning calorimeter, and the component [C] contains a compound represented by a particular formula (a), and a prepreg and a fiber reinforced composite material using the same.

Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a guide pattern disposed adjacent to a wall of the recess portion and disposed in the frame. An edge of the bottom surface of the recess portion has a groove portion.

Abstract: A semiconductor substrate includes a dielectric layer, a heat dissipation structure and a first patterned conductive layer. The dielectric layer has a surface. The heat dissipation structure is surrounded by the dielectric layer. The heat dissipation structure defines a space and includes a liquid in the space. The first patterned conductive layer is disposed adjacent to the surface of the dielectric layer and thermally connected with the heat dissipation structure.

Abstract: Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed.

Abstract: The present invention discloses a assembling method, a manufacturing method, an device and an electronic apparatus of flip-die. The method for assembling a flip-die, comprises: temporarily bonding the flip-die onto a laser-transparent first substrate, wherein bumps of the flip-die are located on the side of the flip-die opposite to the first substrate; aligning the bumps with pads on a receiving substrate; irradiating the original substrate with laser from the first substrate side to lift-off the flip-die from the first substrate; and attaching the flip-die on the receiving substrate. A faster assembly rate can be achieved by using the present invention. A smaller chip size can be achieved by using the present invention. A lower profile can be achieved by using the present invention.

Abstract: A method for manufacturing a power-module substrate includes a lamination step of laminating a ceramic member and a copper member through an active metal material and a filler metal having a melting point of 710° C. or lower, and a heating treatment step of heating the ceramic member and the copper member laminated together.

Abstract: Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded by an insulating adhesive.

Abstract: A chip package includes a flexible substrate, a chip, a pressure-proof member and a reinforcement sheet. The chip and the pressure-proof member are located on a first surface of the flexible substrate, and the reinforcement sheet is located on a second surface of the flexible substrate. The pressure-proof member at least includes a pair of pressure-proof ribs which are located outside of the chip oppositely. The pressure-proof ribs located outside the chip can protect the chip from the damage caused by the pressure of other component (e.g. curved panel) except the chip package.

Abstract: Method of constructing a printed circuit board, preferably with one lamination step: constructing multilayer cores wherein each multilayer core includes a sheet of cured dielectric material having a layer of metal on each side of the sheet of cured dielectric material; patterning each layer of metal to form wiring traces; forming a sheet of uncured dielectric material; embedding a solder element in the sheet of the uncured dielectric material; alternately stacking the multilayer cores with the sheets of uncured dielectric material, the sheet of the uncured dielectric material having the embedded solder element positioned so as to be aligned with wiring traces in adjacent layers of metal in adjacent multilayer cores; heating the solder element so as to cause the solder element to melt; and hot pressing the stack of multilayer cores and sheets of uncured dielectric material to cause curing of the sheets of uncured dielectric material.

Abstract: In order to easily inspect a dispersion state of conductive particles in such an anisotropic conductive film that the conductive particles are dispersed even at high density, linear lines including no conductive particle in a plan view of an anisotropic conductive film including an insulating adhesive layer and conductive particles dispersed in the insulating adhesive layer are allowed to exist at predetermined intervals. Specifically, the conductive particles are disposed in a lattice so as to be arranged in a first arrangement direction and a second arrangement direction, and the disappearance lines are inclined relative to the first arrangement direction or the second arrangement direction.

Abstract: A method for producing a ceramic circuit board comprising the steps of bonding a metal sheet to a ceramic substrate via a brazing material containing Ag to form a bonded body; etching the bonded metal sheet to form a circuit pattern; and removing an unnecessary brazing material from the substrate provided with the circuit pattern, by etching with an acidic solution comprising carboxylic acid and/or carboxylate and hydrogen peroxide.

Abstract: Provided is a circuit board interconnection structure including: a first circuit board including a first substrate and a first electrode formed on a surface of the first substrate; a second circuit board including a second substrate and a second electrode formed on a surface of the second substrate; one or more joining portions formed of a metal-containing conductive material for joining the first and second electrodes, interposed between the first and second electrodes; and a reinforcing resin portion for reinforcing the one or more joining portions. The first electrode is a transparent electrode including a metal oxide film. A first abutting portion of the joining portion abutting the first electrode, is formed by adhesional wetting of the first electrode with the conductive material.

Abstract: A method of fabricating a MEMS device includes depositing an expandable material into a first recess of a cap wafer. The cap wafer includes a plurality of walls that surround and define the first recess and a second recess. The cap wafer is bonded to a MEMS wafer including a first MEMS device and a second MEMS device. The first MEMS device is encapsulated in the first recess, and the second MEMS device is encapsulated in the second recess. The expandable material is then heated to at least an activation temperature to cause the expandable material to expand after the first recess has been sealed. The expansion of the expandable material causes a reduction in volume of the first recess.

Abstract: The embodiments herein relate to a method for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The method involves the step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.

Abstract: A thermosetting adhesive composition and thermosetting adhesive sheet capable of obtaining stable conductivity even in high-temperature environments or high-temperature/high-humidity environments are provided. The thermosetting adhesive sheet comprises an acrylic copolymer obtained by copolymerizing 55 to 80 wt % of alkyl (meth)acrylate, 15 to 30 wt % of acrylonitrile, and 5 to 15 wt % of glycidyl methacrylate; an epoxy resin; an epoxy resin curing agent; and a dendritic conductive filler having a tap density of 1.0 to 1.8 g/cm3. Thereby, thermal expansion after curing is suppressed, and electrical contacts of the conductive filler are increased, allowing stable conductivity to be obtained even in high-temperature environments or high-temperature/high-humidity environments.

Abstract: A composite, a high-frequency circuit substrate using the same and method thereof are discussed. The composite includes the following solid components: a DOPO (9,10-dihydro-9-oxa-10-phosphaphenanthrene 10-oxide) derivative compound of 10-70 wt %, a curing agent of 10-50 wt %, one or more epoxy of 10-90 wt % and an inorganic filling material of 10-40 wt %. The non-halogen low dielectric epoxy composite uses a high-purity DOPO (9,10-dihydro-9-oxa-10-phosphaphenanthrene 10-oxide) derivative as tiny particles dispersing in the composite. The crosslinking yield of the composite is not reduced, while the heat resistance and flame retardancy are increased. The prepreg and copper foil covered laminate for use in printed circuit board, made from the epoxy composite, has great dielectric property and high glass transition temperature (GTT), satisfying the need of high frequency in electronic signal transmission and high speed in data processing of the industry of copper covered printed circuit board.

Abstract: The present invention relates to an adhesive resin composition for bonding semiconductors, including: a (meth)acrylate-based resin including more than 17% by weight of (meth)acrylate-based repeating units containing epoxy-based functional groups; an epoxy resin having a softening point of more than 70° C.; and a phenol resin having a softening point of more than 105° C., wherein the weight ratio of the (meth)acrylate-based resin is 0.48 to 0.65 relative to the total weight of the (meth)acrylate-based resin, the epoxy resin, and the phenol resin, an adhesive film for semiconductors obtained from the resin composition, a dicing die-bonding film including an adhesive layer that includes the adhesive film for semiconductors, a semiconductor wafer including the dicing die-bonding film, and a dicing method for the semiconductor wafer using the dicing die-bonding film.

Abstract: An anisotropic conductive film whereby electrically conductive particles can be sufficiently captured at each connection terminal while suppressing the occurrence of shorts and conduction reliability can be improved even in cases where connecting finely pitched connection terminals. The anisotropic conductive film has a structure in which electrically conductive particle units in which electrically conductive particles are arranged in a row, or electrically conductive particle units in which electrically conductive particles are arranged in a row and independent electrically conductive particles are disposed in a lattice form in an electrically insulating adhesive layer. The shortest distance La between electrically conductive particles selected from adjacent electrically conductive particle units and the independent electrically conductive particles is not less than 0.5 times the particle diameter of the electrically conductive particles.

Abstract: The wiring board of the present disclosure includes an insulating layer, and a wiring conductor existing so as to be adjacent to both main surfaces of the insulating layer; the insulating layer includes at least two particle-containing resin layers containing insulating particles in an insulating resin, and a particle-free resin layer formed of an insulating resin; and the particle-free resin layer is interposed between the particle-containing resin layers.

Abstract: A semiconductor device has a first semiconductor die disposed over a substrate. A plurality of composite interconnect structures are formed over the semiconductor die. The composite interconnect structures have a non-fusible conductive pillar and a fusible layer formed over the non-fusible conductive pillar. The fusible layer is reflowed to connect the first semiconductor die to a conductive layer of the substrate. The non-fusible conductive pillar does not melt during reflow eliminating a need to form a solder resist over the substrate. An encapsulant is deposited around the first semiconductor die and composite interconnect structures. The encapsulant flows between the active surface of the first semiconductor die and the substrate. A second semiconductor die is disposed over the substrate adjacent to the first semiconductor die. A heat spreader is disposed over the first semiconductor die. A portion of the encapsulant is removed to expose the heat spreader.

Abstract: In a charging station for charging a battery installed on an autonomously navigating utility vehicle equipped with a prime mover powered by the battery to travel about a working area delineated by a boundary wire, there are provided with a pair of charging terminals installed on the station to be capable of connecting with a pair of charging terminals installed on the vehicle, a first wire installed on the station at a location inside of the working area and being formed as a circular shape having a center, and a second wire installed on the station to be formed as a shape that is symmetrical with respect to a center line obtained by connecting a midpoint of the terminals and the center of the first wire.

Abstract: A wiring substrate includes a first wiring structure and a second wiring structure stacked thereon. The first wiring structure includes a first insulation layer and a via wiring extending through the first insulation layer. The second wiring structure includes a first wiring layer formed on the first insulation layer and the via wiring, and a first plane layer stacked on the first insulation layer and at least partially grid-shaped in a plan view to define second through holes. A second insulation layer is stacked on the first insulation layer to fill the second through holes and cover the first plane layer and the first wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The second through holes each include a lower open end and an upper open end having a smaller open width than the lower open end.

Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.

Abstract: The present invention aims to improve the signal transmission characteristics by shortening the length of the detour path of the return current. The present invention comprises a return current transmission path relative to a signal transmission path for transmitting signals. The signal transmission path includes a signal pad formed on a circuit board surface layer, and signal through-holes formed on the circuit board surface layer and a circuit board inner layer and connected to the signal pad. The return current transmission path includes a ground pad formed on the circuit board surface layer, and a plurality of ground through-holes formed on the circuit board surface layer and the circuit board inner layer and connected to the ground pad and a ground layer of the circuit board inner layer. Each of the ground through-holes is arranged by being separated on either side of the ground pad.

Abstract: In a semi-finished product for the production of a printed circuit board with at least one recessed electronic component having at least one conductive layer structured to provide a connector pad for an electronic component, fan-out lines connected to the connector pad and further to provide at least one laser-stop device encompassing the connector pad, wherein the laser-stop device has at least one passage for passing-through the fan-out lines, the semi-finished product further comprises at least one cap layer applied to the conductive layer, the at least one cap layer having an opening in registration with each passage.

Abstract: A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.

Abstract: Systems and methods for providing input component assemblies for dome switches are provided. In some embodiments, an input component assembly may include a contact area coupled to a circuit board for a switch, a conductive covering for enclosing the circuit board, and a dome positioned over the conductive covering, where the dome is operative to close at least one circuit of the switch when the dome is depressed towards the conductive covering.