Adhesive/bonding Patents (Class 174/259)
  • Patent number: 10383224
    Abstract: [Problem] To allow an efficient sheet layout of a flexible printed circuit board having a plurality of cable sections extending in different directions and to improve a yield.
    Type: Grant
    Filed: September 29, 2015
    Date of Patent: August 13, 2019
    Assignee: NIPPON MEKTRON, LTD.
    Inventor: Fumihiko Matsuda
  • Patent number: 10347586
    Abstract: A fan-out semiconductor package includes: a frame including insulating layers, wiring layers, and connection via layers, and having a recess portion and a stopper layer disposed on a bottom surface of the recess portion; a semiconductor chip having connection pads and disposed in the recess portion so that an inactive surface is disposed on the stopper layer; an encapsulant covering at least portions of the semiconductor chip and filling at least portions of the recess portion; a connection member disposed on the frame and an active surface of the semiconductor chip and including a redistribution layer electrically connecting the wiring layers and the connection pads to each other; and a guide pattern disposed adjacent to a wall of the recess portion and disposed in the frame. An edge of the bottom surface of the recess portion has a groove portion.
    Type: Grant
    Filed: May 22, 2018
    Date of Patent: July 9, 2019
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jin Su Kim, Jeong Ho Lee, Shang Hoon Seo, Bong Ju Cho
  • Patent number: 10344132
    Abstract: Provided are an epoxy resin composition for manufacturing a fiber reinforced composite material having excellent curability allowing for curing in a short time, and excellent storage stability and heat resistance, and a prepreg and a fiber reinforced composite material using the same. The epoxy resin composition includes at least an epoxy resin [A], a curing agent [B] having an exothermic onset temperature higher than the exothermic onset temperature of a component [C], as measured by a differential scanning calorimeter, and the component [C] contains a compound represented by a particular formula (a), and a prepreg and a fiber reinforced composite material using the same.
    Type: Grant
    Filed: January 6, 2017
    Date of Patent: July 9, 2019
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Jun Misumi, Hiroaki Sakata
  • Patent number: 10340212
    Abstract: A semiconductor substrate includes a dielectric layer, a heat dissipation structure and a first patterned conductive layer. The dielectric layer has a surface. The heat dissipation structure is surrounded by the dielectric layer. The heat dissipation structure defines a space and includes a liquid in the space. The first patterned conductive layer is disposed adjacent to the surface of the dielectric layer and thermally connected with the heat dissipation structure.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: July 2, 2019
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Cheng Lee, Yu-Lin Shih
  • Patent number: 10290557
    Abstract: Embodiments of the present disclosure describe selective metallization of an integrated circuit (IC) substrate. In one embodiment, an integrated circuit (IC) substrate may include a dielectric material and metal crystals having a polyhedral shape dispersed in the dielectric material and bonded with a ligand that is to ablate when exposed to laser light such that the metal crystals having the ablated ligand are activated to provide a catalyst for selective electroless deposition of a metal. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: May 14, 2019
    Assignee: Intel Corporation
    Inventors: Brandon C. Marin, Trina Ghosh Dastidar, Dilan Seneviratne, Yonggang Li, Sirisha Chava
  • Patent number: 10224307
    Abstract: The present invention discloses a assembling method, a manufacturing method, an device and an electronic apparatus of flip-die. The method for assembling a flip-die, comprises: temporarily bonding the flip-die onto a laser-transparent first substrate, wherein bumps of the flip-die are located on the side of the flip-die opposite to the first substrate; aligning the bumps with pads on a receiving substrate; irradiating the original substrate with laser from the first substrate side to lift-off the flip-die from the first substrate; and attaching the flip-die on the receiving substrate. A faster assembly rate can be achieved by using the present invention. A smaller chip size can be achieved by using the present invention. A lower profile can be achieved by using the present invention.
    Type: Grant
    Filed: July 14, 2015
    Date of Patent: March 5, 2019
    Assignee: GOERTEK, INC.
    Inventors: Quanbo Zou, Zhe Wang
  • Patent number: 10199237
    Abstract: A method for manufacturing a power-module substrate includes a lamination step of laminating a ceramic member and a copper member through an active metal material and a filler metal having a melting point of 710° C. or lower, and a heating treatment step of heating the ceramic member and the copper member laminated together.
    Type: Grant
    Filed: March 17, 2014
    Date of Patent: February 5, 2019
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Nobuyuki Terasaki, Yoshiyuki Nagatomo
  • Patent number: 10199358
    Abstract: Provided is a multilayer substrate obtained by laminating semiconductor substrates each having a trough electrode. The multilayer substrate has excellent conduction characteristics and can be manufactured at low cost. Conductive particles are each selectively present at a position where the through electrodes face each other as viewed in a plan view of the multilayer substrate. The multilayer substrate has a connection structure in which the facing through electrodes are connected by the conductive particles, and the semiconductor substrates each having the through electrode are bonded by an insulating adhesive.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: February 5, 2019
    Assignee: DEXERIALS CORPORATION
    Inventors: Yasushi Akutsu, Tomoyuki Ishimatsu
  • Patent number: 10168582
    Abstract: A chip package includes a flexible substrate, a chip, a pressure-proof member and a reinforcement sheet. The chip and the pressure-proof member are located on a first surface of the flexible substrate, and the reinforcement sheet is located on a second surface of the flexible substrate. The pressure-proof member at least includes a pair of pressure-proof ribs which are located outside of the chip oppositely. The pressure-proof ribs located outside the chip can protect the chip from the damage caused by the pressure of other component (e.g. curved panel) except the chip package.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: January 1, 2019
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Chun-Yang Su, Jhao-Shin Wang, Nian-Cih Yang, Xin-Wei Lo
  • Patent number: 10172244
    Abstract: Method of constructing a printed circuit board, preferably with one lamination step: constructing multilayer cores wherein each multilayer core includes a sheet of cured dielectric material having a layer of metal on each side of the sheet of cured dielectric material; patterning each layer of metal to form wiring traces; forming a sheet of uncured dielectric material; embedding a solder element in the sheet of the uncured dielectric material; alternately stacking the multilayer cores with the sheets of uncured dielectric material, the sheet of the uncured dielectric material having the embedded solder element positioned so as to be aligned with wiring traces in adjacent layers of metal in adjacent multilayer cores; heating the solder element so as to cause the solder element to melt; and hot pressing the stack of multilayer cores and sheets of uncured dielectric material to cause curing of the sheets of uncured dielectric material.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Matteo Cocchini, Kyle I. Giesen
  • Patent number: 10121756
    Abstract: In order to easily inspect a dispersion state of conductive particles in such an anisotropic conductive film that the conductive particles are dispersed even at high density, linear lines including no conductive particle in a plan view of an anisotropic conductive film including an insulating adhesive layer and conductive particles dispersed in the insulating adhesive layer are allowed to exist at predetermined intervals. Specifically, the conductive particles are disposed in a lattice so as to be arranged in a first arrangement direction and a second arrangement direction, and the disappearance lines are inclined relative to the first arrangement direction or the second arrangement direction.
    Type: Grant
    Filed: May 8, 2015
    Date of Patent: November 6, 2018
    Assignee: DEXERIALS CORPORATION
    Inventors: Seiichiro Shinohara, Yasushi Akutsu
  • Patent number: 10104783
    Abstract: A method for producing a ceramic circuit board comprising the steps of bonding a metal sheet to a ceramic substrate via a brazing material containing Ag to form a bonded body; etching the bonded metal sheet to form a circuit pattern; and removing an unnecessary brazing material from the substrate provided with the circuit pattern, by etching with an acidic solution comprising carboxylic acid and/or carboxylate and hydrogen peroxide.
    Type: Grant
    Filed: March 12, 2014
    Date of Patent: October 16, 2018
    Assignee: HITACHI METALS, LTD.
    Inventor: Nobuhiko Chiwata
  • Patent number: 10080298
    Abstract: Provided is a circuit board interconnection structure including: a first circuit board including a first substrate and a first electrode formed on a surface of the first substrate; a second circuit board including a second substrate and a second electrode formed on a surface of the second substrate; one or more joining portions formed of a metal-containing conductive material for joining the first and second electrodes, interposed between the first and second electrodes; and a reinforcing resin portion for reinforcing the one or more joining portions. The first electrode is a transparent electrode including a metal oxide film. A first abutting portion of the joining portion abutting the first electrode, is formed by adhesional wetting of the first electrode with the conductive material.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: September 18, 2018
    Assignee: PANASONIC CORPORATION
    Inventors: Hideki Eifuku, Koji Motomura
  • Patent number: 10035699
    Abstract: A method of fabricating a MEMS device includes depositing an expandable material into a first recess of a cap wafer. The cap wafer includes a plurality of walls that surround and define the first recess and a second recess. The cap wafer is bonded to a MEMS wafer including a first MEMS device and a second MEMS device. The first MEMS device is encapsulated in the first recess, and the second MEMS device is encapsulated in the second recess. The expandable material is then heated to at least an activation temperature to cause the expandable material to expand after the first recess has been sealed. The expansion of the expandable material causes a reduction in volume of the first recess.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: July 31, 2018
    Assignee: Robert Bosch GmbH
    Inventors: Ashwin K. Samarao, Gary O'Brien, Ando Feyh
  • Patent number: 10034391
    Abstract: The embodiments herein relate to a method for selective partitioning of a via in a printed circuit board as to produce an electrically isolating portion between two electrically conducting portions in said via. The method involves the step of prior to drilling the hole for the via, laminating plating resist layers to the printed circuit board at a distance from each other corresponding to a desired length of the electrically isolated portion of the via. After drilling, copper is added to selected portions of the interior of the via in two different processing steps followed by a step of removing undesired copper as to produce the electrically isolating portion.
    Type: Grant
    Filed: May 20, 2014
    Date of Patent: July 24, 2018
    Assignee: Telefonaktiebolaget LM Ericsson (publ)
    Inventors: Stig Kallman, Tomas Bergsten
  • Patent number: 10011745
    Abstract: A thermosetting adhesive composition and thermosetting adhesive sheet capable of obtaining stable conductivity even in high-temperature environments or high-temperature/high-humidity environments are provided. The thermosetting adhesive sheet comprises an acrylic copolymer obtained by copolymerizing 55 to 80 wt % of alkyl (meth)acrylate, 15 to 30 wt % of acrylonitrile, and 5 to 15 wt % of glycidyl methacrylate; an epoxy resin; an epoxy resin curing agent; and a dendritic conductive filler having a tap density of 1.0 to 1.8 g/cm3. Thereby, thermal expansion after curing is suppressed, and electrical contacts of the conductive filler are increased, allowing stable conductivity to be obtained even in high-temperature environments or high-temperature/high-humidity environments.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: July 3, 2018
    Assignee: DEXERIALS CORPORATION
    Inventor: Toshiki Natori
  • Patent number: 9956742
    Abstract: A composite, a high-frequency circuit substrate using the same and method thereof are discussed. The composite includes the following solid components: a DOPO (9,10-dihydro-9-oxa-10-phosphaphenanthrene 10-oxide) derivative compound of 10-70 wt %, a curing agent of 10-50 wt %, one or more epoxy of 10-90 wt % and an inorganic filling material of 10-40 wt %. The non-halogen low dielectric epoxy composite uses a high-purity DOPO (9,10-dihydro-9-oxa-10-phosphaphenanthrene 10-oxide) derivative as tiny particles dispersing in the composite. The crosslinking yield of the composite is not reduced, while the heat resistance and flame retardancy are increased. The prepreg and copper foil covered laminate for use in printed circuit board, made from the epoxy composite, has great dielectric property and high glass transition temperature (GTT), satisfying the need of high frequency in electronic signal transmission and high speed in data processing of the industry of copper covered printed circuit board.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 1, 2018
    Assignee: Jiangsu Yoke Technology Co., Ltd
    Inventors: Tung-Ying Hsieh, Qi Shen, Jung-Che Lu
  • Patent number: 9953947
    Abstract: An anisotropic conductive film whereby electrically conductive particles can be sufficiently captured at each connection terminal while suppressing the occurrence of shorts and conduction reliability can be improved even in cases where connecting finely pitched connection terminals. The anisotropic conductive film has a structure in which electrically conductive particle units in which electrically conductive particles are arranged in a row, or electrically conductive particle units in which electrically conductive particles are arranged in a row and independent electrically conductive particles are disposed in a lattice form in an electrically insulating adhesive layer. The shortest distance La between electrically conductive particles selected from adjacent electrically conductive particle units and the independent electrically conductive particles is not less than 0.5 times the particle diameter of the electrically conductive particles.
    Type: Grant
    Filed: October 28, 2015
    Date of Patent: April 24, 2018
    Assignee: DEXERIALS CORPORATION
    Inventor: Reiji Tsukao
  • Patent number: 9953945
    Abstract: The present invention relates to an adhesive resin composition for bonding semiconductors, including: a (meth)acrylate-based resin including more than 17% by weight of (meth)acrylate-based repeating units containing epoxy-based functional groups; an epoxy resin having a softening point of more than 70° C.; and a phenol resin having a softening point of more than 105° C., wherein the weight ratio of the (meth)acrylate-based resin is 0.48 to 0.65 relative to the total weight of the (meth)acrylate-based resin, the epoxy resin, and the phenol resin, an adhesive film for semiconductors obtained from the resin composition, a dicing die-bonding film including an adhesive layer that includes the adhesive film for semiconductors, a semiconductor wafer including the dicing die-bonding film, and a dicing method for the semiconductor wafer using the dicing die-bonding film.
    Type: Grant
    Filed: November 17, 2015
    Date of Patent: April 24, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Hee Jung Kim, Jung Hak Kim, Se Ra Kim, Kwang Joo Lee
  • Patent number: 9913372
    Abstract: The wiring board of the present disclosure includes an insulating layer, and a wiring conductor existing so as to be adjacent to both main surfaces of the insulating layer; the insulating layer includes at least two particle-containing resin layers containing insulating particles in an insulating resin, and a particle-free resin layer formed of an insulating resin; and the particle-free resin layer is interposed between the particle-containing resin layers.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: March 6, 2018
    Assignee: KYOCERA Corporation
    Inventors: Masaaki Harazono, Takayuki Umemoto
  • Patent number: 9876370
    Abstract: In a charging station for charging a battery installed on an autonomously navigating utility vehicle equipped with a prime mover powered by the battery to travel about a working area delineated by a boundary wire, there are provided with a pair of charging terminals installed on the station to be capable of connecting with a pair of charging terminals installed on the vehicle, a first wire installed on the station at a location inside of the working area and being formed as a circular shape having a center, and a second wire installed on the station to be formed as a shape that is symmetrical with respect to a center line obtained by connecting a midpoint of the terminals and the center of the first wire.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: January 23, 2018
    Assignee: Honda Motor Co., Ltd.
    Inventors: Makoto Yamamura, Toshiaki Kawakami, Jin Nishimura, Yuki Matsui
  • Patent number: 9875988
    Abstract: A semiconductor device has a first semiconductor die disposed over a substrate. A plurality of composite interconnect structures are formed over the semiconductor die. The composite interconnect structures have a non-fusible conductive pillar and a fusible layer formed over the non-fusible conductive pillar. The fusible layer is reflowed to connect the first semiconductor die to a conductive layer of the substrate. The non-fusible conductive pillar does not melt during reflow eliminating a need to form a solder resist over the substrate. An encapsulant is deposited around the first semiconductor die and composite interconnect structures. The encapsulant flows between the active surface of the first semiconductor die and the substrate. A second semiconductor die is disposed over the substrate adjacent to the first semiconductor die. A heat spreader is disposed over the first semiconductor die. A portion of the encapsulant is removed to expose the heat spreader.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: January 23, 2018
    Assignee: Semtech Corporation
    Inventors: Satyamoorthi Chinnusamy, Weng Hing Tan, Andrew Pan, Kok Khoon Ho
  • Patent number: 9859201
    Abstract: A wiring substrate includes a first wiring structure and a second wiring structure stacked thereon. The first wiring structure includes a first insulation layer and a via wiring extending through the first insulation layer. The second wiring structure includes a first wiring layer formed on the first insulation layer and the via wiring, and a first plane layer stacked on the first insulation layer and at least partially grid-shaped in a plan view to define second through holes. A second insulation layer is stacked on the first insulation layer to fill the second through holes and cover the first plane layer and the first wiring layer. The second wiring structure has a higher wiring density than the first wiring structure. The second through holes each include a lower open end and an upper open end having a smaller open width than the lower open end.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: January 2, 2018
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Noriyoshi Shimizu, Kiyoshi Oi, Yuichiro Shimizu
  • Patent number: 9837369
    Abstract: In a semiconductor device (SP1) according to an embodiment, a solder resist film (first insulating layer, SR1) which is in contact with the base material layer, and a resin body (second insulating layer, 4) which is in contact with the solder resist film and the semiconductor chip, are laminated in between the base material layer (2CR) of a wiring substrate 2 and a semiconductor chip (3). In addition, a linear expansion coefficient of the solder resist film is equal to or larger than a linear expansion coefficient of the base material layer, and the linear expansion coefficient of the solder resist film is equal to or smaller than a linear expansion coefficient of the resin body. Also, the linear expansion coefficient of the base material layer is smaller than the linear expansion coefficient of the resin body. According to the above-described configuration, damage of the semiconductor device caused by a temperature cyclic load can be suppressed, and thereby reliability can be improved.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: December 5, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshikazu Shimote, Shinji Baba, Toshihiro Iwasaki, Kazuyuki Nakagawa
  • Patent number: 9836429
    Abstract: The present invention aims to improve the signal transmission characteristics by shortening the length of the detour path of the return current. The present invention comprises a return current transmission path relative to a signal transmission path for transmitting signals. The signal transmission path includes a signal pad formed on a circuit board surface layer, and signal through-holes formed on the circuit board surface layer and a circuit board inner layer and connected to the signal pad. The return current transmission path includes a ground pad formed on the circuit board surface layer, and a plurality of ground through-holes formed on the circuit board surface layer and the circuit board inner layer and connected to the ground pad and a ground layer of the circuit board inner layer. Each of the ground through-holes is arranged by being separated on either side of the ground pad.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: December 5, 2017
    Assignee: HITACHI, LTD.
    Inventors: Nobuhiko Wakayama, Akio Ikeya
  • Patent number: 9820381
    Abstract: In a semi-finished product for the production of a printed circuit board with at least one recessed electronic component having at least one conductive layer structured to provide a connector pad for an electronic component, fan-out lines connected to the connector pad and further to provide at least one laser-stop device encompassing the connector pad, wherein the laser-stop device has at least one passage for passing-through the fan-out lines, the semi-finished product further comprises at least one cap layer applied to the conductive layer, the at least one cap layer having an opening in registration with each passage.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: November 14, 2017
    Assignee: AT&S Austria Technologie Systemtechnik Aktiengesellschaft
    Inventors: Vic Wang, Ethan Zhou, Laura Bai, Mikael Tuominen, Al Chen
  • Patent number: 9806045
    Abstract: A semiconductor device includes a carrier, an under bump metallurgy (UBM) pad on the carrier, and a post on a surface of the UBM pad. In some embodiments, a height of the post to a longest length of the UBM pad is between about 0.25 and about 0.7. A method of manufacturing a semiconductor device includes providing a carrier, disposing a UBM pad on the carrier and forming a post on the UBM pad.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Lin Lu, Kai-Chiang Wu, Ming-Kai Liu, Yen-Ping Wang, Shih-Wei Liang, Ching-Feng Yang, Chia-Chun Miao, Hao-Yi Tsai
  • Patent number: 9786449
    Abstract: Systems and methods for providing input component assemblies for dome switches are provided. In some embodiments, an input component assembly may include a contact area coupled to a circuit board for a switch, a conductive covering for enclosing the circuit board, and a dome positioned over the conductive covering, where the dome is operative to close at least one circuit of the switch when the dome is depressed towards the conductive covering.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: October 10, 2017
    Assignee: APPLE INC.
    Inventors: Richard Hung Minh Dinh, Lee E. Hooton
  • Patent number: 9738774
    Abstract: There is provided herein a curing agent compound for curing thermosetting resins, e.g., epoxy resins, a composition comprising a thermoplastic and/or thermosetting resin, e.g., an epoxy resin and the curing agent, an article comprising the curing agent, and a method of making the curing agent.
    Type: Grant
    Filed: February 10, 2016
    Date of Patent: August 22, 2017
    Assignee: ICL-IP America Inc.
    Inventors: Andrew M. Piotrowski, Mayank P. Singh, Kali A. Suryadevara, Mariya Kozytska, Yossi Zilberman
  • Patent number: 9728306
    Abstract: A micro-resistance structure with high bending strength is disclosed. The micro-resistance structure with high bending strength comprises a multi-layer metallic substrate; a patterned electrode layer disposed on a lower surface of the multi-layer metallic substrate; an encapsulant layer covering a portion of the multi-layer metallic substrate, wherein the encapsulant layer is substantially made of a flexible resin ink; and two external electrodes, which are electrically insulated from each other, covering the exposed portion of the multi-layer metallic substrate. The abovementioned structure is characterized in high bendability and applicable to wearable devices. A manufacturing method and a semi-finished structure of the micro-resistance structure with high bending strength are also disclosed herein.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: August 8, 2017
    Assignee: VIKING TECH CORPORATION
    Inventors: Chi-Yu Lu, Chien-Ming Shao, Chien-Chung Yu, Guan-Min Zeng
  • Patent number: 9710587
    Abstract: The electronic-substrate electrical design apparatus has: a user interface for setting a first position coordinate and a first direction coordinate with respect to a predetermined layer constituting a multilayer electronic substrate, the first position coordinate indicating a viewpoint position when viewing the layer, the first direction coordinate indicating a visual line direction; a controller for controlling the generation of a three dimensional display image of the electronic substrate obtained when viewing the layer on the basis of the first position coordinate and the first direction coordinate set by the user interface; a display for displaying the three-dimensional display image generated by the control of the controller; and an editor for performing an electrical design of the electronic substrate on the three-dimensional display image displayed by the display.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: July 18, 2017
    Assignee: Zuken Inc.
    Inventors: Kazuhiko Sekido, Shinji Takahashi, Kouki Minami
  • Patent number: 9691636
    Abstract: The mechanisms of using an interposer frame to form a PoP package are provided in the disclosure. The interposer frame is formed by using a substrate with one or more additives to adjust the properties of the substrate. The interposer frame has openings lined with conductive layer to form through substrate vias (TSVs) with solder balls on adjacent packages. The interposer frame enables the reduction of pitch of TSVs, mismatch of coefficients of thermal expansion (CTEs), shorting, and delamination of solder joints, and improve mechanical strength of the package.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jiun Yi Wu
  • Patent number: 9689897
    Abstract: A test socket for IC devices includes a multi-layered socket housing with at least one center layer and first and second surface layers. The first and second surface layers have a thickness and dielectric constant less than that of the center layers. A plurality of contact members are located in center openings in the center layer with distal ends extending into openings in the first and second layers. The distal ends of the contact members having at least one dimension greater than the openings in the first and second surface layers to retain the contact members in the socket housing. The contact members include center portions with major diameters less than the diameters of the center openings, such that an air gap is maintained between the contact members and the center layer.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: June 27, 2017
    Assignee: HSIO Technologies, LLC
    Inventor: James Rathburn
  • Patent number: 9650717
    Abstract: A pre-treatment method of plating and a plating system can perform a uniform plating process in which sufficient adhesivity on a surface of a substrate is obtained. The pre-treatment method of plating includes a coupling layer forming process of forming a titanium-based coupling layer 21b on the surface of the substrate with a titanium coupling agent; and a coupling layer modification process of modifying a surface of the titanium-based coupling layer 21b with a modifying liquid after the coupling layer forming process.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: May 16, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazutoshi Iwai, Nobutaka Mizutani, Mitsuaki Iwashita
  • Patent number: 9605115
    Abstract: A process for preparing a reinforced and reactive thermoplastic composition having a continuous phase based on a thermoplastic polymer and dispersed therein is a discontinuous phase based on a reactive reinforcing agent that may be immiscible with the thermoplastic polymer is provided. A composition obtained by this process is also provided. The reinforcing agent is selected from the group consisting of epoxy resins, polyorganosiloxanes having SiH functional group(s), diisocyanates or polyisocyanates and mixtures thereof, comprises a grafting, a branching and/or a crosslinking, that are carried out in situ, by reactive compounding of these phases with a shear rate greater than 102 s?1, of the reinforcing agent onto the chain of the thermoplastic polymer, so that the discontinuous phase is dispersed homogeneously in the continuous phase in the form of nodules having a number-average size of less than 5 ?m.
    Type: Grant
    Filed: April 4, 2014
    Date of Patent: March 28, 2017
    Assignee: Hutchinson
    Inventors: Nicolas Garois, Philippe Sonntag, Gregory Martin, Matthieu Vatan, Jacques Drouvroy
  • Patent number: 9585238
    Abstract: Provided is a printed circuit board which is used in a bent state, including: a substrate; a first conductive layer which is formed on the substrate; a first insulation layer which is formed on the substrate so as to cover the first conductive layer; and a second conductive layer which is formed on the first insulation layer, wherein on the assumption that the Youngs modulus of the first insulation layer is indicated by Ei1 and the fracture elongation of the second conductive layer is indicated by Bc2, the following equations (I) and (II) are satisfied.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: February 28, 2017
    Assignee: FUJIKURA LTD.
    Inventor: Yasuyuki Tachikawa
  • Patent number: 9585251
    Abstract: A method of manufacturing conductive wiring includes: printing on an insulated substrate 1 with ink 2 to form a predetermined pattern (S1); placing (spraying) conductive powder 3 on the ink 2 (in the predetermined pattern) before the printed ink 2 dries (S2); pressing the placed conductive powder 3 against the insulated substrate 1 to compress the conductive powder 3 (S3); and heating the compressed conductive powder 3 to sinter the conductive powder 3 (S4), and by such a series of processes (S1 to S4), conductive wiring 20 is manufactured.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: February 28, 2017
    Assignee: SHUHOU CO., LTD.
    Inventor: Kouji Muraoka
  • Patent number: 9547401
    Abstract: A touch panel includes a driving layer and a sensing layer. The driving layer has a first top surface and a driving layer edge. The first top surface has at least one first connecting region. The driving layer edge surrounds the first connecting region and there is a first distance between the first connecting region and the driving layer edge. The sensing layer is disposed on the first top surface of the driving layer. The second top surface of sensing layer away from the driving layer has at least one second connecting region. The sensing layer edge of the sensing layer surrounds the second connecting region, and there is a second distance between the sensing layer edge and the at least one second connecting region.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: January 17, 2017
    Inventors: Chen-Hsin Chang, Bin Zhong, Che-I Wu, Fuding Wang, Lixian Chen, Yongbin Ke
  • Patent number: 9532469
    Abstract: A multilayer substrate includes a first substrate a second substrate that is stacked on and electrically connected to the first substrate, the second substrate having a different characteristic from a characteristic of the first substrate, a third substrate that is provided on a side of the first substrate, the second substrate being provided on the side of the first substrate, and the third substrate is electrically connected to the second substrate, and a connection member that electrically connects the first substrate and the third substrate to each other while the second substrate is bypassed.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: December 27, 2016
    Assignee: FUJITSU LIMITED
    Inventors: Shunji Baba, Takashi Kanda
  • Patent number: 9523709
    Abstract: A method of manufacturing a multilayer wiring board includes a stacking process in which insulating layers, each of which includes a ceramic layer and a shrinkage suppression layer being stacked on top of the ceramic layer, are stacked on top of one another, a press-bonding process in which the insulating layers are press-bonded, so that a multilayer body is formed, and a firing process in which the multilayer body is fired. In the stacking process, in each of the insulating layers, a wiring electrode is formed on a surface of the shrinkage suppression layer on the opposite side to the surface of the layer facing the ceramic layer, and the thickness of a peripheral area of the shrinkage suppression layer located around the area of the shrinkage suppression layer that is in contact with the electrode is larger than those of portions of the layer except for the peripheral area.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: December 20, 2016
    Assignee: Murata Manufcaturing Co., Ltd.
    Inventor: Yoshihito Otsubo
  • Patent number: 9503671
    Abstract: Provided is a display device. The display device includes: a display panel which displays an image; and a housing which supports the display panel, wherein the housing includes: a bottom plate which includes edge regions; and a plurality of sidewalls which are located on the edge regions of the bottom plate and face the display panel, wherein the plurality of sidewalls include a first region and a second region adjacent to the first region and overlap an edge portion of the display panel, and an average height of at least one of the sidewalls on the first region is greater than an average height of at least one of the sidewalls on the second region.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: November 22, 2016
    Assignee: Samsung Display Co., Ltd.
    Inventors: Eui Yun Jang, Na Young Shin, Yun Jang
  • Patent number: 9456507
    Abstract: A method for fabrication of a circuit board using the disclosed embodiments relies on a CAD model of a multilayer circuit board with conductive elements defined by layer. A first granular conductive material layer is introduced into a mold. A fusion process element traverses across the mold to fuse selected portions of the first granular conductive material layer forming first layer conductive elements. An additional granular conductive material layer is introduced into the mold over the fused selected portions of the first layer and unfused portions of the first layer. The fusion process element is then traversed across the mold to fuse selected portions of the additional granular conductive material layer forming an additional layer of conductive elements. Unfused granular conductive material is then purged from the fused first conductive elements and additional conductive layer elements.
    Type: Grant
    Filed: October 7, 2013
    Date of Patent: September 27, 2016
    Assignee: The Boeing Company
    Inventor: Donald F. Wilkins
  • Patent number: 9389338
    Abstract: An optical member includes an anisotropic conductive film that has a multilayer structure having a bonding layer containing an epoxy resin as a curing part and a bonding layer containing a (meth)acrylate resin as a curing part.
    Type: Grant
    Filed: October 14, 2011
    Date of Patent: July 12, 2016
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Dong Seon Uh, Hyun Hee Namkung, Kwang Jin Jung, Jin Seong Park, Jae Sun Han
  • Patent number: 9392701
    Abstract: An electronic component package includes a substrate having at least one electronic circuit; a sealing resin for sealing the electronic circuit, at least one filler on which at least one crack is formed being filled in the sealing; and a metal film formed on a top surface of the sealing resin, a root of the metal film being embedded in the crack on the filler. The electronic component package can shield the environmental electromagnetic noise and satisfy with lightweight requirement for the integrated circuit modules.
    Type: Grant
    Filed: May 29, 2014
    Date of Patent: July 12, 2016
    Assignee: SAE MAGNETICS (H.K.) LTD.
    Inventors: Akio Nakao, Hidenobu Takemoto
  • Patent number: 9350115
    Abstract: An electrical connector is provided for electrically connecting a chip module with a position post to a printed circuit board. The connector includes an insulative housing defining a matching surface and a mounting surface opposite each other, and a position hole disposed in the insulative housing; a plurality of terminals loaded in the insulative housing. The position hole has three ribs in an inner surface thereof, the ribs extend from the matching surface toward the mounting surface along a straight line.
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: May 24, 2016
    Assignee: FOXCONN INTERCONNECT TECHNOLOGY LIMITED
    Inventor: Fang-Jwu Liao
  • Patent number: 9332658
    Abstract: A wiring board includes first and second insulating layers, first and second through holes, a via, a plane layer, and signal wirings. The first insulating layer covers a first wiring layer. The first through hole opens on a surface of the first insulating layer and exposes a surface of the first wiring layer. The via fills the first through hole. The plane layer is connected to the via and is stacked on the first insulating layer. The second through hole opens on a surface of the plane layer and exposes the surface of the first insulating layer. The second insulating layer at least partially fills the second through hole and covers the plane layer. The signal wirings are stacked on the second insulating layer. The first through hole overlaps the signal wirings in a plan view. The second through hole does not overlap the signal wirings in a plan view.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 3, 2016
    Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Yuji Kunimoto, Noriyoshi Shimizu
  • Patent number: 9263417
    Abstract: The embedded package includes a semiconductor chip having contact portions disposed on a top surface thereof, a first dielectric layer substantially surrounding sidewalls of the semiconductor chip and including first fillers dispersed therein, a second dielectric layer substantially covering the top surface of the semiconductor chip and including second fillers dispersed therein, and first external interconnection portions disposed on the second dielectric layer and electrically connected to the contact portions, wherein an average size of the first fillers is different from that of the second fillers.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: February 16, 2016
    Assignee: SK Hynix Inc.
    Inventor: Seung Jee Kim
  • Patent number: 9230903
    Abstract: Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.
    Type: Grant
    Filed: July 20, 2015
    Date of Patent: January 5, 2016
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Arkadii V. Samoilov, Peter R. Harper, Viren Khandekar, Pirooz Parvarandeh
  • Patent number: 9215805
    Abstract: A wiring board including a substrate having opening penetrating from first to second surfaces, an electronic component in the opening having first and second electrodes, a first insulation layer over the first surface, a second insulation layer over the second surface, a first via conductor in the first layer having bottom connected to the first electrode, a second via conductor in the first layer having bottom connected to the second electrode, a third via conductor in the second layer having bottom connected to the first electrode, and a fourth via conductor in the second layer having bottom connected to the second electrode. The first conductor is longer than the third conductor and has the bottom having greater width than the bottom of the third conductor, and the second conductor is longer than the fourth conductor and has the bottom having greater width than the bottom of the fourth conductor.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: December 15, 2015
    Assignee: IBIDEN CO., LTD.
    Inventors: Masahiro Zanma, Toshiki Furutani, Yukinobu Mikado
  • Patent number: 9190381
    Abstract: An insulating adhesive film is formed by laminating a first insulating adhesive layer which contains a filler in an insulating adhesive composition and a second insulating adhesive layer which contains no filler in an insulating adhesive composition. H/2<Tf<H?Tf+Tn is satisfied, wherein H is the height of the bump of the IC chip, Tf is the thickness of the first insulating adhesive layer, and the Tn is the thickness of the second insulating adhesive layer. The side of the substrate on which an electrode is formed and the side of an IC chip on which a bump is formed are connected via the insulating adhesion film arranged such that the first insulating adhesive layer and the electrode-forming side of the electronic component are opposed to thereby connect the electrode of the substrate and the bump of the IC chip.
    Type: Grant
    Filed: December 7, 2012
    Date of Patent: November 17, 2015
    Assignee: DEXERIALS CORPORATION
    Inventor: Ryoji Kojima