Adhesive/bonding Patents (Class 174/259)
  • Patent number: 8912450
    Abstract: A method for attaching a metal surface to a carrier is provided, the method including: forming a first polymer layer over the metal surface; forming a second polymer layer over a surface of the carrier; and bringing the first polymer layer into physical contact with the second polymer layer such that at least one of an interpenetrating polymer structure and an inter-diffusing polymer structure is formed between the first polymer layer and the second polymer layer.
    Type: Grant
    Filed: June 27, 2011
    Date of Patent: December 16, 2014
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Manfred Mengel, Khalil Hosseini, Franz-Peter Kalz
  • Patent number: 8895866
    Abstract: A printed circuit board structure includes a plurality of circuit layer plates stacked together in which each of the stacked circuit layer plates includes an epoxy resin plate body and a fabric structure completely encapsulated in the epoxy resin plate body, and each circuit layer plate stacked between two circuit layer plates is further provided with filler particles distributed in its epoxy resin plate body, and the two opposite and outermost circuit layer plates thereof have metal soldering pads on the outer surfaces of the epoxy resin plate body thereof, and the two opposite and outermost circuit layer plates do not have the filler particles in its epoxy resin plate body thereof.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: November 25, 2014
    Assignees: Quanta Computer Inc., Tech-Front (Shanghai) Computer Co., Ltd.
    Inventors: Steven Wang, Jin-Chang Wu, Mide Yang
  • Patent number: 8895869
    Abstract: Electrode protective films 13a and 13b are formed on the surface of the metal layer using imidazole preflux, as terminal electrodes 35a and 35b of an electronic component. The terminal electrodes of an electronic component on which the protective films are formed are fixed by electroconductive adhesives 33a and 33b supplied to mounting lands 40a and 40b. Thereby an electronic component mounting structure without change in resistance caused by electroconductive adhesives is provided.
    Type: Grant
    Filed: November 9, 2010
    Date of Patent: November 25, 2014
    Assignee: Koa Corporation
    Inventor: Toshifumi Mizokami
  • Patent number: 8889995
    Abstract: To reduce the RF losses associated with high RF loss plating, such as, for example, Ni/Pd/Au plating, the solder mask is reconfigured to prevent the edges and sidewalls of the wire-bond areas from being plated in some embodiments. Leaving the edges and sidewalls of the wire-bond areas free from high RF loss plating, such as Ni/Pd/Au plating, provides a path for the RF current to flow around the high resistivity material, which reduces the RF signal loss associated with the high resistivity plating material.
    Type: Grant
    Filed: March 3, 2011
    Date of Patent: November 18, 2014
    Assignee: Skyworks Solutions, Inc.
    Inventors: Weimin Sun, Peter J. Zampardi, Hongxiao Shao
  • Patent number: 8878075
    Abstract: Providing a connecting structure for connecting first electrodes formed on the upper surface of a first substrate to second electrodes formed on the upper surface of a second substrate glued on the upper surface of the first substrate by an electrically conductive member, wherein the second substrate is smaller in its outer size than the first substrate, the first electrodes are arranged on the first substrate around the periphery of the second substrate, a gap is formed between the first and second substrates at the peripheral edge of the second substrate, an insulating resin is arranged near the first electrodes so as to cover portions of the side surfaces of the second substrate and to fill the gap between the first and second substrates, and the electrically conductive member is arranged over regions leading from the first electrodes through the insulating resin to the second electrodes.
    Type: Grant
    Filed: May 15, 2012
    Date of Patent: November 4, 2014
    Assignee: NLT Technologies, Ltd.
    Inventor: Akira Fujita
  • Patent number: 8877878
    Abstract: A sulfonium borate complex that is capable of reducing the amount of fluorine ions generated during thermal cationic polymerization, and is capable of providing a thermal cationic polymerizable adhesive with low-temperature fast curing properties is represented by a structure represented by the formula (1). In the formula (1), R1 is an aralkyl group, R2 is a lower alkyl group, and R3 is a lower alkoxycarbonyl group. X is a halogen atom, and n is an integer of from 1 to 3.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: November 4, 2014
    Assignee: Dexerials Corporation
    Inventors: Yoshihisa Shinya, Jun Yamamoto, Ryota Aizaki, Naoki Hayashi, Misao Konishi, Yasuhiro Fujita
  • Publication number: 20140318840
    Abstract: An embodiment of a stacked structure includes: a first substrate that includes a first electrode; a second substrate that includes a second electrode; and an adhesive resin material that is provided between the first substrate and the second substrate and includes a plurality of conductive vias, the plurality of conductive vias electrically connecting the first electrode and the second electrode.
    Type: Application
    Filed: March 21, 2014
    Publication date: October 30, 2014
    Applicant: FUJITSU LIMITED
    Inventor: TAKASHI KANDA
  • Patent number: 8869387
    Abstract: Microelectronic packages with leadframes, including leadframes configured for stacked die packages, and associated systems and methods are disclosed. A system in accordance with one embodiment includes a support member having first package bond sites electrically coupled to leadframe bond sites. A microelectronic die can be carried by the support member and electrically coupled to the first packaged bond sites. A leadframe can be attached to the leadframe bond sites so as to extend adjacent to the microelectronic die, with the die positioned between the leadframe and the support member. The leadframe can include second package bond sites facing away from the first package bond sites. An encapsulant can at least partially surround the leadframe and the microelectronic die, with the first and second package bond sites accessible from outside the encapsulant.
    Type: Grant
    Filed: March 17, 2010
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Chin Hui Chong, Choon Kuan Lee, David J. Corisis
  • Patent number: 8861214
    Abstract: Substrates for integrated passive devices are described herein. Embodiments of the present invention provide substrates including a glass layer and at least one passive device disposed thereon. According to various embodiments of the present invention, the glass layer may have a thickness adapted to minimize conductive and/or other interactions between the substrate and the at least one passive device. Other embodiments may be described and claimed.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: October 14, 2014
    Assignee: Marvell International Ltd.
    Inventors: Albert Wu, Chuan-Cheng Cheng
  • Publication number: 20140300832
    Abstract: An electronic device may have structures that are coupled together using conductive adhesive such as anisotropic conductive film and other adhesives. The structures that are coupled together may include a touch sensor structure formed from electrodes on the inner surface of a display cover layer, a display module having display layers such as a thin-film transistor layer, and circuitry mounted on substrates such as printed circuits. Conductive signal path structures may be used in routing signals within the electronic device. The conductive signal path structures may be formed from pins that are embedded within injection molded plastic, from metal traces such as laser-deposited metal traces that are formed on the surface of a plastic member or other dielectric, from metal structures that run within channels in a plastic, printed circuit traces, and other signal path structures.
    Type: Application
    Filed: April 8, 2013
    Publication date: October 9, 2014
    Applicant: Apple Inc.
    Inventor: Apple Inc.
  • Patent number: 8851621
    Abstract: A liquid ejecting head has a flow channel substrate, an actuator formed on the flow channel substrate and having at least one mount, and a flexible wiring substrate electrically connected to the mount to supply a drive signal to the actuator. The mount of the actuator and the wiring substrate are bonded together using an epoxy adhesive agent containing p-aminophenol epoxy resin, bisphenol A epoxy resin, and bisphenol F epoxy resin.
    Type: Grant
    Filed: March 26, 2013
    Date of Patent: October 7, 2014
    Assignee: Seiko Epson Corporation
    Inventors: Masahiko Sato, Munehide Kanaya, Toshinobu Yamazaki
  • Patent number: 8854827
    Abstract: An electronic control unit is configured in such a way that the groove-shaped concave portion of the second case member includes a first concave portion, in which a groove width at a bottom surface side is narrow, and a second concave portion, in which a groove width at an aperture surface side is wide, and the first concave portion and the second concave portion are linked by an inclined step portion in such a way that a groove width at the step portion is increased in a direction from the bottom surface side to the aperture surface side, and moreover, a tip of the rail-shaped convex portion of the first case member is fitted into the first concave portion at the bottom surface side of the second case member.
    Type: Grant
    Filed: August 28, 2012
    Date of Patent: October 7, 2014
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takaaki Tanaka, Yasuhiro Takahashi, Toru Kubo, Seiji Kato, Hideki Umemoto
  • Publication number: 20140287299
    Abstract: A heat-debonding adhesive member is provided. The heat-debonding adhesive member attaches electronic device components such as a battery and a housing together. The heat-debonding adhesive includes a heat-generating layer that generates heat for debonding structures that are attached together using the adhesive member. The heat-generating layer includes a conductive layer that generates heat when a current flows through the conductive layer. The heat-debonding adhesive includes additional adhesive layers such as a voided polymer film having air-filled voids and one or more pressure-sensitive adhesive layers. A debonding tool provides current to conductive contacts on the conductive layer for generating heat in the heat-generating layer when it is desired to debond the structures that are attached together using the adhesive member.
    Type: Application
    Filed: March 25, 2013
    Publication date: September 25, 2014
    Applicant: Apple Inc.
    Inventor: James R. Krogdahl
  • Patent number: 8842440
    Abstract: A method for manufacturing a printed circuit board includes forming an opening portion in a substrate, positioning chip capacitors in the opening portion of the substrate such that the chip capacitors are accommodated in the opening portion of the substrate, forming a buildup structure including an interlayer resin insulating layer and a conductive layer over a surface of the substrate and the chip capacitors accommodated in the opening portion of the substrate, and forming on a surface of the buildup structure bump structures positioned to mount an IC chip such that the chip capacitors in the opening portion of the substrate are positioned directly below the IC chip.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: September 23, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8835770
    Abstract: An electronic component that includes an electronic component body, sealing members sealing the electronic component body, and adhesive layers which adhere the electronic component body and the sealing members, respectively. Between the electronic component body and the sealing members, sealed spaces are formed, respectively. The adhesive layers each contain organic fillers and inorganic fillers. The organic fillers are in contact with both the electronic component body and the sealing members. The inorganic fillers each have a minimum particle diameter smaller than the thickness of each of the adhesive layers. When the adhesive layers are viewed in a thickness direction thereof, the inorganic fillers are provided between the organic fillers and the electronic component body and between the organic fillers and each of the sealing members.
    Type: Grant
    Filed: October 1, 2012
    Date of Patent: September 16, 2014
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Junji Oyama, Takamasa Kuboki, Yasuharu Matsui, Muneyuki Daidai
  • Patent number: 8835772
    Abstract: In order to lower the substantial heating temperature of a thermosetting adhesive and to realize favorable connection reliability during connecting an electrical element to a circuit board by anisotropic conductive connection with using solder particles, a product in which solder particles having a melting temperature Ts are dispersed in an insulating acrylic-based thermosetting resin having a minimum melt viscosity temperature Tv is used as an anisotropic conductive adhesive in producing a connection structure by connecting the circuit board and the electrical element to each other by anisotropic conductive connection.
    Type: Grant
    Filed: June 3, 2011
    Date of Patent: September 16, 2014
    Assignee: Dexerials Corporation
    Inventor: Satoshi Igarashi
  • Patent number: 8830691
    Abstract: A printed circuit board including a core substrate including a first resin substrate, a second resin substrate having an opening and a third resin substrate in a multilayer manner while interposing bonding plates, insulating layers and conductive circuit layers alternately laminated on the core substrate, solder bumps formed on an outer surface of the printed circuit board, a first capacitor formed in the opening of the second resin substrate, a conductive pad formed on the first resin substrate and connected to an electrode of the first capacitor, a via hole formed in the first resin substrate and directly connected to the conductive pad and a conductive circuit on the core substrate, and a second capacitor mounted on a surface of the printed circuit board.
    Type: Grant
    Filed: May 21, 2010
    Date of Patent: September 9, 2014
    Assignee: IBIDEN Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi, Seiji Shirai
  • Patent number: 8829360
    Abstract: The connector for PV cells is a strip of electrically conductive material which has a flat cross-section with two broad sides and with two narrow sides which each connect opposite edges of the broad sides. At least one broad side has a corrugated structure running in longitudinal direction of the strip and is pre-tinned in an area the length of which is somewhat less than the length of the edge of a PV cell.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: September 9, 2014
    Assignee: Schlenk Metallfolien GmbH & Co. KG
    Inventors: Thomas Booz, Fabian Distelrath
  • Patent number: 8822836
    Abstract: A bonding sheet includes an insulating sheet with cavities formed within the insulating sheet, and adhesive-filling portions made of an electrically conductive adhesive filled in the cavities. An electronic circuit device includes an IC package mounted on a circuit board, with the bonding sheet disposed between the IC package and the circuit board. The IC package is provided with terminal electrodes in the lower surface, and electrode bumps project from the terminal electrodes. The circuit board has recesses in the upper surface, and electrode pads are formed on the bottom of the recesses. The electrically conductive adhesive that flows out from the adhesive-filling portions filled the recesses and fix the electrode bumps and the electrode pads.
    Type: Grant
    Filed: September 9, 2009
    Date of Patent: September 2, 2014
    Assignee: NEC Corporation
    Inventor: Eiji Hori
  • Patent number: 8822835
    Abstract: A capacitive touch panel sensor in which waviness generated in a film furnished with a transparent electrode pattern can be small. The touch panel sensor according to the present invention includes a first film, a first transparent electrode pattern formed on the first film, a first adhesive layer laminated on the first film so as to cover the first transparent electrode pattern, a second film laminated on the first adhesive layer, a second adhesive layer laminated on the second film, a third film laminated on the second adhesive layer, and a second transparent electrode pattern formed on the third film, wherein Da/Db is 0.5 to 0.9 where a total thickness of the second film and the second adhesive layer is Da, and a distance between the first transparent electrode pattern and the second transparent electrode pattern is Db.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: September 2, 2014
    Assignee: Nitto Denko Corporation
    Inventors: Mizue Nagata, Tomotake Nashiki
  • Patent number: 8816214
    Abstract: A pane with an electrical connection element is described, including a substrate made of glass with a first coefficient of thermal expansion, an electrically conductive structure with a layer thickness of 5 ?m to 40 ?m on a region of the substrate, a connection element with a second coefficient of thermal expansion, and a layer of a solder material that connects the connection element electrically to subregions of the electrically conductive structure.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: August 26, 2014
    Assignee: Saint Gobain Glass France
    Inventors: Stefan Ziegler, Mitja Rateiczak, Bernhard Reul, Andreas Schlarb
  • Patent number: 8816215
    Abstract: The present invention relates to a disk with an electrical connection element, having a substrate with a first coefficient of thermal expansion, an electrically conductive structure on a region of the substrate, and a connection element with a second coefficient of thermal expansion.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: August 26, 2014
    Assignee: Saint-Gobain Glass France
    Inventors: Bernhard Reul, Mitja Rateiczak, Stefan Ziegler, Andreas Schlarb
  • Patent number: 8803004
    Abstract: In one embodiment, an apparatus includes a cover panel. An adhesive layer is coupled to the cover panel. A perimeter of the adhesive layer forms at least a portion of a gasket seal extending substantially perpendicular to an inner surface of the cover panel. An inner surface of the gasket seal defines an edge of a channel. The apparatus also includes a substrate coupled to the adhesive layer. The substrate includes an outer surface having disposed thereon a connection pad region and drive or sense electrodes. The drive or sense electrodes are disposed between the substrate and the cover panel. At least a portion of the channel is disposed between the gasket seal and the connection pad region. The apparatus further includes a flexible printed circuit (FPC) electrically coupled by the connection pad region to the drive or sense electrodes. A first portion of the FPC extends through the channel.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Atmel Corporation
    Inventor: David Brent Guard
  • Patent number: 8802997
    Abstract: Disclosed is a PCB having multiple layers of heavy copper. A prepreg having a nonwoven glass web substrate is used alone or together with another prepreg having a glass fabric substrate so that the space between heavy copper, which is comparable to a thick film, can be filled efficiently without creating voids. The PCB includes a copper clad laminate having first copper patterned on one surface or both surfaces of a core substrate; at least one first prepreg laminated on one surface or both surfaces of the copper clad laminate, nonwoven glass web being used as the substrate of the first prepreg; at least one second prepreg laminated on one surface or both surfaces of the first prepreg, glass fabric being used as a substrate of the second prepreg; and second copper laminated on one surface or both surfaces of the second prepreg.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: August 12, 2014
    Assignee: Doosan Corporation
    Inventors: Jeong Don Kwon, Seung Min Hong, Ju Ho Shin
  • Patent number: 8803001
    Abstract: Devices, methods and systems are disclosed herein to describe the wettability characteristics of the material forming a bonding area, a non-bonding area, and a melted bonding material. The melted bonding material may have a high degree of cohesion and may result in a very high contact angle (e.g., between 90°- 180°) in the non-bonding area thereby preventing or limiting the flow of a melted material into the non-bonding area, which often results when the melted bonding material forms a low contact angle (e.g., between 0°-90°) in the bonding area. In other words, by choosing a material for the non-bonding area to have low wettability characteristics when compared to the melted materials of the bonding area or by treating the material forming the non-bonding area to have much lower wettability characteristics, the melted materials of the bonding area may be prevented from flowing into the non-bonding area.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 12, 2014
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Sang Won Yoon, Satoshi Yasuda, Koji Shiozaki
  • Patent number: 8804358
    Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: August 12, 2014
    Assignee: Hypres Inc.
    Inventor: Vladimir V. Dotsenko
  • Publication number: 20140216801
    Abstract: A method of manufacturing a component-embedded substrate comprises forming an adhesive layer on a metal layer formed on a supporting plate, and mounting an electric or electronic component on the adhesive layer, wherein the component includes a component main body and a protrusion that protrudes beyond the component main body toward the adhesive layer, the adhesive layer includes a first adhesive body and a second adhesive body, the first adhesive body is formed only at a position corresponding to the protrusion, the second adhesive body is formed in an area corresponding to the whole of the surface of the component facing the adhesive layer after the first adhesive body is cured, and the component is mounted with the protrusion aligned with the first adhesive body in the component mounting step.
    Type: Application
    Filed: September 12, 2011
    Publication date: August 7, 2014
    Applicant: MEIKO ELECTRONICS CO., LTD.
    Inventors: Tohru Matsumoto, MItsuaki Toda, Yoshio Imamura
  • Patent number: 8796557
    Abstract: An adhesive film, containing a first adhesive layer in which conductive particles are dispersed, and a second adhesive layer adhered to the first adhesive layer, wherein the lowest viscosity of the first adhesive layer attained at or below the curing temperature is higher than that of the second adhesive layer attained at or below the curing temperature, where the curing temperature is a temperature at which the adhesive layer starts to cure, wherein the first and second adhesive layers are respectively disposed to a substrate side and an electronic part side, and the adhesive film is configured to join the electronic part and the substrate by heating and pressurizing the substrate and the electronic part with the adhesive layer being therebetween, and wherein the first adhesive layer has a thickness which is less than two times of an average particle diameter of the conductive particles.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 5, 2014
    Assignee: Dexerials Corporation
    Inventors: Tomoyuki Ishimatsu, Hiroki Ozeki
  • Patent number: 8787028
    Abstract: The electronic device includes a terminal structure and a printed circuit board including the terminal structure. The terminal structure includes a solder-joint conductor region placed on a wiring conductor, an intermediate layer contacting with the conductor region, and a solder region contacting with the intermediate layer. The intermediate layer includes an intermetallic compound including tin and at least one of copper and nickel as principal components. When the indentation elastic modulus of the conductor region is E1 and the indentation elastic modulus of the intermediate layer is E2, the ratio of E1 to E2 is equal to or more than 0.8 and equal to or less than 1.5.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 22, 2014
    Assignee: TDK Corporation
    Inventors: Yuhei Horikawa, Shin Fujita, Kenichi Yoshida, Hisayuki Abe, Makoto Orikasa, Hideyuki Seike
  • Patent number: 8780573
    Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 15, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi
  • Patent number: 8780572
    Abstract: A printed circuit board that include: an electronic component having a plating electrode pad having a predetermined thickness; an insulating resin layer that exposes a lower surface of the electrode pad, receives the electronic component, and embodies the electronic component so that the center of the base body forming the electronic component is positioned at the center of the insulating resin layer; and circuit layers that include a circuit pattern disposed on the electrode pad, form inter-layer connection, and are disposed on both surfaces of the insulating resin layer, respectively, the plating electrode pad having a thickness that conforms to a thickness from an upper surface of the electronic component to an upper surface of the insulating resin.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: July 15, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Doo Hwan Lee, Tae Sung Jeong
  • Publication number: 20140182904
    Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board including an adhesive promoter interposed between an insulating layer and a circuit layer on a substrate in order to improve adhesion therebetween; and a first metal layer formed between the adhesive promoter and the circuit layer has high adhesion between an insulating layer such as a resin and a circuit while having low roughness by including a polymer adhesive promoter, easily forms a fine circuit and has low signal transmission loss due to low roughness, and has high reliability due to the high adhesion.
    Type: Application
    Filed: June 27, 2013
    Publication date: July 3, 2014
    Inventors: Yong Jin Park, Sung Gap Im, Jae Bum You, Young Gwan Ko
  • Publication number: 20140158413
    Abstract: An adhesive composition includes (A) a phenoxy resin including a plurality of hydroxyl groups at a side chain: 100 parts by mass, (B) a multifunctional isocyanate compound including an isocyanate and at least one functional group selected from the group consisting of a vinyl group, an acrylate group and a methacrylate group within its molecule: 2 to 55 parts by mass, (C) a maleimide compound and/or a reaction product thereof having a plurality of maleimide groups within its molecule: 5 to 30 parts by mass, and (D) one or more kinds of an inorganic filler having an average particle size of 5 ?m or less which is measured by a laser diffraction: 1 to 50 parts by mass, a total amount of the components (B) and (C) is 7 to 60 parts by mass.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 12, 2014
    Applicant: HITACHI METALS, LTD.
    Inventors: Daisuke SHANAI, Takashi Aoyama, Kazuhiko Sasada, Hiroaki Komatsu
  • Patent number: 8749076
    Abstract: The present invention relates to a resin paste composition including an organic compound, and a granular aluminum powder having an average particle diameter of from 2 to 10 ?m and a flake-shaped silver powder having an average particle diameter of from 1 to 5 ?m which are uniformly dispersed in the organic compound, and a semiconductor device manufactured by bonding a semiconductor element onto a supporting member through the resin paste composition and then encapsulating the resulting bonded product. According to the present invention, it is possible to provide a resin paste composition used for bonding an element such as semiconductor chips onto a lead frame which is excellent in not only electrical conductivity and bonding property but also working efficiency without using a large amount of rare and expensive silver, and a semiconductor device having a high productivity and a high reliability.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: June 10, 2014
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Chiaki Okada, Kazuhiko Yamada, Yukari Inoue
  • Patent number: 8726495
    Abstract: A base material (20) is arranged on top of at least one first internal layer base material (10), and a second internal base material (30) is arranged underneath the base material (10). And thereafter a surface layer circuitry conductive foil (40) is arranged underneath the base material (30), and subsequently these materials are colaminated for forming a colaminated body (80). While this colaminating operation, conductive portions being formed in the base materials 10, 30 are aligned to electrically connect one another for forming an internal circuitry. And thereafter, an interlayer conductive portion (51) being electrically connected to the internal circuitry is formed, and a minute circuitry is formed on the top of the base material (20) and the conductive foil (40) accordingly.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: May 20, 2014
    Assignee: Fujikura Ltd.
    Inventors: Osamu Nakao, Reiji Higuchi, Syouji Ito, Masahiro Okamoto
  • Patent number: 8723050
    Abstract: An exemplary multilayer printed circuit board includes a first circuit substrate, a third circuit substrate, a second circuit substrate between the first and third circuit substrates, a first anisotropically conductive adhesive layer between the first and second circuit substrates, and a second anisotropically conductive adhesive layer between the second and third circuit substrates. The first circuit substrate includes a first conductive terminal and a first through hole. The second circuit substrate includes a second conductive terminal and two through holes (i.e. second and third through holes). The third circuit substrate includes a third conductive terminal and a fourth through hole. The first anisotropically conductive adhesive layer fills the first and third through holes to electrically connect the first and second conductive terminals. The second anisotropically conductive adhesive layer fills the second and fourth through holes to electrically connect the second and third conductive terminals.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: May 13, 2014
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventor: Chien-Pang Cheng
  • Patent number: 8716401
    Abstract: A semiconductor chip laminate comprises a plurality of semiconductor chips and an adhesive layer through which the plurality of semiconductor chips are laminated, wherein the adhesive layer is composed of an adhesive composition comprising an acrylic polymer (A); an epoxy resin (B); a thermal curing agent (C); and a certain organophosphonium compound (D) as a thermal curing accelerator, and the content of the organophosphonium compound (D) relative to 100 parts by weight in total of the epoxy resin (B) and the thermal curing agent (C) is 0.001 to 15 parts by weight.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: May 6, 2014
    Assignee: Lintec Corporation
    Inventors: Yasunori Karasawa, Isao Ichikawa
  • Patent number: 8698007
    Abstract: There is provided a printed circuit board including an insulating substrate having a guide hole, a solder resist layer coated on a surface of the insulating substrate, and a connection pad arranged on the surface of the insulating substrate and having an outer periphery covered with the solder resist layer and a central portion exposed in an opening formed in the solder resist layer. The solder resist layer has a positioning hole having a diameter smaller than that of the guide hole and formed by photolithography above the guide hole simultaneously with the opening.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 15, 2014
    Assignee: Kyocera SLC Technologies Corporation
    Inventor: Keizou Sakurai
  • Patent number: 8696942
    Abstract: The adhesive composition of the invention comprises a radical generator, a thermoplastic resin and a urethane(meth)acrylate having two or more radical-polymerizing groups in the molecule and a weight-average molecular weight of 3000-30,000.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 15, 2014
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Shigeki Katogi, Hiroyuki Izawa, Houko Sutou, Masami Yusa, Tohru Fujinawa
  • Patent number: 8698004
    Abstract: A fabrication method for a multi-piece board includes: checking whether pieces (printed wiring boards) are defect-free or not; forming a first recess in a joint portion between a defective piece and a frame; forming a first fitting portion at the frame by separating the defective piece; cutting out a defect-free piece having a second fitting portion from another board; forming a second recess in the second fitting portion; fitting the second fitting portion into the first fitting portion; flattening a joint portion; and filling an adhesive in a third recess which is formed by the first recess and the second recess, and curing the adhesive to adhere the frame and the defect-free piece.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: April 15, 2014
    Assignee: IBIDEN Co., Ltd.
    Inventor: Yasushi Hasegawa
  • Patent number: 8692968
    Abstract: Provided are a chip component mounting structure and a chip component mounting method, wherein when a plurality of chip components having different heights are mounted on a substrate via an anisotropic conductive film, position gaps which occur when the chip components are pressure-bonded to the substrate are prevented, and the chip components can be accurately mounted to the substrate at target positions; and a liquid crystal display device provided with the substrate. In the chip component mounting structure, a position fixing resin (4) for maintaining the orientation of chip components (2) which are pressure-bonded to a substrate (1) via an anisotropic conductive film (7) is provided.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: April 8, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroki Miyazaki
  • Patent number: 8686299
    Abstract: An electronic element unit (1) includes an electronic element (2) having a plurality of connecting terminals (12) on a lower surface thereof, a circuit board (3) having a plurality of electrodes (22) corresponding to the connecting terminals (12) on an upper surface thereof. The connecting terminals (12) and the electrodes (22) are connected by solder bumps (23), and the electronic element (2) and the circuit board (3) are partly bond by a resin bond part (24) made of a thermosetting material of a thermosetting resin, and a metal powder (25) is included in the resin bond parts (24) in a dispersed state. The metal powder (25) has a melting point lower than a temperature at which the resin bond parts (24) are heated when a work (a repairing work) is carried out for removing the electronic element (2) from the circuit board (3).
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Koji Motomura, Seiichi Yoshinaga, Tadahiko Sakai
  • Publication number: 20140085551
    Abstract: The invention relates to a conducting substrate and a touch panel comprising the same. A conducting substrate according to one embodiment of the invention comprises at least one base material and at least one conductive pattern on the base material, wherein the arithmetic average roughness height (Ra) of the surface of the conductive pattern is 0.1-0.3 ?m. The conducting substrate and the touch panel comprising the same do not obstruct the view, have excellent conductivity, and can reduce the intensity of a diffraction pattern caused by reflected light.
    Type: Application
    Filed: May 16, 2012
    Publication date: March 27, 2014
    Applicant: LG CHEM, LTD.
    Inventors: Beom Mo Koo, Jaehoon Shim, Song Ho Jang, Jin Woo Park, Ji Young Hwang, Je Seob Park
  • Publication number: 20140085317
    Abstract: This disclosure provides systems, methods and apparatus for providing a transparent multilayer structure having electrical connections between conductive components disposed throughout the structure. In one aspect, a thin transparent conductive adhesive is used to provide electrical connections between layers. These electrical connections can be made throughout the multilayer structure, even in portions of the structure that overlie a display in a display device, reducing the overall footprint of a display device including such a multilayer structure.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Kristopher A. Lavery, David William Burns
  • Patent number: 8677615
    Abstract: A method for embedding at least one component into a dielectric layer. obtain a good result, it is provided that the method includes the following steps: a) Position and affix the at least one component on a carrier; b) Cast a liquid dielectric around the at least one component, thereby enclosing the at least one component completely; c) Harden the liquid dielectric to form a solid dielectric layer; and d) Apply, in particular by lamination thereon, another layer, in particular an electrically conductive layer. The use of a dielectric layer formed entirely of liquid dielectric, wherein the liquid dielectric is not converted into a solid state until the dielectric is processed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: March 25, 2014
    Assignee: DYCONEX AG
    Inventors: Marc Hauer, Markus Riester
  • Patent number: 8677618
    Abstract: A method of manufacturing a substrate using a carrier, that includes preparing a carrier having a releasing layer, and insulating layers and metal layers sequentially disposed on both sides of the releasing layer; patterning the metal layers to form base circuit layers; forming buildup layers on the base circuit layers; executing a routing process to separate the insulating layers from the releasing layer; and forming solder resist layers on the buildup layers and forming openings in the solder resist layers and the insulating layers to expose pads.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 25, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ki Hwan Kim, Jin Yong An, Myung Sam Kang
  • Patent number: 8671560
    Abstract: Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: March 18, 2014
    Assignee: Research Triangle Institute
    Inventors: Robert O. Conn, Daniel S. Stevenson
  • Patent number: 8667675
    Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: March 11, 2014
    Assignee: Sanmina Sci Corporation
    Inventor: George Dudnikov, Jr.
  • Publication number: 20140048320
    Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same, the printed circuit board including an adhesion promoter (AP) film for enhancing adhesive strength, interposed between a circuit pattern and an insulating layer above a substrate, the AP film containing any one of a first polymer, a second polymer, and an organic compound. According to the method for manufacturing the printed circuit board, there can be provided a printed circuit board having a fine circuit pattern by using the AP film having a low roughness value and having improved adhesive strength with respect to the circuit pattern.
    Type: Application
    Filed: December 7, 2012
    Publication date: February 20, 2014
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Jin Park, Yong Gwan Ko, Hye Won Jung, Joon Sung Kim
  • Patent number: 8648261
    Abstract: A printed circuit board comprises a circuit substrate, an electrically conductive cloth structure, and a shielding structure. The circuit substrate comprises a base layer, a grounded circuit layer, and a connecting pad formed on the grounded circuit layer. The cloth structure comprises an anisotropic conductive adhesive connected to the connecting pad, an insulating layer, and a metallic deposition layer arranged between the anisotropic conductive adhesive and the insulating layer. The shielding structure comprises a shielding metal layer, an adhesive matrix, and a number of electrically conductive particles electrically connected to the shielding metal layer. The insulating layer defines a number of through holes corresponding to the particles, the particles is arranged in the through holes respectively and electrically connected the metallic deposition layer and the shielding metal layer. A method for manufacturing the above PCB is also provided.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: February 11, 2014
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventor: Feng-Yan Huang