Adhesive/bonding Patents (Class 174/259)
  • Patent number: 8816214
    Abstract: A pane with an electrical connection element is described, including a substrate made of glass with a first coefficient of thermal expansion, an electrically conductive structure with a layer thickness of 5 ?m to 40 ?m on a region of the substrate, a connection element with a second coefficient of thermal expansion, and a layer of a solder material that connects the connection element electrically to subregions of the electrically conductive structure.
    Type: Grant
    Filed: February 15, 2011
    Date of Patent: August 26, 2014
    Assignee: Saint Gobain Glass France
    Inventors: Stefan Ziegler, Mitja Rateiczak, Bernhard Reul, Andreas Schlarb
  • Patent number: 8804358
    Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: August 12, 2014
    Assignee: Hypres Inc.
    Inventor: Vladimir V. Dotsenko
  • Patent number: 8802997
    Abstract: Disclosed is a PCB having multiple layers of heavy copper. A prepreg having a nonwoven glass web substrate is used alone or together with another prepreg having a glass fabric substrate so that the space between heavy copper, which is comparable to a thick film, can be filled efficiently without creating voids. The PCB includes a copper clad laminate having first copper patterned on one surface or both surfaces of a core substrate; at least one first prepreg laminated on one surface or both surfaces of the copper clad laminate, nonwoven glass web being used as the substrate of the first prepreg; at least one second prepreg laminated on one surface or both surfaces of the first prepreg, glass fabric being used as a substrate of the second prepreg; and second copper laminated on one surface or both surfaces of the second prepreg.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: August 12, 2014
    Assignee: Doosan Corporation
    Inventors: Jeong Don Kwon, Seung Min Hong, Ju Ho Shin
  • Patent number: 8803001
    Abstract: Devices, methods and systems are disclosed herein to describe the wettability characteristics of the material forming a bonding area, a non-bonding area, and a melted bonding material. The melted bonding material may have a high degree of cohesion and may result in a very high contact angle (e.g., between 90°- 180°) in the non-bonding area thereby preventing or limiting the flow of a melted material into the non-bonding area, which often results when the melted bonding material forms a low contact angle (e.g., between 0°-90°) in the bonding area. In other words, by choosing a material for the non-bonding area to have low wettability characteristics when compared to the melted materials of the bonding area or by treating the material forming the non-bonding area to have much lower wettability characteristics, the melted materials of the bonding area may be prevented from flowing into the non-bonding area.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: August 12, 2014
    Assignee: Toyota Motor Engineering & Manufacturing North America, Inc.
    Inventors: Sang Won Yoon, Satoshi Yasuda, Koji Shiozaki
  • Patent number: 8803004
    Abstract: In one embodiment, an apparatus includes a cover panel. An adhesive layer is coupled to the cover panel. A perimeter of the adhesive layer forms at least a portion of a gasket seal extending substantially perpendicular to an inner surface of the cover panel. An inner surface of the gasket seal defines an edge of a channel. The apparatus also includes a substrate coupled to the adhesive layer. The substrate includes an outer surface having disposed thereon a connection pad region and drive or sense electrodes. The drive or sense electrodes are disposed between the substrate and the cover panel. At least a portion of the channel is disposed between the gasket seal and the connection pad region. The apparatus further includes a flexible printed circuit (FPC) electrically coupled by the connection pad region to the drive or sense electrodes. A first portion of the FPC extends through the channel.
    Type: Grant
    Filed: December 31, 2012
    Date of Patent: August 12, 2014
    Assignee: Atmel Corporation
    Inventor: David Brent Guard
  • Publication number: 20140216801
    Abstract: A method of manufacturing a component-embedded substrate comprises forming an adhesive layer on a metal layer formed on a supporting plate, and mounting an electric or electronic component on the adhesive layer, wherein the component includes a component main body and a protrusion that protrudes beyond the component main body toward the adhesive layer, the adhesive layer includes a first adhesive body and a second adhesive body, the first adhesive body is formed only at a position corresponding to the protrusion, the second adhesive body is formed in an area corresponding to the whole of the surface of the component facing the adhesive layer after the first adhesive body is cured, and the component is mounted with the protrusion aligned with the first adhesive body in the component mounting step.
    Type: Application
    Filed: September 12, 2011
    Publication date: August 7, 2014
    Applicant: MEIKO ELECTRONICS CO., LTD.
    Inventors: Tohru Matsumoto, MItsuaki Toda, Yoshio Imamura
  • Patent number: 8796557
    Abstract: An adhesive film, containing a first adhesive layer in which conductive particles are dispersed, and a second adhesive layer adhered to the first adhesive layer, wherein the lowest viscosity of the first adhesive layer attained at or below the curing temperature is higher than that of the second adhesive layer attained at or below the curing temperature, where the curing temperature is a temperature at which the adhesive layer starts to cure, wherein the first and second adhesive layers are respectively disposed to a substrate side and an electronic part side, and the adhesive film is configured to join the electronic part and the substrate by heating and pressurizing the substrate and the electronic part with the adhesive layer being therebetween, and wherein the first adhesive layer has a thickness which is less than two times of an average particle diameter of the conductive particles.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 5, 2014
    Assignee: Dexerials Corporation
    Inventors: Tomoyuki Ishimatsu, Hiroki Ozeki
  • Patent number: 8787028
    Abstract: The electronic device includes a terminal structure and a printed circuit board including the terminal structure. The terminal structure includes a solder-joint conductor region placed on a wiring conductor, an intermediate layer contacting with the conductor region, and a solder region contacting with the intermediate layer. The intermediate layer includes an intermetallic compound including tin and at least one of copper and nickel as principal components. When the indentation elastic modulus of the conductor region is E1 and the indentation elastic modulus of the intermediate layer is E2, the ratio of E1 to E2 is equal to or more than 0.8 and equal to or less than 1.5.
    Type: Grant
    Filed: November 15, 2012
    Date of Patent: July 22, 2014
    Assignee: TDK Corporation
    Inventors: Yuhei Horikawa, Shin Fujita, Kenichi Yoshida, Hisayuki Abe, Makoto Orikasa, Hideyuki Seike
  • Patent number: 8780573
    Abstract: A printed circuit board includes an accommodating layer, chip capacitor devices accommodated in the accommodating layer, and a buildup structure formed on the accommodating layer such that the buildup structure covers the chip capacitor devices in the accommodating layer. The buildup structure has mounting conductor structures positioned to mount an IC chip device on a surface of the buildup structure such that the IC chip device is mounted directly over the chip capacitor devices, each of the chip capacitor devices has a dielectric body having a surface facing the buildup structure, a first electrode formed on the dielectric body and extending on the surface of the dielectric body, and a second electrode formed on the dielectric body and extending on the surface of the dielectric body, and the dielectric body is interposed between the first electrode and the second electrode.
    Type: Grant
    Filed: October 31, 2012
    Date of Patent: July 15, 2014
    Assignee: Ibiden Co., Ltd.
    Inventors: Yasushi Inagaki, Motoo Asai, Dongdong Wang, Hideo Yabashi
  • Patent number: 8780572
    Abstract: A printed circuit board that include: an electronic component having a plating electrode pad having a predetermined thickness; an insulating resin layer that exposes a lower surface of the electrode pad, receives the electronic component, and embodies the electronic component so that the center of the base body forming the electronic component is positioned at the center of the insulating resin layer; and circuit layers that include a circuit pattern disposed on the electrode pad, form inter-layer connection, and are disposed on both surfaces of the insulating resin layer, respectively, the plating electrode pad having a thickness that conforms to a thickness from an upper surface of the electronic component to an upper surface of the insulating resin.
    Type: Grant
    Filed: October 5, 2010
    Date of Patent: July 15, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Doo Hwan Lee, Tae Sung Jeong
  • Publication number: 20140182904
    Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same. The printed circuit board including an adhesive promoter interposed between an insulating layer and a circuit layer on a substrate in order to improve adhesion therebetween; and a first metal layer formed between the adhesive promoter and the circuit layer has high adhesion between an insulating layer such as a resin and a circuit while having low roughness by including a polymer adhesive promoter, easily forms a fine circuit and has low signal transmission loss due to low roughness, and has high reliability due to the high adhesion.
    Type: Application
    Filed: June 27, 2013
    Publication date: July 3, 2014
    Inventors: Yong Jin Park, Sung Gap Im, Jae Bum You, Young Gwan Ko
  • Publication number: 20140158413
    Abstract: An adhesive composition includes (A) a phenoxy resin including a plurality of hydroxyl groups at a side chain: 100 parts by mass, (B) a multifunctional isocyanate compound including an isocyanate and at least one functional group selected from the group consisting of a vinyl group, an acrylate group and a methacrylate group within its molecule: 2 to 55 parts by mass, (C) a maleimide compound and/or a reaction product thereof having a plurality of maleimide groups within its molecule: 5 to 30 parts by mass, and (D) one or more kinds of an inorganic filler having an average particle size of 5 ?m or less which is measured by a laser diffraction: 1 to 50 parts by mass, a total amount of the components (B) and (C) is 7 to 60 parts by mass.
    Type: Application
    Filed: December 11, 2013
    Publication date: June 12, 2014
    Applicant: HITACHI METALS, LTD.
    Inventors: Daisuke SHANAI, Takashi Aoyama, Kazuhiko Sasada, Hiroaki Komatsu
  • Patent number: 8749076
    Abstract: The present invention relates to a resin paste composition including an organic compound, and a granular aluminum powder having an average particle diameter of from 2 to 10 ?m and a flake-shaped silver powder having an average particle diameter of from 1 to 5 ?m which are uniformly dispersed in the organic compound, and a semiconductor device manufactured by bonding a semiconductor element onto a supporting member through the resin paste composition and then encapsulating the resulting bonded product. According to the present invention, it is possible to provide a resin paste composition used for bonding an element such as semiconductor chips onto a lead frame which is excellent in not only electrical conductivity and bonding property but also working efficiency without using a large amount of rare and expensive silver, and a semiconductor device having a high productivity and a high reliability.
    Type: Grant
    Filed: June 10, 2011
    Date of Patent: June 10, 2014
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Chiaki Okada, Kazuhiko Yamada, Yukari Inoue
  • Patent number: 8726495
    Abstract: A base material (20) is arranged on top of at least one first internal layer base material (10), and a second internal base material (30) is arranged underneath the base material (10). And thereafter a surface layer circuitry conductive foil (40) is arranged underneath the base material (30), and subsequently these materials are colaminated for forming a colaminated body (80). While this colaminating operation, conductive portions being formed in the base materials 10, 30 are aligned to electrically connect one another for forming an internal circuitry. And thereafter, an interlayer conductive portion (51) being electrically connected to the internal circuitry is formed, and a minute circuitry is formed on the top of the base material (20) and the conductive foil (40) accordingly.
    Type: Grant
    Filed: June 16, 2008
    Date of Patent: May 20, 2014
    Assignee: Fujikura Ltd.
    Inventors: Osamu Nakao, Reiji Higuchi, Syouji Ito, Masahiro Okamoto
  • Patent number: 8723050
    Abstract: An exemplary multilayer printed circuit board includes a first circuit substrate, a third circuit substrate, a second circuit substrate between the first and third circuit substrates, a first anisotropically conductive adhesive layer between the first and second circuit substrates, and a second anisotropically conductive adhesive layer between the second and third circuit substrates. The first circuit substrate includes a first conductive terminal and a first through hole. The second circuit substrate includes a second conductive terminal and two through holes (i.e. second and third through holes). The third circuit substrate includes a third conductive terminal and a fourth through hole. The first anisotropically conductive adhesive layer fills the first and third through holes to electrically connect the first and second conductive terminals. The second anisotropically conductive adhesive layer fills the second and fourth through holes to electrically connect the second and third conductive terminals.
    Type: Grant
    Filed: September 15, 2011
    Date of Patent: May 13, 2014
    Assignee: Zhen Ding Technology Co., Ltd.
    Inventor: Chien-Pang Cheng
  • Patent number: 8716401
    Abstract: A semiconductor chip laminate comprises a plurality of semiconductor chips and an adhesive layer through which the plurality of semiconductor chips are laminated, wherein the adhesive layer is composed of an adhesive composition comprising an acrylic polymer (A); an epoxy resin (B); a thermal curing agent (C); and a certain organophosphonium compound (D) as a thermal curing accelerator, and the content of the organophosphonium compound (D) relative to 100 parts by weight in total of the epoxy resin (B) and the thermal curing agent (C) is 0.001 to 15 parts by weight.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: May 6, 2014
    Assignee: Lintec Corporation
    Inventors: Yasunori Karasawa, Isao Ichikawa
  • Patent number: 8698004
    Abstract: A fabrication method for a multi-piece board includes: checking whether pieces (printed wiring boards) are defect-free or not; forming a first recess in a joint portion between a defective piece and a frame; forming a first fitting portion at the frame by separating the defective piece; cutting out a defect-free piece having a second fitting portion from another board; forming a second recess in the second fitting portion; fitting the second fitting portion into the first fitting portion; flattening a joint portion; and filling an adhesive in a third recess which is formed by the first recess and the second recess, and curing the adhesive to adhere the frame and the defect-free piece.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: April 15, 2014
    Assignee: IBIDEN Co., Ltd.
    Inventor: Yasushi Hasegawa
  • Patent number: 8698007
    Abstract: There is provided a printed circuit board including an insulating substrate having a guide hole, a solder resist layer coated on a surface of the insulating substrate, and a connection pad arranged on the surface of the insulating substrate and having an outer periphery covered with the solder resist layer and a central portion exposed in an opening formed in the solder resist layer. The solder resist layer has a positioning hole having a diameter smaller than that of the guide hole and formed by photolithography above the guide hole simultaneously with the opening.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 15, 2014
    Assignee: Kyocera SLC Technologies Corporation
    Inventor: Keizou Sakurai
  • Patent number: 8696942
    Abstract: The adhesive composition of the invention comprises a radical generator, a thermoplastic resin and a urethane(meth)acrylate having two or more radical-polymerizing groups in the molecule and a weight-average molecular weight of 3000-30,000.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: April 15, 2014
    Assignee: Hitachi Chemical Company, Ltd.
    Inventors: Shigeki Katogi, Hiroyuki Izawa, Houko Sutou, Masami Yusa, Tohru Fujinawa
  • Patent number: 8692968
    Abstract: Provided are a chip component mounting structure and a chip component mounting method, wherein when a plurality of chip components having different heights are mounted on a substrate via an anisotropic conductive film, position gaps which occur when the chip components are pressure-bonded to the substrate are prevented, and the chip components can be accurately mounted to the substrate at target positions; and a liquid crystal display device provided with the substrate. In the chip component mounting structure, a position fixing resin (4) for maintaining the orientation of chip components (2) which are pressure-bonded to a substrate (1) via an anisotropic conductive film (7) is provided.
    Type: Grant
    Filed: November 4, 2009
    Date of Patent: April 8, 2014
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Hiroki Miyazaki
  • Patent number: 8686299
    Abstract: An electronic element unit (1) includes an electronic element (2) having a plurality of connecting terminals (12) on a lower surface thereof, a circuit board (3) having a plurality of electrodes (22) corresponding to the connecting terminals (12) on an upper surface thereof. The connecting terminals (12) and the electrodes (22) are connected by solder bumps (23), and the electronic element (2) and the circuit board (3) are partly bond by a resin bond part (24) made of a thermosetting material of a thermosetting resin, and a metal powder (25) is included in the resin bond parts (24) in a dispersed state. The metal powder (25) has a melting point lower than a temperature at which the resin bond parts (24) are heated when a work (a repairing work) is carried out for removing the electronic element (2) from the circuit board (3).
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: April 1, 2014
    Assignee: Panasonic Corporation
    Inventors: Koji Motomura, Seiichi Yoshinaga, Tadahiko Sakai
  • Publication number: 20140085317
    Abstract: This disclosure provides systems, methods and apparatus for providing a transparent multilayer structure having electrical connections between conductive components disposed throughout the structure. In one aspect, a thin transparent conductive adhesive is used to provide electrical connections between layers. These electrical connections can be made throughout the multilayer structure, even in portions of the structure that overlie a display in a display device, reducing the overall footprint of a display device including such a multilayer structure.
    Type: Application
    Filed: September 27, 2012
    Publication date: March 27, 2014
    Inventors: Kristopher A. Lavery, David William Burns
  • Publication number: 20140085551
    Abstract: The invention relates to a conducting substrate and a touch panel comprising the same. A conducting substrate according to one embodiment of the invention comprises at least one base material and at least one conductive pattern on the base material, wherein the arithmetic average roughness height (Ra) of the surface of the conductive pattern is 0.1-0.3 ?m. The conducting substrate and the touch panel comprising the same do not obstruct the view, have excellent conductivity, and can reduce the intensity of a diffraction pattern caused by reflected light.
    Type: Application
    Filed: May 16, 2012
    Publication date: March 27, 2014
    Applicant: LG CHEM, LTD.
    Inventors: Beom Mo Koo, Jaehoon Shim, Song Ho Jang, Jin Woo Park, Ji Young Hwang, Je Seob Park
  • Patent number: 8677615
    Abstract: A method for embedding at least one component into a dielectric layer. obtain a good result, it is provided that the method includes the following steps: a) Position and affix the at least one component on a carrier; b) Cast a liquid dielectric around the at least one component, thereby enclosing the at least one component completely; c) Harden the liquid dielectric to form a solid dielectric layer; and d) Apply, in particular by lamination thereon, another layer, in particular an electrically conductive layer. The use of a dielectric layer formed entirely of liquid dielectric, wherein the liquid dielectric is not converted into a solid state until the dielectric is processed.
    Type: Grant
    Filed: July 8, 2011
    Date of Patent: March 25, 2014
    Assignee: DYCONEX AG
    Inventors: Marc Hauer, Markus Riester
  • Patent number: 8677618
    Abstract: A method of manufacturing a substrate using a carrier, that includes preparing a carrier having a releasing layer, and insulating layers and metal layers sequentially disposed on both sides of the releasing layer; patterning the metal layers to form base circuit layers; forming buildup layers on the base circuit layers; executing a routing process to separate the insulating layers from the releasing layer; and forming solder resist layers on the buildup layers and forming openings in the solder resist layers and the insulating layers to expose pads.
    Type: Grant
    Filed: August 30, 2011
    Date of Patent: March 25, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ki Hwan Kim, Jin Yong An, Myung Sam Kang
  • Patent number: 8671560
    Abstract: Low temperature bond balls connect two structures having disparate coefficients of linear thermal expansion. An integrated circuit is made to heat the device such that the low temperature bond balls melt. After melting, the bond balls solidify, and the device is operated with the bond balls solidified. In one example, one of the two structures is a semiconductor substrate, and the other structure is a printed circuit board. The integrated circuit is a die mounted to the semiconductor substrate. The bond balls include at least five percent indium, and the integrated circuit is an FPGA loaded with a bit stream. The bit stream configures the FPGA such that the FPGA has increased power dissipation, which melts the balls. After the melting, a second bit stream is loaded into the FPGA and the FPGA is operated in a normal user-mode using the second bit stream.
    Type: Grant
    Filed: March 30, 2010
    Date of Patent: March 18, 2014
    Assignee: Research Triangle Institute
    Inventors: Robert O. Conn, Daniel S. Stevenson
  • Patent number: 8667675
    Abstract: Systems and methods for simultaneously partitioning a plurality of via structures into electrically isolated portions by using plating resist within a PCB stackup are disclosed. Such via structures are made by selectively depositing plating resist in one or more locations in a sub-composite structure. A plurality of sub-composite structures with plating resist deposited in varying locations are laminated to form a PCB stackup of a desired PCB design. Through-holes are drilled through the PCB stackup through conductive layers, dielectric layers and through the plating resist. Thus, the PCB panel has multiple through-holes that can then be plated simultaneously by placing the PCB panel into a seed bath, followed by immersion in an electroless copper bath. Such partitioned vias increase wiring density and limit stub formation in via structures. Such partitioned vias allow a plurality of electrical signals to traverse each electrically isolated portion without interference from each other.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: March 11, 2014
    Assignee: Sanmina Sci Corporation
    Inventor: George Dudnikov, Jr.
  • Publication number: 20140048320
    Abstract: Disclosed herein are a printed circuit board and a method for manufacturing the same, the printed circuit board including an adhesion promoter (AP) film for enhancing adhesive strength, interposed between a circuit pattern and an insulating layer above a substrate, the AP film containing any one of a first polymer, a second polymer, and an organic compound. According to the method for manufacturing the printed circuit board, there can be provided a printed circuit board having a fine circuit pattern by using the AP film having a low roughness value and having improved adhesive strength with respect to the circuit pattern.
    Type: Application
    Filed: December 7, 2012
    Publication date: February 20, 2014
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Jin Park, Yong Gwan Ko, Hye Won Jung, Joon Sung Kim
  • Patent number: 8648261
    Abstract: A printed circuit board comprises a circuit substrate, an electrically conductive cloth structure, and a shielding structure. The circuit substrate comprises a base layer, a grounded circuit layer, and a connecting pad formed on the grounded circuit layer. The cloth structure comprises an anisotropic conductive adhesive connected to the connecting pad, an insulating layer, and a metallic deposition layer arranged between the anisotropic conductive adhesive and the insulating layer. The shielding structure comprises a shielding metal layer, an adhesive matrix, and a number of electrically conductive particles electrically connected to the shielding metal layer. The insulating layer defines a number of through holes corresponding to the particles, the particles is arranged in the through holes respectively and electrically connected the metallic deposition layer and the shielding metal layer. A method for manufacturing the above PCB is also provided.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: February 11, 2014
    Assignees: FuKui Precision Component (Shenzhen) Co., Ltd., Zhen Ding Technology Co., Ltd.
    Inventor: Feng-Yan Huang
  • Patent number: 8638565
    Abstract: A method for producing an arrangement of optoelectronic components (10) is specified, comprising the following steps: producing at least two fixing regions (2) on a first connection carrier (1); introducing solder material (3) into the fixing regions (2); applying a second connection carrier (4) to the fixing regions (2); and soldering the second connection carrier (4) onto the first connection carrier (1) with the solder material (3) in the fixing regions (2).
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: January 28, 2014
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rainer Sewald, Markus Kirsch
  • Patent number: 8637151
    Abstract: An objective of this invention is to provide an interlayer dielectric film with a carrier material used in a multilayer printed circuit board, which exhibits sufficient rigidity for a thin multilayer printed circuit board. According to the present invention, there is provided an interlayer dielectric film with a carrier material comprising a carrier material comprised of a metal foil or resin film and an interlayer dielectric film formed on one side of the carrier material, wherein the interlayer dielectric film is comprised of a base material impregnated with a resin; the base material has a thickness of 8 ?m to 20 ?m; and when the resin is cured at 170° C. for one hour under a pressure of 30 kgf/cm2, an elongation percentage of the interlayer dielectric film in a planar direction is 0.05% or less as determined by a TMA method.
    Type: Grant
    Filed: February 12, 2008
    Date of Patent: January 28, 2014
    Assignee: Sumitomo Bakelite Co., Ltd.
    Inventor: Toyoaki Kishi
  • Patent number: 8630097
    Abstract: Disclosed herein are a power module using sintering die attach and a manufacturing method of the same. The power module includes: a substrate having an insulating layer formed on a surface of a metal plate; a circuit layer formed on the substrate and including a wiring pattern and an electrode pattern; a device mounted on the wiring pattern; a sintering die attach layer applying a metal paste between the wiring pattern and the device and sintering the metal paste to bond the wiring pattern to the device; and a lead frame electrically connecting the device to the electrode pattern, whereby making it possible to simplify and facilitate the process, increase electrical efficiency and improve radiation characteristics, and manufacture firm and reliable power module.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: January 14, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Tae Hyun Kim, Yong Hui Joo, Seog Moon Choi
  • Patent number: 8624128
    Abstract: A printed circuit board and a manufacturing method of the printed circuit board are disclosed. The printed circuit board includes: a first insulation layer having a first pattern formed thereon; a first trench caved in one surface of the first insulation layer along at least a portion of the first pattern; and a second insulation layer stacked on one surface of the first insulation layer so as to cover the first pattern. The first trench is filled by the second insulation layer.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: January 7, 2014
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Ju-Pyo Hong, Young-Do Kweon, Jin-Gu Kim, Seon-Hee Moon, Dong-Jin Lee, Seung-Wook Park
  • Publication number: 20130342986
    Abstract: Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.
    Type: Application
    Filed: June 26, 2012
    Publication date: December 26, 2013
    Inventors: Tsung-Yu Chen, Rebecca Shia
  • Patent number: 8604354
    Abstract: A printed wiring board including: an insulated substrate; a conductive circuit provided on one side of this insulated substrate; a cover layer covering the insulated substrate and the conductive circuit; and a conductive particle buried in this cover layer, wherein the conductive particle is buried in the cover layer so that the conductive particle contacts the conductive circuit and protrudes from the cover layer; and the conductive particle serves as an electric contact point.
    Type: Grant
    Filed: December 22, 2009
    Date of Patent: December 10, 2013
    Assignee: Fujikura Ltd.
    Inventors: Shoji Ito, Tomofumi Kitada, Tadanori Ominato
  • Publication number: 20130319737
    Abstract: A multilayer electronic support structure comprising a plurality of layers extending in an X-Y plane consisting of a dielectric material surrounding metal via posts that conduct in a Z direction perpendicular to the X-Y plane, wherein a stacked via structure crossing at least two via layers of the plurality of layers comprises at least two via posts in neighboring via layers wherein the at least two stacked via posts in neighboring layers have different dimensions in the X-Y plane, such that the stacked via structure tapers.
    Type: Application
    Filed: May 29, 2012
    Publication date: December 5, 2013
    Inventor: DROR HURWITZ
  • Publication number: 20130299223
    Abstract: Disclosed are a printed circuit board and a method for manufacturing the same. The method for manufacturing the printed circuit board includes forming a base circuit board including a cavity circuit pattern in a cavity region on upper and lower portions of a substrate and internal circuit layers outside the cavity region, forming a cavity separation layer on the cavity circuit pattern, forming at least one pair of an insulating layer and a circuit layer on the base circuit board, cutting the insulating layer and the cavity separation layer provided on an etch stop pattern by controlling a focal length of a laser beam such that the laser beam reaches a surface of the base circuit board, and removing the insulating layer by separating the cavity separation layer to form the cavity. The cavity separation layer is formed on the cavity circuit pattern, and the resultant structure is cut to the cavity separation layer by using a laser so that the insulating layer is separated.
    Type: Application
    Filed: July 1, 2011
    Publication date: November 14, 2013
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Jae Hyoun Yoo, Hyung Jong Kim, Jun Soo Park, Ki Yong Lee, Jin Goo Jeon
  • Publication number: 20130284244
    Abstract: The present invention provides a transparent conductive film which is low in terms of surface resistivity and high in terms of transparency. The transparent conductive film according to the present invention includes an adhesive conductive layer in openings of a conductive metal mesh layer provided on at least one surface of a transparent base material, wherein the conductive layer is composed of a conductive adhesive composition containing (A) a water-soluble vinyl polymer, (B) an organic additive, and (C) a conductive organic polymer compound, the organic additive (B) is at least one member selected among water-soluble polyhydric alcohols, water-soluble pyrrolidones, and hydrophilic aprotic solvents, and the conductive organic polymer compound (C) is at least one member selected among polyanilines, polypyrroles, polythiophenes, and derivatives thereof.
    Type: Application
    Filed: July 20, 2011
    Publication date: October 31, 2013
    Applicant: LINTEC CORPORATION
    Inventors: Kunihisa Kato, Tsuyoshi Muto, Kazue Uemura, Emi Nakajima
  • Patent number: 8558117
    Abstract: An electroconductive ink made with metallic nanoparticles is disclosed. The ink contains an organophosphorus acid that increases adhesion between the deposited metallic layer and the substrate to which the metallic layer is applied.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: October 15, 2013
    Assignee: Aculon, Inc.
    Inventor: Eric L. Hanson
  • Patent number: 8558116
    Abstract: The present invention provides a multilayer rigid flexible printed circuit board including: a flexible region including a flexible film having a circuit pattern formed on one or both surfaces thereof and a laser blocking layer formed on the circuit pattern; and a rigid region formed adjacent to the flexible region and including a plurality of pattern layers on one or both surfaces of extended portions extended to both sides of the flexible film of the flexible region, and a method for manufacturing the same.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: October 15, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yang Je Lee, Dek Gin Yang, Dong Gi An, Jae Ho Shin
  • Patent number: 8557392
    Abstract: In order to provide a flexible laminate circuit board using a surface treated copper foil satisfying all of a bonding strength of a copper foil with respect to polyimide, acid resistance, and etching property, in a flexible laminate circuit board formed by a copper foil on the surface of a polyimide resin layer, the copper foil is a surface treated copper foil formed by depositing an Ni—Zn alloy onto at least one surface of a untreated copper foil, and the Zn deposition amount in the deposited Ni—Zn alloy is 6% or more and 15% or less of the (Ni deposition amount+Zn deposition amount), and the Zn deposition amount is 0.08 mg/dm2 or more to provide a flexible copper clad laminate.
    Type: Grant
    Filed: July 22, 2009
    Date of Patent: October 15, 2013
    Assignees: Furukawa Electric Co., Ltd., Nippon Steel & Sumikin Chemical Co., Ltd.
    Inventors: Satoshi Fujisawa, Yuji Suzuki, Takeo Uno, Koichi Hattori, Naoya Kuwasaki
  • Patent number: 8559185
    Abstract: An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: October 15, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Sang-Ho Lee, Soo-San Park, DaeSik Choi
  • Patent number: 8552310
    Abstract: A mounting structure of an electronic component includes: a bump electrode included in the electronic component, the bump electrode having an internal resin as a core and a conductive film covering a surface of the internal resin, and elastically deforming so as to follow a shape of at least one corner of a terminal so that the conductive film makes direct conductive contact with at least part of a top surface of the terminal and at least part of a surface along a thickness direction of the terminal; a substrate having the terminal and the electronic component that is mounted on the substrate; and a holding unit provided to the substrate and the electronic component so as to hold a state in which the bump electrode electrically deformed makes conductive contact with the terminal.
    Type: Grant
    Filed: January 9, 2012
    Date of Patent: October 8, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 8528195
    Abstract: A layout method for electronic components of a double-sided surface mount circuit board is presented, which includes the following steps. At least one first electronic component is fixed on a first side surface of a circuit board through a reflow soldering process. At least one second electronic component is inserted on the first side surface of the circuit board. The other first electronic component is placed on a second side surface of the circuit board, and the other second electronic component is inserted on the second side surface of the circuit board. Finally, a reflow soldering process is performed on the circuit board disposed with the first electronic components and the second electronic components, thereby completing a layout process for the electronic components on the two side surfaces of the circuit board at the same time.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: September 10, 2013
    Assignee: Inventec Corporation
    Inventors: Chung-Yang Wu, Hung-Tao Wong
  • Patent number: 8530753
    Abstract: At least one electronic component having a plurality of terminals on one of surfaces is temporarily fixed to a surface of a first support with a first adhesive layer in such a manner that the terminal side of the electronic component faces the first support. A second support having a second adhesive layer is fixed to the electronic component in order to interpose the electronic component between the first support and the second support. The first support and the first adhesive layer are peeled. The electronic component on the second support is sealed with a sealing resin in such a manner that at least a part of the terminals of the electronic component is exposed. An insulating resin layer and a wiring layer to be electrically connected to the terminal of the electronic component are stacked on the electronic component and the sealing resin.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: September 10, 2013
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Yuji Kunimoto, Akihiko Tateiwa
  • Publication number: 20130220687
    Abstract: Disclosed is a wafer process body, a temporary adhesive layer is formed on a supporting body, and a wafer having a circuit-formed front surface and a to-be-processed back surface is stacked on the temporary adhesive layer, wherein the temporary adhesive layer is provided with a first temporary adhesive layer including a non-aromatic saturated hydrocarbon group-containing organopolysiloxane layer (A) which is adhered to the front surface of the wafer so as to be detachable and a second temporary adhesive layer comprised of a thermosetting-modified siloxane polymer layer (B) which is stacked on the first temporary adhesive layer and adhered to the supporting body so as to be detachable. Thus, temporary adhesion of a wafer with a supporting body may become easy, process conformity with the TSV formation process and with the wafer-back surface-wiring process may become high, and removal may be done easily, with high productivity.
    Type: Application
    Filed: February 19, 2013
    Publication date: August 29, 2013
    Applicant: SHIN-ETSU CHEMICAL CO., LTD.
    Inventor: SHIN-ETSU CHEMICAL CO., LTD.
  • Patent number: 8519530
    Abstract: Disclosed is a composition, in particular a dispersion, which contains nanofiber material in at least one organic matrix component, said nanofiber material being pre-treated in at least one method step for adjusting the physical properties of the composition.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: August 27, 2013
    Assignee: Curamik Electronics GmbH
    Inventors: Ka Chun Tse, Ben Zhong Tang, Ernst Hammel, Xinhe Tang
  • Patent number: 8520402
    Abstract: Decoupling capacitor circuit assembly is described. In one example, a circuit assembly includes a passive substrate, a plurality of terminals, and at least one capacitor. The passive substrate includes a top surface and a bottom surface. The plurality of terminals is formed on the top surface and is configured for electrical communication with a respective plurality of lands on a printed circuit board (PCB). The at least one capacitor is mounted to the bottom surface of the passive substrate and is configured to provide decoupling capacitance for an integrated circuit (IC) on the PCB. Each capacitor is coupled to a pair of the plurality of terminals. In another example, a circuit assembly includes a PCB, and IC mounted to the PCB, a passive substrate mounted to the PCB, and at least one capacitor mounted to the passive substrate for providing decoupling capacitance for the IC.
    Type: Grant
    Filed: October 25, 2005
    Date of Patent: August 27, 2013
    Assignee: Xilinx, Inc.
    Inventor: Suresh Sivasubramaniam
  • Patent number: 8519273
    Abstract: A circuit subassembly, comprising: a conductive layer, a dielectric layer formed from a thermosetting composition, wherein the thermosetting composition comprises, based on the total weight of the thermosetting composition a polybutadiene or polyisoprene resin, about 30 to about 70 percent by weight of a magnesium hydroxide having less than about 1000 ppm of ionic contaminants, and about 5 to about 15 percent by weight of a nitrogen-containing compound, wherein the nitrogen-containing compound comprises at least about 15 weight percent of nitrogen; and an adhesive layer disposed between and in intimate contact with the conductive layer and the dielectric layer, wherein the adhesive comprises a poly(arylene ether), wherein the circuit subassembly has a UL-94 rating of at least V-1.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: August 27, 2013
    Inventors: Sankar Paul, Dirk M. Baars
  • Patent number: 8514587
    Abstract: The present disclosure relates to a conductive structure. The conductive structure includes a first conductive layer, a conductive unit, a circuit board and a conductive material. The conductive unit is disposed on the first conductive layer. The circuit board having a first through hole is disposed on the first conductive layer. The conductive unit is exposed to the first through hole. The first through hole is filled with a conductive material, such that the conductive material is electrically connected to the conductive unit.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: August 20, 2013
    Assignees: Innocom Technology (Shenzhen) Co., Ltd., Chimei Innolux Corporation
    Inventors: Jun-Yong Zhang, Peng Wang