Abstract: An electrical assembly includes a first lead, a second lead, and an electrical component extending from a first end to a second end. A first non-electrically conductive adhesive member mechanically connects the first lead to the first end of the electrical component. A second non-electrically conductive adhesive member mechanically connects the second lead to the second end of the electrical component. A first electrically conductive adhesive member electrically connects the first lead to the first end of the electrical component. A second electrically conductive adhesive member electrically connects the second lead to the second end of the electrical component.

Abstract: An embedded chip substrate includes a first insulation layer, a core layer, a chip, a second insulation layer, a first circuit layer, and a second circuit layer. The core layer disposed on the first insulation layer has an opening that exposes a portion of the first insulation layer. The chip is adhered into a recess constructed by the opening and the first insulation layer. The second insulation layer is disposed on the core layer for covering the chip. The first circuit layer is disposed at the outer side of the first insulation layer located between the first circuit layer and the core layer. The second circuit layer is disposed at the outer side of the second insulation layer located between the second circuit layer and the core layer. The first circuit layer is electrically connected to the second circuit layer that is electrically connected to the chip.

Abstract: A semiconductor apparatus includes a multilayer interposer substrate including a power layer as an inner layer; a plurality of connection terminals provided on one surface of the interposer substrate; and a semiconductor chip mounted on the other surface of the interposer substrate. Among power terminals, ground terminals, and signal terminals provided in the semiconductor apparatus, all the power terminals are arranged in one power area and the power area includes only the power terminals.

Abstract: A flexible multilayer substrate includes a stacked body including a plurality of stacked resin layers and defining a flexible portion. The stacked body includes an innermost surface located inside and an outermost surface located outside when the stacked body is bent in use. A plurality of conductor patterns are arranged inside the stacked body to be distributed over a surface of one or more of the plurality of resin layers. A portion located on the innermost surface side with respect to a center plane of the stacked body in a thickness direction is a first portion, and a portion located on the outermost surface side with respect to the center plane is a second portion. An area having a minimum spacing along the longitudinal direction between the conductor patterns arranged in the same plane, in all of the plurality of resin layers, is located in the second portion.

Abstract: An optical device includes: an optical integrated circuit chip that comprises an optical integrated circuit and an optical interface connected thereto; an electronic circuit chip that comprises an electronic circuit connected to the optical integrated circuit; a through wiring board that comprises a through wiring connected to the electronic circuit chip; a first bump that connects the optical integrated circuit and the electronic circuit between the optical integrated circuit chip and the electronic circuit chip; a second bump that connects the electronic circuit and the through wiring between the electronic circuit chip and the through wiring board; and a third bump connected to an end portion on an opposite side to the second bump of the through wiring. The optical integrated circuit chip and the through wiring board are disposed on a side of a first main surface of the electronic circuit chip.

Abstract: A wiring board on which an electronic component is to be mounted includes a resist having an opening exposing a joint face which is part of the surface of a wiring layer and to which a terminal of the electronic component is to be joined. In the placing step, the electronic component is placed on the wiring board such that the terminal covers the opening entirely and contacts the solder paste applied onto the joint face. Next, the solder paste applied onto the joint face is heated to melt solder and soften thermosetting resin. This allows the solder to gather in a first space within the opening closed with the wiring layer and the electronic component, while allowing the thermosetting resin to gather in a second space formed between a top side of the resist and a lateral side of the electronic component.

Abstract: A method of making a semiconductor device is characterized by the step of attaching a chip-on-interposer subassembly to a heat spreader with the chip inserted into a cavity of the heat spreader and the interposer laterally extending beyond the cavity. The interposer backside process is executed after the chip-on-interposer attachment and encapsulation to form the finished interposer. The heat spreader provides thermal dissipation, and the finished interposer provides primary fan-out routing for the chip. In the method, a buildup circuitry is electrically coupled to the interposer to provide further fan-out routing.

Abstract: A hermetically packaged microelectromechanical system (MEMS) device has a substrate with an assembly pad (101) and a plurality of terminals (102); a chip (110) with a MEMS mechanical element (111) of a first height (111a) assembled on the pad and connected to the terminals by wires (120) with an insulating coat (121); a ridge (130) on the substrate, which surrounds the MEMS element (111) with a second height (130c) greater than the first height and comprises a plastic compound (131) filled with particles (132) and a surface (130a, 130b) having an adhering moisture-impermeable seal layer (133); and a moisture-impervious lid (140) attached to the ridge by moisture-proof bonds (150, 151), sealing the volume (160) enclosed by the lid, the chip, and the metalized ridge as a hermetic space for the MEMS element (111).

Abstract: A light emitting semiconductor element includes at least two electrically conductive units, at least a light emitting semiconductor die and a light transmitting layer. A groove is located between the two electrically conductive units. The light emitting semiconductor die is cross over the electrically conductive units. The light transmitting layer covers the light emitting semiconductor and partially fills within the groove for linking the electrically conductive units.

Abstract: A wiring board with built-in capacitors includes a core substrate, and a high dielectric sheet including a lower electrode layer, an upper electrode layer and a dielectric layer, the dielectric layer made of a sintered ceramic body and sandwiched between the lower electrode layer and the upper electrode layer, the lower electrode layer and/or the upper electrode layer being partitioned into multiple electrodes such that the high dielectric sheet has multiple capacitors. The lower electrode layer and/or the upper electrode layer is connected to a ground line and the other one of the lower electrode layer and the upper electrode layer is connected to a power line such that the capacitors are electrically connected in parallel.

Abstract: A pixel structure includes a first conductive layer, a semiconductor layer, an insulating layer, a second conductive layer, a passivation layer, and a first electrode layer. The first conductive layer includes a scan line and a bottom electrode. The semiconductor layer includes a first semiconductor pattern having a first source region, a first drain region, and a first channel region. The insulating layer is disposed on the semiconductor layer. The second conductive layer is disposed on the insulating layer and includes a top electrode, a first gate, a first source, a first drain, and a data line connected with the first source. The bottom electrode and the top electrode overlap to form a capacitor. The passivation layer covers the first and second conductive layers and the semiconductor layer. The first electrode layer is disposed on the passivation layer and provides electrical connection to different layers.

Abstract: A circuit layout structure is suitable for a circuit board and includes following components. A first differential pair and a second differential pair respectively extend from the inside of a chip area of the circuit board to the outside of the chip area through a first patterned conductive layer of the circuit board, and respectively extend between the chip area and a port area of the circuit board through a second patterned conductive layer of the circuit board. A third differential pair extends from the chip area to the port area through the first patterned conductive layer. A first ground plane is constituted by the first patterned conductive layer. Orthogonal projections of the first differential pair and the second differential pair on the second patterned conductive layer overlap the first ground plane.

Abstract: A wiring substrate includes: a connection pad having a first surface; a protective insulation layer formed on the first surface of the connection pad and having an opening portion therein, wherein a portion of the first surface of the connection pad is exposed from the opening portion; a metal layer having a lower surface facing the first surface of the connection pad and an upper surface opposite to the lower surface and formed on the first surface of the connection pad which is exposed from the opening portion, the metal layer including a raised portion that extends upward from the upper surface of the metal layer in a peripheral portion thereof; and a bump electrode formed on the upper surface of the metal layer.

Abstract: There is provided a multilayer ceramic capacitor, including a ceramic body including a plurality of dielectric layers stacked in a width direction and having upper and lower surface, first and second side surfaces, and first and second end surfaces, a first internal electrode formed on the dielectric layer and including a first lead part exposed to the upper and lower surfaces, a second internal electrode facing the first internal electrode, having at least one dielectric layer therebetween and having a second lead part exposed to the upper and lower surfaces, a first external electrode, a second external electrode, a first dummy pattern, and a second dummy pattern, wherein when a length of the ceramic body is B, a distance of the first lead part is C1, and a distance of the first dummy pattern is C3, 0.1?(C1+C3)/B?0.6 is satisfied.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body, first and second capacitor parts, first and second internal connection conductors, and first to fourth external electrodes, wherein the first capacitor part is connected to the first connection conductor in series, and the second capacitor part is connected to the second connection conductor in series, the second connection conductor being connected to the first connection conductor in series.

Abstract: A double sided board with buried element and a method for manufacturing the same are disclosed. At least one buried element is fixed on a dielectric layer and embedded in an insulation layer. First and second electrical circuits are formed on upper and lower surfaces of the insulation layer, respectively. At least one through-hole is formed in the insulation layer and filled with a conductive layer to electrically connect the first and the second electrical circuits. The dielectric layer beneath the buried element and the insulation layer above the buried element are provided with at least one opening, respectively, which is filled with the conductive layer, thereby connecting the conductive layer and external circuits or electrical elements. Additionally, the first and second electrical circuits are covered with first and second solder masks, respectively, so as to avoid environmental effect and improve preciseness of the circuits.

Abstract: A process of making efficient metal bump bonding with relative low temperature, preferably lower than the melting point of Indium, is described. To obtaining a lower processing temperature (preferred embodiments have a melting point of <100° C.), a metal or alloy layer is deposited on the indium bump surface. Preferably, the material is chosen such that the metal or alloy forms a passivation layer that is more resistant to oxidation than the underlying indium material. The passivation material is also preferably chosen to form a low melting temperature alloy with indium at the indium bump surface. This is typically accomplished by diffusion of the passivation material into the indium to form a diffusion layer alloy. Various metals, including Ga, Bi, Sn, Pb and Cd, that can be used to form a binary to quaternary low melting point alloy with indium.

Abstract: A printed wiring board includes a core substrate including an insulative substrate, a first conductive layer formed on first surface of the insulative substrate, and a second conductive layer formed on second surface of the insulative substrate, a first buildup laminated on first surface of the core and including an interlayer insulation layer, a conductive layer formed on the insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer, and a second buildup laminated on second surface of the core and including an interlayer insulation layer, a conductive layer formed on the interlayer insulation layer, and a via conductor penetrating through the insulation layer and connected to the conductive layer. The insulation layer of the first buildup has thermal expansion coefficient set higher than thermal expansion coefficient of the insulation layer of the second buildup.

Abstract: The invention discloses a package structure with an overlaying metallic material overlaying a solder material. A substrate comprises a first solder pad and a second solder pad thereon. A conductive element on the substrate comprises a first electrode and a second electrode thereon. A solder material electrically connects the first solder pad and the second solder pad to the first electrode and the second electrode respectively. An overlaying metallic material overlays the exposed areas of the solder metallic material, the first solder pad, the second solder pad, the first electrode and the second electrode, wherein the exposed areas comprise metallic material having a lower melting point than the second metallic material.

Abstract: A multilayer ceramic electronic component includes a ceramic main body including dielectric layers and satisfying T/W>1.0 when W and T are width and thickness, respectively; and first and second internal electrodes stacked in the ceramic main body and facing each other with the dielectric layer interposed therebetween, the ceramic main body including an active layer corresponding to a capacitance forming portion contributing to capacitance formation and a cover layer corresponding to a non-capacitance forming portion provided on at least one of uppermost and lowermost surfaces of the active layer, and when the active layer is divided into three regions in a direction in which the first and second internal electrodes are stacked, an average width of internal electrodes in a central region of the three regions is Wa, and an average width of internal electrodes in upper and lower regions of the three regions is Wb, 0.920?Wb/Wa?0.998 is satisfied.

Abstract: A power supply control IC is mounted on a surface of a multilayer body that defines a power supply control circuit module. A first inner-layer electrode connecting an inductor element and a switching regulator element for the power supply control IC, another first inner-layer electrode connecting the inductor element and a capacitor element, and still another first inner-layer electrode connecting the switching regulator element and the capacitor element are located on upper layer regions of the multilayer body and are routed in between a mounting area of the power supply control IC and a peripheral wall of the multilayer body. The first inner-layer electrodes have widths that are wider than those of second inner-layer electrodes which are located near a center region of the multilayer body and transmit control signals.

Abstract: Systems (100) and methods (600) for recharging a battery (292) of an electronic device (102) which has been placed in a cradle (106) of a charging dock (104). The methods involve: measuring a charging voltage value and a charging current value for the electronic device; determining a first value of angular orientation for a current position of the electronic device relative to a reference angular orientation of the electronic device; selecting at least one first indicator from a plurality of indicators based on the charging voltage value, the charging current value, and the first value of angular orientation; and outputting a first indicator to the user of the electronic device.

Abstract: There is provided a substrate with built-in component, including a metal core layer having a cavity for storing a component; a wiring layer that is laminated on the core layer and has a plurality of vias for an interlayer connection, the vias being formed at regions opposing to the cavity; and an electronic component including a plurality of terminals electrically connected to the plurality of vias, and a component body that is stored in the cavity and has a support surface for supporting the plurality of terminals, the plurality of terminals being disposed eccentrically from a center of the support surface to a first direction, and the component body being disposed eccentrically from a center of the cavity to a second direction opposite to the first direction.

Abstract: A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.

Abstract: To achieve a reduction in cost of a semiconductor device, in a common board (a wiring board), a plurality of bonding leads each extend toward the center of the board, and a solder resist film as a die bonding region supporting a minimum chip is coated with a die bonding material. With this, even when a first semiconductor chip as a large chip is mounted, wire bonding can be performed without causing the die bonding material to cover the bonding leads. Thus, development cost can be reduced to reduce the cost of the semiconductor device (LGA).

Abstract: In a multilayer capacitor, a dimension of a third terminal electrode on a second main surface in a length direction is greater than a dimension of first and second terminal electrodes on the second main surface in the length direction. The first to third terminal electrodes extend across the second main surface from one end to the other end in a width direction and have a thickest portion at a portion on a side of the other end beyond the center portion in the width direction, and the thickest portion projects toward the center in the length direction.

Abstract: An apparatus for conveying an electrical signal includes: a conductive pathway having a conductive material. The conductive material has a first edge and a second edge and is configured to convey the electrical signal. The apparatus also includes a resistive material in contact with at least a portion of the conductive pathway, covering an edge of the conductive pathway, and extending beyond the edge. The resistive material has a conductivity less than the conductivity of the conductive material.

Abstract: A curable epoxy resin composition including (a) at least one epoxy resin; and (b) at least one hardener; wherein the curable epoxy resin composition has at least two exotherm peaks representing at least two distinct chemical reactions and wherein the exothermic peak difference of the two exotherm peaks is sufficient to allow the curable epoxy resin composition of being B-staged.

Abstract: An integrated circuit assembly includes a main board unit mounted fixedly on and connected electrically to an external circuit board, a daughter board unit disposed on and connected detachably to the main board unit, and an integrated circuit device mounted fixedly on and connected electrically to the daughter board unit. When the daughter board unit is connected to the main board unit, the integrated circuit device is connected electrically to the external circuit board via the main board unit and the daughter board unit.

Abstract: Provided is an antioxidant gas supply unit including: a base body (10) in a shape of a hollow plate having antioxidant gas flow paths (53) and (54) defined therein; an antioxidation gas inlet (20) for letting an antioxidant gas flow into the antioxidant gas flow paths (53) and (54); a through hole (30) penetrating through the base body (10) in a through-thickness direction so that a capillary (72) is allowed to be inserted into and removed from the hole, and communicating with the antioxidant gas flow paths (53) and (54) to let the antioxidant gas flow out; and a film heater (40) attached to an outer surface of the base body (10) around the through hole (30). The antioxidant gas supply unit has a compact structure and is capable of effectively heating a free air ball.

Abstract: A wiring substrate is provided with a core substrate including a first main surface, a second main surface, and a through hole. An electronic component including a resin cover is arranged in the through hole. A projection projects from an inner wall of the through hole toward the resin cover of the electronic component. An insulator is filled between the inner wall of the through hole and the electronic component. A first insulation layer covers the electronic component and the first main surface. A second insulation layer covers the electronic component and the second main surface. The resin cover of the electronic component includes an engagement groove formed by the projection and extending along a direction in which the electronic component is fitted into the through hole.

Abstract: The present invention discloses an electronic component embedded substrate and a manufacturing method thereof. The electronic component embedded substrate in accordance with an embodiment of the present invention includes: a core board having a cavity formed therein; an electronic component being embedded in the cavity; and a circuit pattern formed on one surface of the core board and configured for fixing the electronic component in the cavity by pressing the electronic component.

Abstract: An electrical apparatus, comprising a circuit board, and a capacitor installed on the circuit board; the capacitor is detachably installed on the circuit board. The capacitor can be conveniently detached from the circuit board; therefore, a damaged capacitor can be easily replaced with a new capacitor, saving cost by avoiding the problem in the prior art that the entire electrical apparatus is discarded or causes downtime for repairs due to a damaged capacitor.

Abstract: Solder material used in soldering of an Au electrode including Ni plating containing P includes Ag satisfying 0.3?[Ag]?4.0, Bi satisfying 0?[Bi]?1.0, and Cu satisfying 0?[Cu]?1.2, where contents (mass %) of Ag, Bi, Cu and In in the solder material are denoted by [Ag], [Bi], [Cu], and [In], respectively. The solder material includes In in a range of 6.0?[In]?6.8 when [Cu] falls within a range of 0<[Cu]<0.5, In in a range of 5.2+(6?(1.55×[Cu]+4.428))?[In]?6.8 when [Cu] falls within a range of 0.5?[Cu]?1.0, In in a range of 5.2?[In]?6.8 when [Cu] falls within a range of 1.0<[Cu]?1.2. A balance includes only not less than 87 mass % of Sn.

Abstract: A wiring body connection structure includes a first wiring body and a second wiring body, the first wiring body having a first base material made of an elastomer and a first wiring containing an elastomer and a conductive material, the second wiring body having a second base material and a second wiring. In the wiring body connection structure, a laminated section is partitioned where a first end of the first wiring body and a second end of the second wiring body overlap in a front-rear direction. The wiring body connection structure further includes a cover member arranged on a front surface of the first wiring body, and a conductive adhesive layer bonding the first end and the second end in the laminated section while ensuring a conductive property. The cover member is interposed between a frontmost end of the second end and the first wiring in the laminated section.

Abstract: The present invention discloses a tape substrate for chip on film structure of a liquid crystal panel. The tape substrate is provided with plural package units of chip on film structures arranged along its longitudinal direction, and the package unit has a driver chip, input leads and output leads. The longitudinal direction of the driver chip is parallel to the longitudinal direction of the tape substrate, and the input leads and the output leads are located at the two opposite sides of the driver chip. Each package unit is set up with a short side and a long side, and the input leads are formed at the short side, while the output leads are formed at the long side. In the package units adjacent to each other, the short side of one package unit joins the long side of a next package unit. This invention further discloses a liquid crystal panel having the tape substrate.

Abstract: There is provided a multilayer ceramic electronic component comprising a ceramic body having a hexahedral shape, including dielectric layers, and satisfying T/W>1.0 when a length of the ceramic body is defined as L, a width of a lower surface thereof is defined as W, and a thickness thereof is defined as T, and first and second internal electrodes stacked in the ceramic body to face each other, having the respective dielectric layers therebetween, wherein the ceramic body includes an active layer and cover layers and in a case in which the active layer is divided into three regions in a thickness direction of the ceramic body, when an average thickness of the internal electrodes in an upper region and an average thickness of the internal electrodes in a lower region, based on a central region, are defined as ta and tb, respectively, 0.751?ta/tb?0.913 is satisfied.

Abstract: A wiring board includes a first multilayer wiring board having first conductive layers and having a surface, a second multilayer wiring board having second conductive layers and positioned such that the second multilayer wiring board has a surface facing the surface of the first multilayer wiring board, and an adhesive layer including an adhesive sheet and interposed between the first multilayer wiring board and the second multilayer wiring board such that the adhesive layer is adhering the first multilayer wiring board and the second multilayer wiring board. The first multilayer wiring board has a first pad on the surface of the first multilayer wiring board, the second multilayer wiring board has a second pad on the surface of the second multilayer wiring board, and the first pad and the second pad are positioned such that the first pad and the second pad face each other across the adhesive layer.

Abstract: In a display device (100), a row of protruding electrodes (115) and a row of protruding electrodes (116) are formed on the connecting surface of a terminal section (112), the row of the protruding electrodes (116) is disposed between the row of the protruding electrodes (115) and a display section (111), one end of a flexible printed board (150) is connected to the row of the protruding electrodes (115), one end of a flexible printed board (160) is connected to the row of the protruding electrodes (116), the row of the protruding electrodes (115) is adjacent to the row of the protruding electrodes (116), and the one end of the flexible printed board (150) and the one end of the flexible printed board (160) are opposed to each other.

Abstract: An electronic component includes an interposer, and a multilayer ceramic capacitor. The interposer includes a substrate including front and back surfaces that are parallel or substantially parallel to each other. Two first mounting electrodes and two second mounting electrodes are located on the front surface of the substrate, on opposite end portions in the longitudinal direction. Recesses are located in the longitudinal side surface of the insulating substrate. Connecting conductors are each provided in the side wall surface of each of the recesses. The connecting conductors connect a first external connection electrode and a second external connection electrode that are located on the back surface of the substrate, and first mounting electrodes and second mounting electrodes.

Abstract: There is provided a multilayer ceramic electronic component including: a ceramic body including dielectric layers; and a plurality of internal electrodes disposed in the ceramic body, having at least one of the dielectric layers interposed therebetween, wherein when a distance between a widthwise end of an internal electrode disposed at a central portion of the ceramic body in a thickness direction thereof and an adjacent side surface of the ceramic body is defined as D1 and a distance between a widthwise end of an internal electrode disposed at an upper or lower portion of the ceramic body in the thickness direction thereof and the adjacent side surface of the ceramic body is defined as D2, D1/D2 is in a range of 0.5 to 0.95 (0.5?D1/D2?0.95).

Abstract: A multilayer ceramic electronic component is provided including a ceramic body having dielectric layers and a plurality of internal electrodes disposed in the ceramic body. The internal electrodes have exposed portions exposed to the exterior of the ceramic body. An electrode layer is disposed on an outer surface of the ceramic body electrically connected to the exposed portions of the internal electrodes A conductive resin layer is disposed on the electrode layer. The electrode layer has an uneven surface.

Abstract: A stacked arrangement of metal oxide varistors includes a plurality of metal oxide varistors with each metal oxide varistor of the plurality of metal oxide varistors having a first lead on a first surface and a second lead on a second surface, the first surface and the second surface being opposite facing surfaces of each metal oxide varistor. The first lead and the second lead of adjacent metal oxide varistors, when placed in a stacked arrangement, are arranged, preferably asymmetrically, and having the same voltages so as not to interfere with one another, thereby result in a more compact stacking of metal oxide varistors, as compared to arrangements known to the state of the art. The stacked arrangement of metal oxide varistor can be mounted on printed circuit boards, in addition to a variety of other uses.

Abstract: According to one embodiment, an electronic device includes a printed circuit board on which mounted is a multilayer ceramic capacitor includes a rectangular parallelepiped capacitor main body in which a pair of external electrodes are formed on both ends in a shorter side. The electronic device has a mount structure in which portions of the pair of external electrodes are soldered to the printed circuit board while setting a width of first and second pads provided respectively on the pair of external electrodes less than a width of the pair of external electrodes.

Abstract: Electronic devices to output signals at different frequencies are mounted to a circuit board that has a group of layers, where the group of layers include reference plane layers and signal layers between the reference plane layers. A first signal layer has conductive traces having a first dimension to communicate the signals at a first frequency, and a second signal layer has conductive traces having a second, different dimension to communicate signals at a second, different frequency. The first and second signal layers are successive layers without any reference plane layer in between the first and second signal layers.

Abstract: Embodiments of the present disclosure are directed towards a circuit board having integrated passive devices such as inductors, capacitors, resistors and associated techniques and configurations. In one embodiment, an apparatus includes a circuit board having a first surface and a second surface opposite to the first surface and a passive device integral to the circuit board, the passive device having an input terminal configured to couple with electrical power of a die, an output terminal electrically coupled with the input terminal, and electrical routing features disposed between the first surface and the second surface of the circuit board and coupled with the input terminal and the output terminal to route the electrical power between the input terminal and the output terminal, wherein the input terminal includes a surface configured to receive a solder ball connection of a package assembly including the die. Other embodiments may be described and/or claimed.

Abstract: A connecting member such as a terminal base is used in connection with a printed circuit board unit in which circuit elements such as a power module are mounted on a printed circuit board. The connecting member connects the circuit element of an electrical circuit including the printed circuit board, to an electrical wire. The connecting member includes a terminal connecting section to be directly connected to terminal pins of the circuit element; a wire connecting section to be connected to the electrical wire; and attachment sections for attaching the connecting member to the printed circuit board.

Abstract: A multilayered printed circuit board or a substrate for mounting a semiconductor device includes a semiconductor device, a first resin insulating layer accommodating the semiconductor device, a second resin insulating layer provided on the first resin insulating layer, a conductor circuit provided on the second resin insulating layer, and via holes for electrically connecting the semiconductor device to the conductor circuit, wherein the semiconductor device is accommodated in a recess provided in the first resin insulating layer, and a metal layer for placing the semiconductor device is provided on the bottom face of the recess. A multilayered printed circuit board in which the installed semiconductor device establishes electrical connection through the via holes is provided.

Abstract: An apparatus capable of selectively applying different types of connectors to a substrate is disclosed. The memory apparatus includes a substrate having a controller. First and second connector pads may be arranged on edges of top and bottom surfaces of the substrate. A via hole may be arranged between the controller and the first and second connector pads. A first passive device pad may be arranged between the via hole and the first connector pads. A second passive device pad may be arranged between the via hole and the second connector pads. A passive device may be coupled to only one of the first passive device pad or the second passive device pad.

Abstract: A base insulating layer is formed on a suspension body. Read wiring patterns, write wiring patterns and a ground pattern are formed in parallel on the base insulating layer. A first cover insulating layer is formed on the base insulating layer to cover the read wiring patterns, the write wiring patterns and the ground pattern. A ground layer is formed in a region on the first cover insulating layer above the write wiring patterns. A second cover insulating layer is formed on the first cover insulating layer to cover the ground layer.