Abstract: A system and method reduce stiction while manipulating micro objects on a surface. The system and method employed a field generator configured to generate a driving force at a frequency and amplitude to at least partially overcome stiction between the micro objects and the surface. The field generator is further configured to generate a manipulation force to manipulate the micro objects on the surface in two dimensions. The manipulation force is spatially programmable.

Abstract: A switch arrangement may include at least one carrier having a first side and a second side and a plurality of electrically conductive through connections extending from the first side to the second side; a first switch terminal on the first side; a second switch terminal on the second side; a plurality of electronic switching devices arranged on the first side, each electronic switching device comprising a first controlled terminal and a second controlled terminal; wherein each first controlled terminal is connected to the first switch terminal via a respective electrically conductive connection; wherein the electrically conductive connections have substantially the same length; and wherein each second controlled terminal is connected to a respective through connection to connect the second switch terminal.

Abstract: A wireless display sink device comprises a display panel driver and a PCB (Printed Circuit Board) connected to a wireless communication module. The PCB comprises: a decoder that decodes audio/video data received from the wireless communication module and separates audio data and video data; an audio DAC (Digital Analog Converter) that converts the audio data into an analog voltage; and a timing controller that transmits the video data to the display panel driver and controls the operation timing of the display panel driver.

Abstract: A high frequency circuit device that can avoid an occurrence of a stress concentration to a dielectric substrate during a temperature increase caused by a difference in coefficients of linear expansions of a chassis and a metal housing of a high frequency module is provided.

Abstract: A display device includes a display panel including panel bumps, a flexible circuit film connected to the display panel and including a chip, and panel bonding leads connecting the display panel to the chip. The panel bumps include first panel bumps arranged along a first row, and second panel bumps arranged along a second row which is spaced apart from the first row toward the chip. Each second panel bump is disposed between two adjacent first panel bumps when viewed from a column direction perpendicular to a row direction. The panel bonding leads includes first panel bonding leads connected to the first panel bumps and second panel bonding leads connected to the second panel bumps. Each first panel bonding lead includes a first portion having a first thickness, and a second portion adjacent to the second panel bump having a second thickness smaller than the first thickness.

Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.

Abstract: An engagement structure for preventing the separation of a resin layer is formed in a contact surface of an insulating substrate in a connecting component, the contact surface being in contact with the resin layer. The resin layer engages with the engagement structure in the contact surface in the insulating substrate in contact with the resin layer, the contact surface forming the side surface of the connecting component.

Abstract: In a quality evaluation method, an evaluation substrate that includes a mounting region, in which a multilayer capacitor is to be mounted, in a center portion of the evaluation substrate is fixed in place using a plurality of fixed portions at corner portions of the evaluation substrate, each of which is a same distance from the mounting region. A voltage is applied to the multilayer capacitor mounted on the mounting region of the evaluation substrate. Sound is collected using a microphone that is near the multilayer capacitor mounted on the evaluation substrate.

Abstract: A current bus that includes an opening that extends from one side of the current bus to an opposing side of the current bus. The opening changes in size as the opening extends from one side of the current bus to the opposing side of the current bus. The opening may include a first diameter and a second diameter that is different than the first diameter. The opening may include a first thickness at the first diameter of the opening which may be much smaller than a second thickness of the current bus. A high accuracy current measurement of the current bus may require that the magnetic field profile of the current bus within the opening be non-linear (e.g., 3rd order polynomial with the highest value of the 3rd degree coefficient).

Abstract: A dual band printed antenna pair operates simultaneously at both WLAN frequency bands (2.4 GHz/5 GHz). The antenna pair provides high isolation between both antennas while having an efficient over the air performance. The antenna pair achieve greater than 20 dB isolation at 2.4 GHz and 5 GHz band, while having antennas positioned in close proximity. The high isolation is accomplished using an orthogonal antenna configuration (exploiting orthogonal polarization) and a parasitic element to further enhance isolation at 2.4 GHz. The antenna pair and parasitic element are printed on a Printed Circuit Board (PCB) adding relatively little cost to the Radio Frequency (RF) interface. The PCB is then fixed on top of a metal chassis with the antenna keep out area overhanging a corner of the metal chassis to enhance performance.

Abstract: A wiring substrate includes an insulating layer that is an outermost layer of the wiring substrate and includes an external exposed surface, a pad forming part formed on a side of the external exposed surface, and a pad that projects from the external exposed surface. The pad forming part includes a recess part recessed from the external exposed surface, and a weir part that projects from the external exposed surface and encompasses the recess part from a plan view. The pad includes a pad body formed within the recess part and the weir part, and an eave part formed on the weir part. The pad body includes an end part that projects to the weir part. The eave part projects in a horizontal direction from the end part of the pad body. The end part of the pad body includes a flat surface.

Abstract: Disclosed is a semiconductor package structure and manufacturing method. The semiconductor package structure includes a first dielectric layer, a second dielectric layer, a component, a patterned conductive layer and at least two conductive vias. The first dielectric layer has a first surface and a second surface opposite the first surface. The second dielectric layer has a first surface and a second surface opposite the first surface. The second surface of the first dielectric layer is attached to the first surface of the second dielectric layer. A component within the second dielectric layer has at least two electrical contacts adjacent to the second surface of the first dielectric layer. The patterned conductive layer within the first dielectric layer is adjacent to the first surface of the first dielectric layer. The conductive vias penetrate the first dielectric layer and electrically connect the electrical contacts with the patterned conductive layer.

Abstract: In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.

Abstract: A fingerprint sensor package, including a sensing side for sensing fingerprint information and a separate connection side for electrically connecting the fingerprint sensor package to a host device, is disclosed. The fingerprint sensor package can also include a sensor integrated circuit facing the sensing side and substantially surrounded by a fill material. The fill material includes vias at peripheral locations around the sensor integrated circuit. The fingerprint sensor package can further include a redistribution layer on the sensing side which redistributes connections of the sensor integrated circuit to the vias. The connections can further be directed through the vias to a ball grid array on the connection side. Some aspects also include electrostatic discharge traces positioned at least partially around a perimeter of the connection side. Methods of manufacturing are also disclosed.

Abstract: A system for memory device control may include a stacked memory device and a memory controller. The stacked memory device may include a stack of chips connected to a package substrate by electrical interconnects. The stack may include a plurality of memory chips, a primary control chip, and a secondary control chip. The primary and secondary control chips may be electrically connected to the plurality of memory chips by an internal data bus. The primary control chip may have logic to provide an interface between the internal data bus and a first external data bus. The secondary control chip may have logic to provide an interface between the internal data bus and a second external data bus.

Abstract: An integrated device includes at least one heat generating component which generates heat when operated, at least one temperature-sensitive component, and one or more hollow insulation regions arranged between the at least one heat generating component and the at least one temperature-sensitive component. The hollow insulation region may be provided as a vacuum gap.

Abstract: A semiconductor construct includes a semiconductor substrate and connection pads provided on the semiconductor substrate. Some of the connection pads are connected to a common wiring and at least one of the remaining of the connection pads are connected to a wiring. The construct also includes a first columnar electrode provided to be connected to the common wiring and a second columnar electrode provided to be connected to a connection pad portion of the wiring.

Abstract: An electrical contactor assembly is provided including an electrical bus bar and at least one electrical contactor. The electrical bus bar includes a layer of insulation, a layer of copper, and a composite core having at least one wire embedded therein. The wire is configured to locally reduce thermal strain. The at least one electrical contactor is mounted to the layer of copper through an opening in the layer of insulation. The electrical contactor and the bus bar are thermally and electrically connected.

Abstract: A pad structure includes an insulating layer; a first metal layer formed on one surface of the insulating layer and including an intermetallic compound layer of copper and tin or a tin layer; and a second metal layer formed on the first metal layer and including a gold layer.

Abstract: The invention relates to a method for connecting two energy storage assemblies (10) together, each energy storage assembly including a sealed metal housing, in which: a connector strip (30), which is sized so as to contact the end surface of each of the housings, is positioned on the end surfaces (24) of two housings arranged side by side; and the strip is friction-stir welded to each of the housings.

Abstract: A socket module for an electrosurgical device has a housing (10), at least two connectors (11, 12) each having two contacts (11a, 11b, 12a, 12b). A first connection member (13) electrically connects a first contact (11a) of the first connector (11) to a first contact (12a) of the second connector (12). The first connection member (13) has two contact regions (13a, 13b), of which a first contact region (13a) is connected to the first contact (11a) of the first connector (11) and a second contact region (13b) is connected to the first contact (12a) of the second connector (12). A printed circuit board (15) is arranged in the housing (10) and electrically connected to the first connector. (11) The printed circuit board (15) supports a third contact region (15a, 15b) which connects the first connector (11) to the printed circuit board (15).

Abstract: A connector is to be fixed to a principal surface of a connection object and to be connected with a mating object. The connector comprises a plurality of contacts and a guide member. Each of the contacts has a first soldered portion, a first main portion and a first auxiliary portion. The first main portion has a contact portion. The guide member has a second soldered portion, a second main portion and second auxiliary portion. The second main portion has a guide portion which guides the mating object. When the first soldered portions and the second soldered portion are soldered to the principal surface, the contacts are arranged in a pitch direction while being separated from one another, and the guide member is separated from the contacts. The first auxiliary portion and the second auxiliary portion have cross-sections same as each other in a plane perpendicular to the pitch direction.

Abstract: A circuit may include a differential via that may include a first via having a first-via length and a second via having a second-via length longer than the first-via length. The circuit may also include a differential stripline coupled to the differential via. The differential stripline may include a first trace and a second trace that are broadside coupled to each other over at least a portion of the differential stripline to form a broadside coupled portion of the differential stripline. The first trace may be coupled to the first via and may have a first-trace length. The second trace may be coupled to the second via and may have a second-trace length. The broadside coupled portion of the differential stripline may be offset from a plane intersecting substantially half-way between the first via and the second via such that the second-trace length is shorter than the first-trace length.

Abstract: Electronic assemblies including substrates and their manufacture are described. One assembly includes a die embedded in a dielectric layer in a multilayer substrate, and a dielectric region embedded in the dielectric layer in the multilayer substrate. The multilayer substrate includes a die side and a land side, with the first dielectric region and the dielectric layer extending to the die side. A plurality of vias are positioned within the first dielectric region, the vias extending to pads on the die side. Other embodiments are described and claimed.

Abstract: A multilayer ceramic capacitor includes a ceramic body including dielectric layers and internal electrodes, electrode layers connected to the internal electrodes, and a conductive resin layer formed on the electrode layer and containing conductive particles, fullerenes, and a base resin.

Abstract: A method for mounting a second member on a first member, wherein a pad layer is provided on the first member, and wherein an annular aperture portion exposing the first member to the bottom and having at least one discontinuous portion is provided in a region of the pad layer for mounting the second member having a mount face, the annular aperture portion having the same outer shape as the mount face of the second member is disclosed. The method includes: filling the aperture portion with a solder paste layer; and disposing the mount face of the second member on the solder paste layer, and melting and cooling the solder paste layer to mount the second member on the first member.

Abstract: The invention relates to a printed circuit board arrangement, more particularly a multilayer printed circuit board. The printed circuit board arrangement comprises at least two printed circuit boards which are arranged parallel to one another and connected to one another. According to the invention, in the case of the printed circuit board arrangement of the type mentioned initially, at least one surface region of one printed circuit board is connected to another printed circuit board of the printed circuit board arrangement by means of an element embodied in an elastic and/or damping fashion in such a way that an oscillatory system, more particularly a spring-mass system, an oscillatory bending strip or a flexurally oscillatory board is formed by means of the surface region of the printed circuit board and the element.

Abstract: A circuit board laminate includes a metal substrate, an insulation layer disposed on the metal substrate, and a metal foil disposed on the insulation layer. A metal-based circuit board includes a metal substrate, an insulation layer disposed on the metal substrate, and a circuit pattern disposed on the insulation layer. The insulation layer contains a liquid crystal polyester and 50% by volume or more of an inorganic filler. The inorganic filler is made of boron nitride and at least one of aluminum nitride and aluminum oxide. A proportion of boron nitride in the inorganic filler is within a range of 35 to 80% by volume.

Abstract: A step drill test structure for a PCB and method for using the same is disclosed. In one embodiment, a test structure includes a drill path and a connection via. The drill path may include sensing pads on selected ones of a plurality of layers of the PCB (e.g., the non-surface layers). The sensing pads of a given drill path may be electrically conductive, while the remaining portion of the drill path is non-conductive. The sensing pads of each drill path may be electrically coupled to the connection via. The depth of a given layer at a particular drill path may be determined by drilling, using an electrically conductive drill bit, into the drill path and determining when an electrical connection is made between the drill bit and the connection via.

Abstract: A wiring substrate includes a core substrate. The core substrate includes an accommodation hole extending through the core substrate from. A first wiring layer is formed on a first surface of the core substrate. A second wiring layer is formed on a second surface of the core substrate located opposite to the first surface. An electronic component, which includes a connection terminal, is accommodated in the accommodation hole. A conductive film is formed on a wall surface of the accommodation hole at a location corresponding to the connection terminal of the electronic component. The conductive film is connected to at least one of the first wiring layer and the second wiring layer. A thermal conductor thermally connects the connection terminal of the electronic component and the conductive film.

Abstract: A vehicular camera includes a lens disposed at a lens holder and an imager disposed at a printed circuit board. The lens holder is one of (i) attached at the printed circuit board by a cured adhesive and (ii) attached at a holding element by a cured adhesive with the printed circuit board held by the holding element. The adhesive is initially curable in an initial radiation curing process and initially-cured adhesive is further curable to a further cured strength in a secondary thermal curing process. The adhesive is initially cured via the initial radiation curing process after the lens is brought into focus with the imager and is optically center-aligned therewith. When further cured via the secondary thermal curing process, the further-cured adhesive maintains focus and optical center-alignment of the lens with the imager for use of the camera in a vehicle.

Abstract: A printed wiring board includes a core substrate having a penetrating hole extending through the core substrate, an electronic component accommodated in the penetrating hole of the core substrate, a filler resin filling clearance between the component and the core substrate, a first resin insulation layer formed on the component and a first surface of the core substrate, and a second resin insulation layer formed on the component and a second surface of the core substrate on the opposite side of the first surface of the core substrate. The filler resin has elastic modulus which is set to be lower than 0.2 Gpa and thermal expansion coefficient which is set to be higher than 100 ppm and lower than 200 ppm, and the core substrate has elastic modulus which is set to be higher than 30 Gpa, and thermal expansion coefficient which is set to be lower than 10 ppm.

Abstract: A printed wiring board includes an interlayer resin insulation layer having a penetrating hole, a conductive circuit formed on a first surface of the interlayer resin insulation layer, a filled via conductor formed in the penetrating hole of the interlayer resin insulation layer and connected to the conductive circuit, a first surface-treatment coating structure formed on a first surface of the filled via conductor and having an electroless plating structure, and a second surface-treatment coating structure formed on a second surface of the filled via conductor on an opposite side with respect to the first surface-treatment coating structure and having an electroless plating structure. The filled via conductor includes a first conductive layer formed on side wall of the penetrating hole and a plated material filling the penetrating hole, and the first surface-treatment coating structure has a thickness which is different from a thickness of the second surface-treatment coating structure.

Abstract: Disclosed herein are an insulating film and a producing method of the insulating film which can address problems caused by dents by providing a reinforcing layer having the weight ratio of the silica of 60 to 80 wt % on one surface of the insulating film.

Abstract: A composite device for splitting photonic functionality across two or more materials comprises a platform, a chip, and a bond securing the chip to the platform. The platform comprises a base layer and a device layer. The device layer comprises silicon and has an opening exposing a portion of the base layer. The chip, a III-V material, comprises an active region (e.g., gain medium for a laser). The chip is bonded to the portion of the base layer exposed by the opening such that the active region of the chip is aligned with the device layer of the platform. A coating hermitically seals the chip in the platform.

Abstract: Embodiments of the present packages comprise a package body that is made of an insulating material, has a front surface and a back surface, and has a rectangular shape in plan view, a metal layer that is formed along a peripheral portion of the front surface of the package body and that has a frame shape in plan view, a metal frame that is joined to the metal layer with a brazing material and has a frame shape in plan view. a pair of electrode pads that are formed on the front surface of the package body surrounded by the metal layer and configured to mount a crystal oscillator, and an opening portion of a cavity opened in a position that excludes the pair of electrode pads, wherein the metal layer, the pair of electrode pads, and the opening portion of the cavity are positioned in the same plane.

Abstract: An integrated circuit (IC) package stack with a first and second substrate interconnected by solder further includes solder resist openings (SRO) of mixed lateral dimension are spatially varied across an area of the substrates. In embodiments, SRO dimension is varied between at least two different diameters as a function of an estimated gap between the substrates that is dependent on location within the substrate area. In embodiments where deflection in at least one substrate reduces conformality between the substrates, a varying solder joint height is provided from a fixed volume of solder by reducing the lateral dimensioning of the SRO in regions of larger gap relative to SRO dimensions in regions of smaller gap. In embodiments, the first substrate may be any of an IC chip, package substrate, or interposer while the second substrate may be any of another IC chip, package substrate, interposer, or printed circuit board (PCB).

Abstract: A circuit board module includes a first circuit board, an electrically conductive structure, a first bump, a second circuit board and an electrically conductive film. The electrically conductive structure and the first bump are disposed on the supporting surface of the first circuit board. The electrically conductive structure and the first bump respectively have a first maximal thickness T1 and a second maximal thickness T2 along the normal direction of the supporting surface. The second circuit board is disposed on the electrically conductive structure and the first bump. The electrically conductive film is disposed between the second circuit board and the electrically conductive structure, and it has a plurality of electrically conductive particles. An average particle diameter D of the electrically conductive particles when undeformed satisfies: 0<T2?T1?D.

Abstract: A wiring substrate includes a first multi-layer wiring layer including an insulating layer formed of a non-photosensitive resin, a plurality of external connection pads formed on an upper face side of the first multi-layer wiring layer, and a second multi-layer wiring layer formed on the first multi-layer wiring layer, the second multi-layer wiring layer including an insulating layer formed of a photosensitive resin, the second multi-layer wiring layer having a wiring pitch narrower than the wiring pitch of the first multi-layer wiring layer. The external connection pads are exposed from the insulating layer of the second multi-layer wiring layer.

Abstract: Disclosed is a clad material for an LED light-emitting element holding substrate in which a plurality of layers composed of different materials are stacked and bonded via a metal layer to a III-V group semiconductor crystal surface, the linear expansion coefficient being 14×10?6/K or less and the thermal conductivity at a temperature of 25° C. being 200 W/mK or greater. The clad material is composed of three alternately stacked layers: two copper layers and a molybdenum layer, the molybdenum layer being 10 to 60 vol % and the difference in thickness between the copper layers being 5% or less; or a clad material composed of three copper layers alternately stacked with molybdenum layers to make five layers, the molybdenum layers being 20 to 70 vol % and the difference in thickness between the top and bottom two copper layers and the molybdenum layers being 5% or less.

Abstract: A device includes: a substrate; and a functional element mounted, the functional element including electrodes. The substrate includes a support substrate, and includes a first seed metal, a second seed metal, and a resin component on the support substrate, the first seed metal being disposed in a section opposed to part or all of a first electrode among the electrodes, and being connected to the first electrode by plating, the second seed metal being disposed in a section opposed to part or all of a second electrode among the electrodes, and being connected to the second electrode by plating, and the resin component being disposed in a layer between the functional element and the support substrate, and fixing the functional element to the support substrate, and being provided avoiding a neighborhood of an end of the functional element among opposed side sections of the first and second seed metals.

Abstract: Packaging devices and methods for semiconductor devices are disclosed. In some embodiments, a packaging device for a semiconductor device includes a packaging substrate including a semiconductor device mounting region. The packaging device includes a stress isolation structure (SIS) disposed on the packaging substrate proximate a portion of a perimeter of the semiconductor device mounting region.

Abstract: Provided is a printed wiring board including a first heat dissipation pattern placed in one surface layer on which a semiconductor package is to be mounted, a second heat dissipation pattern placed in the other surface layer, and an inner layer conductor pattern placed in an inner layer, in which through holes are formed in the printed wiring board; the first heat dissipation pattern has a joint portion which is placed in an opposed region opposed to a heat sink of the semiconductor package and which is joined to the heat sink with solder; at least one of the through holes is placed in the opposed region; and the second heat dissipation pattern is formed in a pattern in which an end portion of a conductor film in the one of the through holes on the other surface layer side is separated.

Abstract: A multi-chip socket including multiple cavities. The multiple cavities include support surfaces. The support surfaces may be disposed at different heights relative to a reference plane. A first thermal interface is to thermally contact a top surface of the first component, and a second thermal interface is to thermally contact a top surface of the second component.

Abstract: The invention relates to an electronic module, a support plate (2) having a base area (20) and at least one connection element (21). Said connection element (21) is a part of the base area (20) and is arranged at an angle (a) to the base area (20), in addition to at least one electronic component (3), in particular a sensor, which is arranged in the connection element (21).

Abstract: A multilayer wiring base plate includes an insulating plate including a plurality of synthetic resin layers made of an insulating material, a wiring circuit provided in the insulating plate, a thin-film resistor formed along at least one of the synthetic resin layers to be buried in the synthetic resin layer and inserted in the wiring circuit, and a heat expansion and contraction restricting layer formed to be buried in the synthetic resin layer adjacent to the synthetic resin layer in which the thin-film resistor is formed to be buried, arranged along the thin-film resistor, and having a smaller linear expansion coefficient than a linear expansion coefficient of the adjacent synthetic resin layers.

Abstract: A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.

Abstract: A method for detecting back-drilled holes in a PCB and a PCB panel are provided. The method comprises: forming, on a metal layer of a first inner layer of a multi-layer PCB, metal rings according to positions of the back-drilled holes during a process of forming the PCB, wherein each of the formed metal rings has an outer diameter greater than an aperture of each of the back-drilled holes; forming, at positions corresponding to the positions of the back-drilled holes, metal holes extending through an outer layer of the PCB and the formed metal rings; forming two first detection holes electrically connected with the formed metal rings; forming the back-drilling holes on the PCB, which extend through and expand the metal holes; and detecting an electrical conduction between the two first detection holes so as to determine whether a position offset exists between the back-drilled holes and the metal holes.

Abstract: Disclosed herein is a heat radiating substrate including: a heat radiating plate having a step formed so that one side and the other side thereof have thicknesses different from each other; a conductor pattern layer formed over the heat radiating plate and including a mounting pad on which a control device and a power device are mounted and a circuit pattern; and an insulating layer formed between the heat radiating plate and the conductor pattern layer.

Abstract: A wiring board includes a wiring forming region in which a plurality of wiring layers are stacked while sandwiching insulating layers, an outer periphery region which is arranged around the wiring forming region and in which a reinforcing pattern is formed in the same layer as each of the wiring layers. An area ratio of the reinforcing pattern to the outer periphery region and an area ratio of the wiring layer to the wiring forming region are substantially the same in each of the layers, and the reinforcing patterns exist without a gap in the outer periphery region when the wiring board is viewed in planar perspective.