Abstract: In one or more embodiments, a circuit board may include a trace pair and a serpentine region of the trace pair, which may include: a first subregion in which the first trace includes a first portion that has a third width and a first length and in which the second trace includes a second portion, at least substantially parallel to the first portion, that has a fourth width, greater than the second width, and a second length; and a second subregion, adjacent to the first subregion, in which the first trace includes a third portion that has the third width and a third length and in which the second trace includes a third portion that has the fourth width and a third length, different from the second length.

Abstract: A wiring board is provided with power supply patterns for each type of power supply of an IC. An IC has a plurality of power supply terminals for each type of power supply. For each type of power supply, two or more laminated capacitors are provided in parallel between the power supply of IC and a ground. Two or more laminated capacitors provided for each type of power supply include a laminated capacitor having a Q factor of less than about 0.5. For each type of power supply, in order to satisfy a target impedance, two or more laminated capacitors are arranged and distributed such that at least half of the plurality of power supply terminals are included in a region obtained by combining cover areas.

Abstract: A substrate on which an electronic component is soldered, includes an electronic component, a through hole positioned on the substrate and passing through the substrate, a solder that joins the through hole and a terminal of the electronic component inserted in the through hole, a pattern formed on a first surface of the substrate, the first surface facing a second surface on which the electronic component is placed, a first resist superimposed on the pattern, an exposed portion of which the pattern is exposed from the first resist around the through hole, and a second resist superimposed on the pattern and arranged between the through hole and the exposed portion.

Abstract: An electronic device such as a media player is formed from electrical components such as integrated circuits, buttons, and a battery. Electrical input-output port contacts are used to play audio and to convey digital signals. Electrical components for the device are mounted to a substrate. The components are encapsulated in an encapsulant and covered with an optional housing structure. The electrical input-output port contacts and portions of components such as buttons remain uncovered by encapsulant during the encapsulation process. Integrated circuits are entirely encapsulated with encapsulant. The integrated circuits are packaged or unpackaged integrated circuit die. The substrate is a printed circuit board or is an integrated circuit to which components are directly connected without any printed circuit boards interposed between the integrated circuit and the components.

Abstract: Disclosed herein is a pattern safety device for preventing interference between patterns. In detail, a separately partitioned space is defined in an adhesion portion, which is formed on a plurality of patterns on the surface of a substrate so that a circuit element is placed on the adhesion portion, thus preventing interference between the patterns.

Abstract: The disclosure discloses a power module. The power module includes a substrate, a power chip, a bonding material, and at least one spacer. The substrate includes a circuit-patterned layer. The power chip bonded to the circuit-patterned layer by the bonding material. The spacer is located between the circuit-patterned layer and the power chip, so as to keep the power chip away from the circuit-patterned layer in a distance.

Abstract: A mounting method of an electronic device includes providing an electronic device which includes a semiconductor chip body including an upper surface, a lower surface opposite to the upper surface, and side surfaces connecting the upper surface and the lower surface, a plurality of bumps disposed on the lower surface, and an under-fill element disposed on at least one side surface. The method further includes mounting the electronic device on a printed circuit board including connecting pads formed thereon. The bumps of the semiconductor chip body are connected to the connecting pads. The method additionally includes heating the under-fill element to a predetermined temperature to form an under-fill layer between the lower surface of the semiconductor chip body and the printed circuit board.

Abstract: An embodiment is method including forming a first die package over a carrier substrate, the first die package comprising a first die, forming a first redistribution layer over and coupled to the first die, the first redistribution layer including one or more metal layers disposed in one or more dielectric layers, adhering a second die over the redistribution layer, laminating a first dielectric material over the second die and the first redistribution layer, forming first vias through the first dielectric material to the second die and forming second vias through the first dielectric material to the first redistribution layer, and forming a second redistribution layer over the first dielectric material and over and coupled to the first vias and the second vias.

Abstract: A display device including: a display panel; a printed circuit board (PCB) including a first substrate and a second substrate; a driving circuit disposed on the first substrate; a carrier connected between the display panel and a pad of the PCB and having a data driving integrated circuit mounted thereon; a protrusion corresponding to the pad and protruding from a side of the second substrate; and a signal line disposed in the protrusion, the first substrate, and the second substrate, the signal line for transmitting a signal from the driving circuit to the carrier.

Abstract: An electronic component embedded substrate 1 includes a substrate 10 having a wiring layer 11 and an insulating layer 12; an electronic component 20 built in the substrate 10, and having a pair of electrode layers 21A and 21B, and a dielectric layer 22; and a stress relieving layer 30 provided closer to the wiring layer 11 than the insulating layer 12 is in the lamination direction, wherein at least part of an end portion of the electronic component 20 on the wiring layer 11 side is in contact with the stress relieving layer 30, wherein at least part of an end portion of the electronic component 20 on the insulating layer 12 side is in contact with the insulating layer 12, and wherein the Young's modulus of the stress relieving layer 30 is lower than the Young's modulus of the electrode layer 21B.

Abstract: An integrated circuit includes a substrate having at least one depression on a top surface. At least one solder bump is disposed over the substrate. A die is disposed over the at least one solder bump and electrically connected with the substrate through the at least one solder bump. An underfill surrounds the at least one solder bump and is formed between the substrate and the die. The at least one depression is disposed around the underfill to keep any spillover from the underfill in the at least one depression.

Abstract: Packaging methods for semiconductor devices and methods of packaging thereof are disclosed. In some embodiments, a device includes a packaging apparatus and contact pads disposed on the packaging apparatus. The contact pads are arranged in an array of rows and columns. The contact pads include first contact pads proximate a perimeter region of the packaging apparatus and second contact pads disposed in an interior region of the packaging apparatus. A dam structure that is continuous is disposed around the second contact pads. The contact pads comprise a mounting region for a semiconductor device.

Abstract: A multilayer capacitor includes a body including dielectric layers, and first and second internal electrodes alternately disposed with respective dielectric layers interposed therebetween, first and second groove parts formed in external surfaces of the body in a first direction in which the dielectric layers are stacked, having at least one corner, and contacting the first and second internal electrodes, respectively, and first and second connection electrodes disposed in the first and second groove parts, respectively, and electrically connected to the first and second internal electrodes, respectively.

Abstract: A method for manufacturing an active optical cable comprises (a) flip-chip packaging chips onto a circuit board to form a OE circuit board, (b) integrating the OE circuit board onto an optical bench to form a OE bench, (c) integrating the OE bench onto a printed circuit board to form a OE module, (d) molding encapsulant onto the OE bench, (e) coupling a hybrid cable onto the OE module, and (f) utilizing low temperature, low pressure injection molding process to form the active optical cable.

Abstract: An interposer includes an insulating layer, conductor circuits formed in grooves formed on a first surface of the insulating layer respectively, and metal posts formed in openings extending from the grooves to a second surface of the insulating layer on the opposite side with respect to the first surface such that the metal posts are connected to the conductor circuits respectively. The insulating layer has an opening portion which accommodates an electronic component and is extending from the first surface to the second surface of the insulating layer, and each of the metal posts has an upper surface and a bottom surface on the opposite side of the upper surface such that the upper surface is connected to a respective one of the conductor circuits and that the bottom surface is exposed from the second surface of the insulating layer.

Abstract: In an embodiment, one length-direction end of each first internal electrode layer 111a of the capacitor body 110 is connected, via the conductive part 114a of the first relay layer 114 connected over a connection width equivalent to the width of each first internal electrode layer 111a, to the first external electrode 120 provided on one height-direction face of the capacitor body 110; also, the other length-direction end of each second internal electrode layer 111b is connected, via the conductive part 115a of the second relay layer 115 connected over a connection width equivalent to the width of each second internal electrode layer 111b, to the second external electrode 130 provided on one height-direction face of the capacitor body 110.

Abstract: The present disclosure relates to a fan-out semiconductor package and a method of manufacturing the same. The fan-out semiconductor package includes: a first connection member having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant encapsulating at least portions of the first connection member and the semiconductor chip; and a second connection member disposed on the first connection member and the semiconductor chip. The first connection member includes a first insulating layer, a first redistribution layer and a second redistribution layer disposed on one surface and the other surface of the first insulating layer opposing the one surface thereof, respectively, a second insulating layer disposed on the first insulating layer and covering the first redistribution layer, and a third redistribution layer disposed on the second insulating layer. A fan-out semiconductor package may include one or more connection units instead of the first connection member.

Abstract: A wiring board includes: a first wiring structure including: a first insulating layer; a first wiring layer; and a via wiring; a protective insulating layer formed on the lower surface of the first insulating layer to cover a side surface of a lower portion of the first wiring layer; and a second wiring structure having an insulating layer and a wiring layer and formed on the upper surface of the first insulating layer. The upper surface of the first insulating layer and the upper end surface of the via wiring are substantially flush with each other. A wiring density of the second wiring structure is higher than a wiring density of the first wiring structure. The reinforcing material is positioned on a side of the second wiring structure with respect to a center of the first insulating layer in the thickness direction of the first insulating layer.

Abstract: A method for manufacturing an electronic assembly and electronic assemblies are presented. The method includes obtaining a substrate film for accommodating electronics, providing at least an electrical contact pad to the substrate film, coupling an electrically conductive member to the electrical contact pad, and molding, such as injection molding, a material layer onto the substrate film to embed the elastic electrically conductive member utilizing a mold structure defining a cavity for molding. The elastic electrically conductive member is arranged to extend during the molding from the electrical contact pad through the cavity to be in contact with an element on a different side of the cavity with respect to the electrical contact pad for maintaining at least a part of the elastic electrically conductive member accessible after the molding to provide an electrical connection through the material layer to the electrical contact pad.

Abstract: A printed wiring board includes a support plate, and a build-up wiring layer including resin insulating layers and conductor layers and having a first surface and a second surface on the opposite side with respect to the first surface such that the support plate is positioned on the first surface of the build-up wiring layer. The resin insulating layers in the build-up wiring layer include a first resin insulating layer that forms the second surface of the build-up wiring layer, and the build-up wiring layer includes first conductor pads embedded in the first resin insulating layer such that each of the first conductor pads has an exposed surface exposed from the second surface of the build-up wiring layer.

Abstract: A wiring board includes a ceramic insulating base; a recessed portion provided on a side surface of the insulating base, the recessed portion being connected to one main surface of the insulating base; an internal wiring conductor disposed in an interior of the insulating base; an external wiring conductor disposed on one main surface of the insulating base; a recessed portion wiring conductor disposed in the recessed portion, the recessed portion wiring conductor being connected to the internal wiring conductor and the external wiring conductor; and a through conductor disposed in an interior of the insulating base, the through conductor electrically connecting the internal wiring conductor and the external wiring conductor. In a see-through plan view of the insulating base from a one main surface side, the recessed portion extends in one direction, and the through conductor is disposed in a periphery of an end portion of the recessed portion.

Abstract: A wide I/O semiconductor device is disclosed including a memory die stack wire bonded to an interface chip. The stack of memory die may be wire bonded to the interface chip using a wire bond scheme optimized for die-to-die connection and optimized for the large number of wire bond connections in a wide I/O semiconductor device. This method can achieve significant BW increase by improving packaging yield and costs, not possible with current packaging schemes.

Abstract: An integrated circuit with a micro inductor or with a micro transformer with a magnetic core. A process of forming an integrated circuit with a micro inductor with a magnetic core. A process of forming an integrated circuit with a micro transformer with a magnetic core.

Abstract: An electronic component mount structure includes an electronic component and a mount substrate. The electronic component includes a multilayer body including dielectric layers, internal electrode layers and an insulating layer stacked in a stacking direction. The multilayer body includes two main surfaces opposed to each other in the stacking direction, two side surfaces opposed to each other in a width direction perpendicular to the stacking direction, and two end surfaces opposed to each other in a length direction perpendicular to the stacking and width directions. An insulator is provided on the side surfaces of the multilayer body. The mount substrate includes a land electrode on a mount surface. The electronic component is mounted on the land electrode with a solder fillet being interposed such that the side surfaces are perpendicular to the mount surface. The land electrode is smaller in the width direction than the electronic component.

Abstract: Techniques are disclosed for providing on-chip capacitance using through-body-vias (TBVs). In accordance with some embodiments, a TBV may be formed within a semiconductor layer, and a dielectric layer may be formed between the TBV and the surrounding semiconductor layer. The TBV may serve as one electrode (e.g., anode) of a TBV capacitor, and the dielectric layer may serve as the dielectric body of that TBV capacitor. In some embodiments, the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor. To that end, in some embodiments, the entire semiconductor layer may comprise a low-resistivity material, whereas in some other embodiments, low-resistivity region(s) may be provided just along the sidewalls local to the TBV, for example, by selective doping in those location(s). In other embodiments, a conductive layer formed between the dielectric layer and the semiconductor layer serves as the other electrode (e.g., cathode) of the TBV capacitor.

Abstract: A method of manufacturing an array substrate and a display device includes forming a water-soluble organic layer on a surface of a passivation layer, forming a photoresist layer on a surface of the water-soluble organic layer to perform a yellow light process to form a photoresist layer pattern, a cross-section of a water-soluble organic area is less than a cross-section of a bottom surface of a photoresist area, and dry etching the passivation layer such that a cross-section of the passivation layer pattern is the same as a cross-section of the water-soluble organic layer pattern.

Abstract: An electronic device module includes a board including external connecting electrodes and mounting electrodes; an electronic device mounted on the mounting electrodes; a molded portion sealing the electronic device; connection conductors having an end bonded to the external connecting electrodes and penetrating through the molded portion; and external terminals bonded to another end of the connection conductors.

Abstract: A semiconductor device includes a base member, a wiring portion, a semiconductor element, and a resin package. The base member has an obverse surface, a reverse surface, and a side surface connecting the obverse surface and the reverse surface. The semiconductor element is electrically connected to the wiring portion and arranged on the obverse surface of the base member. The resin package covers the semiconductor element. The wiring portion includes an obverse-surface portion formed on the obverse surface, a reverse-surface portion formed on the reverse surface, and a through portion connecting the obverse-surface portion and the reverse-surface portion. The through portion has an exposed surface exposed from the side surface of the base member and a larger portion. The larger portion has a dimension larger than the exposed surface in a first direction that is perpendicular to the thickness direction and parallel to the exposed surface.

Abstract: According to various embodiments, an electronic device includes a first electronic component, a second electronic component electrically connected to the first electronic component, and a conductive electric connection device disposed to electrically connect the second component and the first electronic component to each other. The electric connection device may include a first member fixed to the first electronic component, a second member formed to extend upward from the first member, and a third member formed to extend from the second member to be substantially parallel to a direction of overlapping with the first member. The second electronic component may be interposed in a space between the first member and the second member to be electrically connected to at least two areas of the second electronic component. Various other embodiments may be made.

Abstract: An interconnect substrate includes vertical connection channels around a cavity. The vertical connection channels are made of a combination of metal posts and metallized vias. The cavity includes a recess in a core layer and an aperture in a stiffener. The metal posts, disposed over the top surface of the core layer, are sealed in the stiffener and are electrically connected to a buildup circuitry adjacent to the bottom surface of the core layer. The minimal height of the metal posts needed for the vertical connection can be reduced by the amount equal to the depth of the recess. The buildup circuitry is electrically connected to the metal posts through the metallized vias.

Abstract: An electric pump having a circuit board comprises a motor housing having a rotor and a stator disposed therein, the rotor arranged on a rotation shaft and the stator disposed outside the rotor with a predetermined space therefrom; a first partition wall disposed on a first side of the motor housing and a second partition wall disposed on a second side of the motor housing, the first and second partition walls being fastened to the motor housing; an impeller disposed outside the first partition wall and fastened to an end portion of the rotation shaft; a ceramic board disposed outside the second partition wall and having a first side with a circuit formed thereon, the circuit being electrically connected to the rotor or the stator, the first side further comprising at least one electric device, and a second side facing the second partition wall with recesses arranged in the second side at predetermined distances; and an adhesive member interposed between the ceramic board and the second partition wall.

Abstract: A multilayer capacitor includes a capacitor body including a plurality of first and second internal electrodes alternately disposed therein and a dielectric layer interposed therebetween, and having first to sixth surfaces, opposing each other, respectively; a plurality of external electrodes connected to the first and second internal electrodes; an insulating layer disposed on the first surface; first and second terminal electrodes spaced apart from each other in a direction in which the third and fourth surfaces are connected, on the insulating layer; and a connecting member electrically connecting the first and second terminal electrodes and the external electrodes.

Abstract: The embodiments of present invention disclose a circuit board and a manufacturing method thereof and a display apparatus comprising the circuit board. The circuit board comprises a base substrate, a device to be soldered, a bonding pad and a support, wherein the bonding pad and the support are provided on the base substrate, and the device to be soldered is provided on the support and is connected with the bonding pad. By providing the device to be soldered on the support, the embodiments of present invention can effectively prevent the short circuit of the device to be soldered during the process of soldering and thus improve product yield.

Abstract: Apparatuses and methods including conductive vias of a printed circuit board are described. An example apparatus includes a first layer including a first conductive plate; a component on the first layer, a second layer including a second conductive plate that may be coupled to an external power source; a third layer between the first layer and the second layer, the third layer including a third conductive plate; a first via coupling the first conductive plate to the second conductive plate; and a second via coupled to the first conductive plate. The first conductive plate includes a first portion coupled to the first via and the first conductive plate further includes a second portion coupled to the second via between the first portion and the component. The second via is coupled to either the second conductive plate or the third conductive plate.

Abstract: There is provided a multilayer ceramic capacitor including a ceramic body including a plurality of dielectric layers and having first and second main surfaces opposing each other, first and second side surfaces opposing each other, and first and second end surfaces opposing each other, a plurality of internal electrodes having the dielectric layer interposed therebetween, electrode layers formed on the first and second end surfaces of the ceramic body and electrically connected to the plurality of internal electrodes, and an impact absorption layer formed on the electrode layer so that an edge thereof is exposed.

Abstract: An array of non-thermal plasma emitters is controlled to emit plasma based on application of an electric current at desired frequencies and a controlled power level. A power supply for an array controller includes a transformer that operates at the resonant frequency of the combined capacitance of the array and the cable connecting the array to the power supply. The power into the array is monitored by the controller and can be adjusted by the user. The controller monitors the phase relationship between the transformer primary winding voltage and the gate drive voltage, and adjusts the drive frequency to resonance. Alternatively the balanced driver is configured as an oscillator which drives the transformer at resonance by default. A signal from the transformer driver generates an interrupt to the controller for synchronizing current and voltage measurements for power control.

Abstract: Supercapacitor structures are provided which include, for example: one or more layers of supercapacitors; and one or more contact tabs. The one or more contact tabs electrically contact and extend outward from the supercapacitor structure to facilitate electrical connection to the supercapacitor structure, and the one or more contact tabs include a multi-contact tab. The multi-contact tab is configured and sized with multiple contact locations which are disposed external to the supercapacitor structure. Various supercapacitor structures are provided, including one supercapacitor structure with a shared C-shaped current collector, and another supercapacitor structure with stacked supercapacitors. One or more additional multi-contact tabs may also extend from the supercapacitor structure(s) and distribute the same or a different capacitor voltage than the multi-contact tab.

Abstract: A structure of a patterned material layer including separate patterns arranged in rows and columns is described. The separate patterns in at least one row including the outmost row each have a larger dimension in the column direction than the separate patterns in the other rows. The separate patterns in at least one column including the outmost column each have a larger dimension in the row direction than the separate patterns in the other columns.

Abstract: An integrated circuit is provided. The integrated circuit includes a package base including package leads, an extracted die removed from a previous packaged integrated circuit, and an an interposer bonded to the extracted die and the package base. The extracted die includes original bond pads and one or more original ball bonds on the original bond pads. The interposer includes first bond pads electrically connected to the original bond pads with 3D printed first bond connections conforming to the shapes and surfaces of the extracted die and the interposer and second bond pads electrically connected to the package leads with 3D printed second bond connections conforming to shapes and surfaces of the interposer and package base.

Abstract: Described herein are display devices having architectures with a reduced number of external connections from the display to the external electronics, which allows for an increase in the pitch of the external connections, thereby improving reliability and flexibility, and reducing costs. The architecture of these devices is based on using multiplexers to connect external source lines to the individual display column lines. Accordingly, data signals can come into the display on a reduced number of external source lines as compared to the number of display column lines. The architecture allows for high-reliability, rugged contacts to a small-sized display by avoiding the need for high resolution interconnects.

Abstract: An RF semiconductor amplifier package includes a flange shaped body section, an electrically conductive die pad centrally located on the body section, and an electrically insulating window frame disposed on an upper surface of the body section. A first electrically conductive lead is disposed on the window frame adjacent to a first side of the die pad and extends away from the first side of the die pad towards a first edge side of the body section. A second electrically conductive lead is disposed on the window frame adjacent to a second side of the die pad and extends away from the second side of the die pad towards a second edge side of the body section. A first electrically conductive biasing strip is disposed on the window frame, continuously connected to the second lead, and extends along and a third side of the die pad.

Abstract: A resistor includes a resistive element, a first resin substrate on an upper surface of the resistive element and having a high thermal conductivity, a first heat radiator plate made of metal provided on an upper surface of the first resin substrate, a second heat radiator plate made of metal provided on the upper surface of the first resin substrate, a first edge-surface electrode provided on the first edge surface of the resistive element and connected to the first heat radiator plate, and a second edge-surface electrode provided on the second edge surface of the resistive element and connected to the second heat radiator plate.

Abstract: A semiconductor package includes: a first substrate, disposed so as to be opposed to a second substrate, on which a semiconductor chip is mounted; and a solder ball formed on the first substrate, wherein the solder ball is joined to a pin that penetrates through the second substrate.

Abstract: A sensing device for power transmission line includes an induction coil device, a sensing circuit device, and a housing. A plurality of iron cores and a plurality of windings defined in the induction coil device. The windings are wound around the iron cores. A hole for power transmission line is defined in the induction coil device. The sensing circuit device detects operation status of a power transmission line and environmental parameters. The sensing circuit device includes a cover and a bottom plate. Multiple circuit boards are mounted on the bottom plate. The induction coil device is mounted on one side of the cover. Each of two ends of the housing has a streamline shape. The housing is hollow for receiving the sensing circuit device. The iron cores of the induction coil device includes at least one first iron core and at least one second iron core.

Abstract: A printed wiring board includes a lowermost resin insulating layer, a first conductor layer formed on first surface of the lowermost layer, a conductor post having upper surface facing the first surface of the lowermost layer, a metal post formed such that the metal post is protruding from second surface of the lowermost layer and is positioned at lower surface of the conductor post, an electronic component embedded in the lowermost layer such that the component is positioned on second surface side of the lowermost layer and has an electrode facing the first surface of the lowermost layer, and via conductors formed in the lowermost layer and including first and second via conductors such that the first via conductor is connecting the first conductor layer and the upper surface of the conductor post and the second via conductor is connecting the first conductor layer and the electrode of the component.

Abstract: An electronic device includes a first circuit board and a second circuit board arranged to have their first main surfaces facing each other, and a casing containing the first and second circuit boards. The first circuit board has the first main surface having a first electronic component with a mounting height from the first main surface toward the second circuit board greater than a distance between the first and second circuit boards. The second circuit board has an opening or a cutout as a first hollow portion facing the first electronic component. The first hollow portion receives a part of the first electronic component.

Abstract: MEMS devices having discharge circuits. In some embodiments, a MEMS device can include a substrate and an electromechanical assembly implemented on the substrate. The MEMS device can further include a discharge circuit implemented relative to the electromechanical assembly. The discharge circuit can be configured to provide a preferred arcing path during a discharge condition affecting the electromechanical assembly. The MEMS device can be, for example, a switching device, a capacitance device, a gyroscope sensor device, an accelerometer device, a surface acoustic wave (SAW) device, or a bulk acoustic wave (BAW) device. The discharge circuit can include a spark gap assembly having one or more spark gap elements configured to facilitate the preferred arcing path.

Abstract: In an embodiment, a multilayer ceramic capacitor 10 is formed in such a way that a first face f1 of a capacitor body 11 has a concave shape and a first part 12a of a first external electrode 12 contacts the concave-shaped first face f1, and that a second face f2 of the capacitor body 11 has a concave shape and a first part 13a of a second external electrode 13 contacts the concave-shaped second face f2.

Abstract: A semiconductor device includes a substrate, and interposer layers. The substrate has a first region, and a second region adjacent the first region. The interposer layers are sequentially stacked on the substrate. Each of the interposer layers has an active region and an open region, which respectively correspond to the first region and the second region of the substrate. Each of the interposer layers includes a device layout pattern, and a stress release structure. The device layout pattern is formed within the active region. The stress release structure is formed within the open region, and includes openings.

Abstract: An imaging module of the invention includes: a solid-state image sensing device including an imaging-device terminal; a connector having a first end face, a second end face located opposite to the first end face, and a side face orthogonal to the first end face, the connector including: a main body serving as an insulating member, an implanted conductor that is implanted in an inside of the main body, a first mounting terminal that is electrically connected to the imaging-device terminal and the implanted conductor and is provided on the first end face, a second mounting terminal that is provided on the side face and constitutes part of the implanted conductor, and a third mounting terminal that is provided on the second end face and constitutes part of the implanted conductor; and a signal cable electrically connected to the second mounting terminal.