With Solder Patents (Class 174/263)
  • Patent number: 10693270
    Abstract: A press-fit pin for a semiconductor package includes a shaft terminating in a head. A pair of arms extends away from a center of the head. Each arm includes a curved shape and the arms together form an s-shape. A length of the s-shape is longer than the shaft diameter. An outer extremity of each arm includes a contact surface configured to electrically couple to and form a friction fit with a pin receiver. In implementations the press-fit pin has only two surfaces configured to contact an inner sidewall of the pin receiver and is configured to contact the inner sidewall at only two locations. The shaft may be a cylinder. The s-shape formed by the pair of arms is visible from a view facing a top of the press-fit pin along a direction parallel with the longest length of the shaft. Versions include a through-hole extending through the head.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: June 23, 2020
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Chee Hiong Chew, Atapol Prajuckamol, Yusheng Lin
  • Patent number: 10681809
    Abstract: Disclosed is a composite printed circuit board including a first printed circuit board (PCB) having a first circuit pattern mounted thereon, and a second PCB having a second circuit pattern mounted thereon, and the first PCB penetrates and is coupled to the second PCB so that the first circuit pattern is electrically connected to the second circuit pattern.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: June 9, 2020
    Assignee: LG ELECTRONICS INC.
    Inventor: Sunil Lee
  • Patent number: 10667398
    Abstract: The present invention relates to a single board computer system with an improved memory and layout. The unique layout of the printed circuit board of the present invention allows for different parts to be placed in a back-to-back configuration to minimize the dimensions of the printed circuit board. This includes a high-performance radiation-hardened reconfigurable FPGA, for processing computation-intensive space systems, disposed on both sides of the printed circuit board. Four dual double data rate synchronous dynamic random-access memories (DDR2 SDRAMs) disposed on both the top side and on the bottom side of the printed circuit board reduce an operating voltage of said printed circuit board. A layout stack-up of the printed circuit board includes twenty-two symmetrical layers including ten ground layers, four power layers, six signal layers, a top layer, and a bottom layer.
    Type: Grant
    Filed: September 26, 2018
    Date of Patent: May 26, 2020
    Assignee: United States of America as represented by the Administrator of NASA
    Inventors: David J. Petrick, Alessandro D. Geist, Thomas P. Flatley
  • Patent number: 10658282
    Abstract: A package substrate structure includes a first substrate, a second substrate, a plurality of conductive pillars and an adhesive layer. The first substrate includes a plurality of vias and a plurality of pads. The vias and the pads are disposed on the first substrate, and fills the vias. The second substrate is disposed opposite to the first substrate. Each conductive pillar is disposed between the first substrate and the second substrate, where each conductive pillar electrically connects each pad and the second substrate, and the adhesive layer fills the gaps between the conductive pillars. A bonding method of the package substrate structure is also provided.
    Type: Grant
    Filed: October 23, 2018
    Date of Patent: May 19, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Cheng-Ta Ko, Kai-Ming Yang, Yu-Hua Chen, Tzyy-Jang Tseng
  • Patent number: 10555451
    Abstract: A method for mounting SMD components on contact springs in electric motors. In a first method variation, the SMD component is mounted on the base of a carrier of the electric motor, which has already been provided with a contact spring protruding into a cavity. As the SMD component is installed, the contact spring is pressed back such that no frictional or sliding contact arises during installation. In a second variation, the SMD component is mounted first and then a contact spring is inserted using a press tool. As the contact spring is inserted, the spring is held back such that likewise no frictional or sliding contact arises with the SMD component that has already been installed. This avoids damage to the SMD component caused by the contact spring during installation.
    Type: Grant
    Filed: September 7, 2015
    Date of Patent: February 4, 2020
    Assignee: Continental Automotive GmbH
    Inventors: Werner Wallrafen, Daniel Muresan
  • Patent number: 10553519
    Abstract: A heat radiating member includes: a composite portion composed of a composite material which contains particles of a satisfactorily thermally conductive material in a metal matrix; and a metal layer formed on at least one surface of the composite portion and composed of a metal. A method for producing a heat radiating member includes: a preparation step to prepare a composite material which contains particles of a satisfactorily thermally conductive material in a metal matrix; a powder arrangement step to dispose a metal powder composed of metal particles on at least one surface of the composite material; and a heating step to heat the composite material and the metal powder, with the metal powder disposed on the composite material, to form a metal layer composed of a metal of the metal powder on a composite portion composed of the composite material.
    Type: Grant
    Filed: September 1, 2015
    Date of Patent: February 4, 2020
    Assignees: A.L.M.T. Corp, Sumitomo Electric Industries, Ltd.
    Inventors: Tatsuya Morikawa, Takanori Kadokura, Isao Iwayama
  • Patent number: 10528694
    Abstract: An electronic breadboard system may include a computing device including a display screen. The display screen has a first portion to display an electronic circuit model and a second portion directly adjacent to the first portion. The electronic breadboard system also includes a translucent breadboard on the second portion of the display screen. The translucent breadboard includes a translucent face plate having a rectangular grid of openings exposing a plurality of contacts. The plurality of contacts are arranged lengthwise along each row of the rectangular grid of openings and orthogonal to a transparent back plate coupling the plurality of contacts to the translucent face plate. The electronic breadboard system includes a graphics controller. The graphics controller may illuminate a row opening and/or a column opening of the translucent breadboard to direct placement of electrical components of a computer model in response to user interaction with the electronic circuit model.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: January 7, 2020
    Assignee: JOEBOTICS INCORPORATED
    Inventors: Joseph Julius Maisel, Leslie Orton, Christopher Draden Henderson
  • Patent number: 10453705
    Abstract: Apparatuses and methods including an apparatus for an electronics package are disclosed. According to one embodiment, the apparatus can include one or more magnetic inductors, one or more capacitors positioned one of above or below to the one or more magnetic inductors and a plurality of electrical conductors comprising pillars. The pillars can extend substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors to the electronics package and the one or more magnetic inductors, the one or more capacitors and the plurality of conductors are disposed one of above or below the electronics package; and at least one electrical conductor comprising a pillar extending substantially vertically to electrically connect the one or more magnetic inductors and the one or more capacitors.
    Type: Grant
    Filed: January 9, 2018
    Date of Patent: October 22, 2019
    Assignee: Intel Corporation
    Inventors: Amit K. Jain, Sameer Shekhar, Kaladhar Radhakrishnan
  • Patent number: 10453799
    Abstract: Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate including a plurality of build-up layers, such as bumpless build-up layer (BBUL). In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: October 22, 2019
    Assignee: INTEL CORPORATION
    Inventors: Deepak V. Kulkarni, Russell K. Mortensen, John S. Guzek
  • Patent number: 10446500
    Abstract: Semiconductor packages with embedded bridge interconnects, and related assemblies and methods, are disclosed herein. In some embodiments, a semiconductor package may have a first side and a second side, and may include a bridge interconnect, embedded in a build-up material, having a first side with a plurality of conductive pads. The semiconductor package may also include a via having a first end that is narrower than a second end. The bridge interconnect and via may be arranged so that the first side of the semiconductor package is closer to the first side of the bridge interconnect than to the second side of the bridge interconnect, and so that the first side of the semiconductor package is closer to the first end of the via than to the second end of the via. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: October 15, 2019
    Assignee: Intel Corporation
    Inventor: Kyu-Oh Lee
  • Patent number: 10410757
    Abstract: An electric conduction component fixation structure includes: a fixed member which has electrically conductive properties and on which an electric conduction component is arranged; and a press member that presses and fixes the electric conduction component, which is arranged on the fixed member, to the fixed member, wherein the fixed member includes a pressed surface that is pressed when the electric conduction component is fixed by the press member, and the pressed surface is covered by a rustproof coating film having a plurality of metal flakes which are layered and a binder which joins the plurality of metal flakes.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: September 10, 2019
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Munehiro Matsubara, Yuki Endo, Tadanobu Aoki, Toru Nakamura
  • Patent number: 10375817
    Abstract: An electronic device has a control board having a plurality of wiring layers, a metal-made housing supporting the control board, and a fixing screw for fixing the control board to the housing through a washer. The control board includes a through hole penetrating from a third surface to a fourth surface, a through electrode formed inside the through hole, and a power system GND pattern formed on any wiring layer of the wiring layers. The power system GND pattern and the housing are electrically coupled through the through electrode, the washer, and the fixing screw.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: August 6, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Norikazu Motohashi, Tomohiro Nishiyama, Tadashi Shimizu, Shinji Nishizono
  • Patent number: 10297540
    Abstract: A wiring substrate includes a first wiring layer, an insulation layer arranged on the first wiring layer and formed of a photosensitive resin, a via hole formed in the insulation layer and reaching the first wiring layer, and a second wiring layer formed in the via hole and on the insulation layer and connected to the first wiring layer. A surface of the first wiring layer in the via hole is formed as a roughened surface.
    Type: Grant
    Filed: May 14, 2018
    Date of Patent: May 21, 2019
    Assignee: SHINKO ELECTRIC INDUSTRIES, CO., LTD.
    Inventor: Yoichi Nishihara
  • Patent number: 10257931
    Abstract: Systems and methods for grooved vias are described. For example, a method may include: drilling a via hole in a Printed Circuit Board (PCB), where the PCB comprises a first layer having a first trace and a second layer having a second trace, the via hole includes a first portion between the first layer and the second layer and a second portion between the second layer and a bottom surface of the PCB, and the via hole is configured to couple the first trace to the second trace through the first portion; after drilling the via hole, creating a rough internal surface in at least the second portion of the via hole that is configured to reduce a resonance of a signal transmitted from the first trace to the second trace; and forming a via by filling the first and second portions of the via hole with conductive material.
    Type: Grant
    Filed: February 9, 2016
    Date of Patent: April 9, 2019
    Assignee: Dell Products, L.P.
    Inventors: Stuart Allen Berke, Bhyrav M. Mutnury, Sandor Farkas
  • Patent number: 10170876
    Abstract: Plugs, receptacles, and assemblies including same. The plug can include an interface having a plurality of pins extending therefrom. The plug can have a plug density of at least 280 pins/in2. The plurality of pins can be positioned in at least three rows along a longitudinal axis of the interface. The receptacle can have an interface having a plurality of sockets disposed therein. The receptacle can have a receptacle density of at least 280 sockets/in2. The plurality of sockets can be positioned in at least three rows along a longitudinal axis of the interface.
    Type: Grant
    Filed: October 5, 2016
    Date of Patent: January 1, 2019
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Erik Quam, Shelby W. Carter
  • Patent number: 10157821
    Abstract: A semiconductor package includes: a substrate including a conductive pad; a semiconductor device including a conductive member; and a connection element between the conductive pad and the conductive member, wherein the connection element has a sidewall, and an angle of the sidewall relative to the conductive pad is equal to or less than about 90 degrees.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: December 18, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Chao Cheng Liu
  • Patent number: 10122139
    Abstract: An adapter apparatus and methods for using in providing such adapter apparatus include providing a substrate having a plurality of openings defined therethrough. A plurality of conductive elements are mounted within corresponding openings thereof using a flowable and curable laminate material.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 6, 2018
    Assignee: IRONWOOD ELECTRONICS, INC.
    Inventors: David Allen Struyk, Kenneth Irving Krawza, Ilavarasan M. Palaniappa, Sultan Mahmood Faiz
  • Patent number: 10096915
    Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.
    Type: Grant
    Filed: February 2, 2017
    Date of Patent: October 9, 2018
    Assignee: MERCURY SYSTEMS, INC.
    Inventors: Darryl J. McKenney, Absu Methratta, Erica Ouellette
  • Patent number: 10091894
    Abstract: An electronic control module for a gear mechanism controller in motor vehicles includes a printed circuit board and an electrical component. The printed circuit board has a mounting side and includes conductor tracks. The electrical component has an electrically conductive connection section. The control module further includes a press contact that is pressed into an opening in the printed circuit board such that it is mechanically fixed to the printed circuit board. The press contact forms an electrical contact with a conductor track of the printed circuit board via an electrically conductive mating connection section of the press contact. The connection section of the electrical component is connected to the mating connection section of the press contact by a welded connection. The connection technique enables soldered connections to be dispensed with and replaced by cold pressing of press contacts and subsequent welding by, for example, a copper/copper laser welding process.
    Type: Grant
    Filed: March 18, 2015
    Date of Patent: October 2, 2018
    Assignee: Robert Bosch GmbH
    Inventor: Uwe Liskow
  • Patent number: 10084503
    Abstract: Surface-mount technology (SMT) devices and related methods. In some embodiments, an SMT device can include an electrical element and a plurality of terminals connected to the electrical element. The SMT device can further include a body configured to support the electrical element and the plurality of terminals. The body can have a rectangular cuboid shape with a length, a width, and a height that is greater than the width. The body can include a base plane configured to allow surface mounting of the SMT device. In some embodiments, the SMT device can be, for example, a capacitor, an inductor, or a resistor.
    Type: Grant
    Filed: October 14, 2015
    Date of Patent: September 25, 2018
    Assignee: Skyworks Solutions, Inc.
    Inventor: Andrew Martin Kay
  • Patent number: 10068844
    Abstract: A semiconductor device includes a molding compound and a through via extending through the molding compound. A via connection is disposed over the through via and a cap is disposed over the via connection. A plurality of holes are formed in a section of the cap.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: September 4, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Yen Chiu, Hsien-Wei Chen
  • Patent number: 10037956
    Abstract: The invention relates to a ball-limiting metallurgy stack for an electrical device that contains at least one copper layer disposed upon a Ti adhesion metal layer. The ball-limiting metallurgy stack resists Sn migration toward the upper metallization of the device.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: July 31, 2018
    Assignee: Intel Corporation
    Inventors: Madhav Datta, Dave Emory, Subhash M. Joshi, Susanne Menezes, Doowon Suh
  • Patent number: 9978710
    Abstract: A method for producing a stack of semiconductor devices and the stacked device obtained thereof are disclosed. In one aspect, the method includes providing a first semiconductor device comprising a dielectric layer with a hole, the hole lined with a metal layer and partially filled with solder material. The method also includes providing a second semiconductor device with a compliant layer having a metal protrusion through the compliant layer, the protrusion capped with a capping layer. The method further includes mounting the devices by landing the metal protrusion in the hole, where the compliant layer is spaced from the dielectric layer. The method includes thereafter reflowing the solder material, thereby bonding the devices such that the compliant layer is contacting the dielectric layer.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: May 22, 2018
    Assignees: IMEC vzw, Katholieke Universiteit Leuven
    Inventors: Vikas Dubey, Eric Beyne, Jaber Derakhshandeh
  • Patent number: 9935072
    Abstract: The present disclosure provides a semiconductor package that prevents a bump bridge from being formed between adjacent conductive bumps to realize a fine bump pitch when each unit circuit part is directly stacked without using a printed circuit board and a method for manufacturing the same. The semiconductor package includes a first semiconductor chip structure including a first unit circuit part, a first passivation layer disposed on the first unit circuit part, and a conductive bump electrically connected to the first unit circuit part, and a second semiconductor chip structure including a second unit circuit part, a second passivation layer having a stepped portion that is recessed inward and disposed on the second unit circuit part, and a bump pad provided in the stepped portion. The first semiconductor chip structure and the second semiconductor chip structure are stacked to allow the conductive bump to be bonded to the bump pad within the stepped portion.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: April 3, 2018
    Assignee: SFA SEMICON CO., LTD.
    Inventors: Byeong Ho Jeong, Eun Dong Kim, Jong Won Lee, Hyun Hak Jung, Jai Kyoung Choi
  • Patent number: 9877394
    Abstract: A mechanical and electrical connection system including a printed circuit board, a busbar and an electrical component, wherein the board includes a first orifice in which a bottom foot of the bar is received and includes a second orifice in which a lug of the component is received, and wherein the bar includes an elastically deformable clamp which receives the lug of the component.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: January 23, 2018
    Assignee: SCHNEIDER ELECTRIC INDUSTRIES SAS
    Inventor: Franck Bordonado
  • Patent number: 9870895
    Abstract: Perforating graphene and other two-dimensional materials with holes inclusively having a desired size range, a narrow size distribution, and a high hole density can be difficult to achieve. A layer in continuous contact with graphene, graphene-based materials and other two-dimensional materials can help promote hole formation. Processes for perforating a two-dimensional material can include exposing to an ion source a two-dimensional material in continuous contact with at least one layer, and interacting a plurality of ions from the ion source with the two-dimensional material and with the at least one layer. The ion source may be a broad ion beam.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: January 16, 2018
    Assignee: Lockheed Martin Corporation
    Inventor: Peter V. Bedworth
  • Patent number: 9848489
    Abstract: A multilayer resin substrate includes resin substrates laminated together, an overlapping portion in which a signal line as a conductor pattern and another conductor pattern overlap each other in a laminating direction of the resin substrates, and a non-overlapping portion in which the signal line and the other conductor pattern do no overlap each other in the laminating direction. A thin portion is provided at a position in the non-overlapping portion near the overlapping portion. The thin portion is a portion of the multilayer resin substrate which has a thickness smaller than the thickness in the overlapping portion in the laminating direction of the resin substrates.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: December 19, 2017
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hirofumi Shinagawa, Shigeru Tago
  • Patent number: 9699919
    Abstract: An electronic component unit and a wire harness are provided with a bus bar plate. The bus bar plate is provided with a metallic bus bar that is built in a resin material, and including a through-hole in which a terminal of a relay mounted on a mounting surface is soldered. The through-hole is provided with a bus bar through-hole which penetrates the bus bar, and a resin material through-hole which penetrates the resin material and is formed to be larger than the bus bar through-hole to expose the surface of the bus bar. When an inner diameter of the bus bar through-hole is defined as r and an inner diameter of the resin material through-hole is defined as R, 1.5r?R is satisfied.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: July 4, 2017
    Assignee: YAZAKI CORPORATION
    Inventors: Akemi Maebashi, Pharima Akanitsuk
  • Patent number: 9669493
    Abstract: When soldering a package having an electrode on which Ni/Au or Ag—Pd alloy is plated, to a printed circuit board having a Cu electrode or an electrode on which Cu is plated, a solid-phase diffusion layer is formed within a layered solder material for bonding different species of electrodes. The layered solder material is composed of a solder material of Sn—Ag—Cu series or Sn—Sb series and a solder material of Sn—Ag—Cu—Ni series or Sn—Pb series. The electrode on which Ni/Au or Ag—Pd alloy is plated and the Cu electrode or the electrode on which Cu is plated are soldered with the solder material of Sn—Ag—Cu series or Sn—Sb series being attached to the Cu electrode and the solder material of Sn—Ag—Cu—Ni series or Sn—Cu series being attached to the electrode on which Ni/Au or Ag—Pd alloy is plated. This restrains formation of intermetallic compounds and provides high bonding reliability.
    Type: Grant
    Filed: November 18, 2013
    Date of Patent: June 6, 2017
    Assignee: Senju Metal Industry Co., Ltd.
    Inventors: Koji Watanabe, Minoru Toyoda, Satoshi Tomita, Tsutomu Sugino, Daichi Kikuchi, Hiroki Oshima
  • Patent number: 9661761
    Abstract: A carrier substrate includes an insulation layer, conductive towers and a circuit structure layer. A diameter of each of the conductive towers is increased gradually from a top surface to a bottom surface, and the conductive towers include first conductive towers and second conductive towers surrounding the first conductive towers. The circuit structure layer is disposed on the insulation layer and includes at least one dielectric layer, at least two circuit layers and first conductive vias. Each of the second conductive towers correspondingly connects to at least two of the first conductive vias, and each of the first conductive towers correspondingly connects to one of the first conductive vias. An interface exists between the first conductive vias and the first and the second conductive towers.
    Type: Grant
    Filed: August 13, 2013
    Date of Patent: May 23, 2017
    Assignee: Unimicron Technology Corp.
    Inventor: Chun-Ting Lin
  • Patent number: 9627347
    Abstract: A method of manufacturing a semiconductor device according to the present invention comprises: a bump forming step of forming a bump electrode 100 on a semiconductor chip 1, the bump electrode 100 protruding in a substantially conical shape; a pad forming step of forming a pad electrode 200 on a substrate 10, the pad electrode 200 having a recess 210 with inner lateral surfaces thereof defining a substantially pyramidal shape or a prism shape; a pressing step of pressing the bump electrode 100 and the pad electrode 200 in a direction which brings them closer to each other, with the bump electrode 100 being inserted in the recess 210 so that the central axis of the bump electrode 100 and the central axis of the recess 210 coincide with each other; and an ultrasonic joining step of joining the bump electrode 100 and the pad electrode 200 by vibrating at least one of the bump electrode 100 and the pad electrode 200 using ultrasonic waves.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: April 18, 2017
    Assignee: National Institute of Advanced Industrial Science and Technology
    Inventors: Masahiro Aoyagi, Thanh Tung Bui, Motohiro Suzuki, Naoya Watanabe, Fumiki Kato, Lai Na Ma, Shunsuke Nemoto
  • Patent number: 9591763
    Abstract: Disclosed substrate with embedded component includes: an insulating base member; a conductive pad formed on the insulating base member; a component connected to the conductive pad with a solder; and a resin covering the component, wherein a hole is provided in the insulating base member and the conductive pad, and the insulating base member is exposed on a side surface of the hole.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: March 7, 2017
    Assignee: FUJITSU LIMITED
    Inventors: Mitsunori Abe, Kiyoyuki Hatanaka, Nobuo Taketomi, Shigeo Iriguchi, Ryo Kanai, Naoki Nakamura
  • Patent number: 9543673
    Abstract: A connecting pin for an electronic circuit board electrically connects a lead of a component to be surface-mounted to the electronic circuit board to a coating layer on an inner wall of a through-hole of the electronic circuit board. The connecting pin includes a cylindrical body formed of an electrically conductive metal, which is inserted into the through-hole of the electronic circuit board. The lead of the component is press-fitted, and inner surface of the cylindrical body is provided with a plurality of small protrusions deformable when contacting protrusions of the press-fitted lead.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: January 10, 2017
    Assignee: HYUNDAI MOTOR COMPANY
    Inventor: Do Seop Kim
  • Patent number: 9520509
    Abstract: Various methods for preparing and/or processing electrically conductive aluminum members such as used in electronic circuits and components are described. Also described are various sheet assemblies using patterned aluminum conductive elements as components of electric circuitry. The sheet assemblies can be used as backsheets for back contact photovoltaic cells or as antennas for RFID tags.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: December 13, 2016
    Assignee: AVERY DENNISON RETAIL INFORMATION SERVICES, LLC
    Inventors: Kourosh Kian, Peikang Liu, Stephen Li
  • Patent number: 9510474
    Abstract: A solid state drive (SSD) assembly and an assembly method for solid state drives, which does not require using screws. The assembly method includes aligning a printed circuit board with a first cover and a second cover, the first cover having pre-installed standoffs on an inner surface thereof. The printed circuit board and the second cover respectively having a first set of through-holes, and the first set of through-holes correspond to the standoffs. The assembly method further includes placing the printed circuit board between the first and second covers, thereby exposing an end portion of each of the standoffs in the through-holes of the second cover, and deforming the end portion of each of the standoffs about the through-holes, thereby fastening the first and second covers with one another.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: November 29, 2016
    Assignee: KINGSTON TECHNOLOGY COMPANY
    Inventors: Peter Leekuo Chou, Stephen Chien, William Tai
  • Patent number: 9506831
    Abstract: A micromechanical measuring element includes a carrier and a sensitive element connected to the carrier by a first solder connection and a second solder connection. The sensitive element is contacted electrically by the first solder connection. The sensitive element, the carrier and the second solder connection form a first chamber. The first chamber has a first opening.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: November 29, 2016
    Assignee: EPCOS AG
    Inventors: Michael Schiffer, Andreas Peschka, Jörg Zapf, Karl Weidner, Harry Hedler
  • Patent number: 9424966
    Abstract: A method for forming an electrical connection structure part according to the present invention includes a step of covering, with an alloy body, a connection part between a first conductor part and a second conductor part, so as to form the electrical connection structure part. The first conductor part contains aluminum. The second conductor part has a surface covered with an ingredient containing nickel. The alloy body contains tin, silver, and nickel. The method further includes steps of: connecting the first conductor part and the second conductor part to each other to form the connection part; melting the alloy body; and dipping at least the connection part into the molten alloy body.
    Type: Grant
    Filed: May 31, 2013
    Date of Patent: August 23, 2016
    Assignee: Panasonic Intellectual Property Management Co., Ltd.
    Inventors: Kenji Kondo, Takehiko Hasegawa, Yugo Ryu, Akihiko Watanabe, Seiji Kurozumi
  • Patent number: 9337131
    Abstract: An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.
    Type: Grant
    Filed: September 29, 2014
    Date of Patent: May 10, 2016
    Assignee: Alpha and Omega Semiconductor (Cayman) Ltd.
    Inventors: Yan Huo, Hamza Yilmaz, Jun Lu, Ming-Chen Lu, Zhi Qiang Niu, Yan Xun Xue, Demei Gong
  • Patent number: 9252510
    Abstract: Disclosed is a soldering structure for mounting at least one connector on a flexible circuit board. The connector includes SMD pins and solder-dipping pins. The flexible circuit board has a connector mounting section having a component surface on which SMD soldering zones and solder-dipping pin holes are formed. A reinforcement plate is coupled to a reinforcement bonding surface of the flexible circuit board. The reinforcement plate has through holes corresponding to the solder-dipping pin holes of the flexible circuit board. The SMD pins of the connector are respectively soldered to the SMD soldering zones of the flexible circuit board, and the solder-dipping pins of the connector are respectively inserted through the solder-dipping pin holes of the flexible circuit board and the through holes of the reinforcement plate to the soldering surface of the reinforcement plate to be soldered with a solder material.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: February 2, 2016
    Assignee: Advanced Flexible Circuits Co., Ltd.
    Inventors: Gwun-Jin Lin, Kuo-Fu Su, Chih-Heng Chuo
  • Patent number: 9129832
    Abstract: An LED multi-chip bonding die (1) comprises a packaging enclosure, a plurality of LED chips and a packaging cover, wherein the chips are arranged in one line from top to bottom on the emitting platform. Large area electrodes are equipped on the packaging enclosure and the packaging cover is made of transparent silicone gel so that the bonding die can emit larger light energy and higher luminance via the packaging cover while the heat produced by the chips can be quickly dissipated by the electrodes. A light strip (20) equipped with the bonding die comprises a plurality of bonding die sections and circuit board (2) and each bonding die section (1) comprises four LED multi-chip bonding dies (1) and a current-limiting resistor in series circuit. Each series circuit is connected in parallel and circuit board (2) is printed circuit board which can provide a optimal heat-dissipating structure for chips of bonding die.
    Type: Grant
    Filed: August 26, 2008
    Date of Patent: September 8, 2015
    Inventor: Dingguo Pan
  • Patent number: 9089043
    Abstract: A first substantially annular conductive material has a first central opening, the first central opening is sufficient to substantially surround a fastener and maintain an electrical connection between the printed circuit board and the chassis. A second substantially annular conductive material is concentric with the first conductive material and the second conductive material hays a second central opening which is sufficient to substantially surround the fastener and maintain the electric connection between the printed circuit board and the chassis. A substantially annular impedance material is between and adjacent to the first conductive material and the second conductive material, the impedance material is sufficient to attenuate the electromagnetic interference from the system.
    Type: Grant
    Filed: July 23, 2013
    Date of Patent: July 21, 2015
    Assignee: International Business Machines Corporation
    Inventors: Edward C. Gillard, Don A. Gilliland
  • Patent number: 9048332
    Abstract: A semiconductor device manufacturing method includes: a first-process for placing, on a first-substrate on which traces and first-electrodes are formed, each of the first-electrodes being connected to one of traces, a second-substrate in which through-holes corresponding to the first-electrodes and relay-members are disposed, each of the relay-members being formed of solder, penetrating through one of the through-holes, and projecting from both ends of the one of the through-holes, so that the first-electrodes are aligned with the through-holes in a plan view; a second-process for melting the relay-members so that the relay-members are connected to the first-electrodes, after the first-process; and a third-process for placing a semiconductor substrate on which a second-electrodes corresponding to the first-electrodes are formed on a side opposite to the first-substrate across the second-substrate, after the second-process, to connect the first-electrodes and the second-electrodes to each other via the relay-m
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: June 2, 2015
    Assignee: FUJITSU LIMITED
    Inventors: Mamoru Kurashina, Daisuke Mizutani
  • Patent number: 9035195
    Abstract: Provided is a circuit board having a tie bar buried therein. The circuit board includes a dielectric stack, at least a first tie bar, at least a first gold finger and at least a first microvia. The dielectric stack includes a first dielectric layer and a second dielectric layer. The first dielectric layer is located on the second dielectric layer. The dielectric stack includes a wireline region and a gold finger region. The first tie bar is buried in the gold finger region between the first dielectric layer and the second dielectric layer. The at least a first gold finger is located in the gold finger region on the first dielectric layer. The first microvia is located in the gold finger region in the first dielectric layer, and electrically connects the first gold finger to the first tie bar.
    Type: Grant
    Filed: November 12, 2012
    Date of Patent: May 19, 2015
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Hsin-Mao Huang, Chun-Huang Yu
  • Patent number: 9024208
    Abstract: In accordance with embodiments of the present disclosure, a circuit board may include a first trace formed in a first layer of the circuit board, a second trace formed in a second layer of the circuit board, a via, and a termination pad. The via may be configured to electrically couple the first trace to the second trace, the via comprising a via stub corresponding to a first portion of a length of the via not within a second portion of the via between a first location in which the first trace is electrically coupled to the via and a second location in which the second trace is electrically coupled to the via. The termination pad may be formed at an end of the via stub opposite at least one of the first location and the second location.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: May 5, 2015
    Assignee: Dell Products L.P.
    Inventors: Bhyrav M. Mutnury, Sandor Farkas, Stuart Allen Berke
  • Patent number: 8999537
    Abstract: A battery pack configured to prevent excess solder material from flowing down onto a protective circuit module (PCM) is disclosed. According to some aspects, the battery pack includes at least one battery cell, a protective circuit module (PCM) electrically connected to the battery cell, and a conductive tab configured to electrically connect the battery cell to the PCM. A tapered through hole is formed in the PCM so that the conductive tab is inserted into and fixed to the through hole.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: April 7, 2015
    Assignee: Samsung SDI Co., Ltd.
    Inventor: Eunyoung Kim
  • Patent number: 8975525
    Abstract: A multi layer interconnecting substrate has at least two spaced apart metal layers with a conductive pad on each one of the metal layers. Two different types of insulating layers are placed between the metal layers. The placement is such that one of the two different types of insulating layers is placed between the conductive pads and the other type of insulating layer is placed between the two spaced apart metal layers.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Kevin Bills, Mahesh Bohra, Jinwoo Choi, Tae Hong Kim, Rohan Mandrekar
  • Patent number: 8975528
    Abstract: Even in an electronic device where electrodes are coupled electrically using a solder, sections to which electrodes of an electronic component are coupled are switched by a method other than changing circuits of the electronic component or changing circuits of a wiring substrate. The electronic device includes: a wiring substrate having two or more first electrodes over one surface thereof; and an electronic component having, over one surface thereof, two or more second electrodes arranged corresponding to the two or more first electrodes, respectively. At least one of the first electrodes is a specific electrode divided into two or more divided portions, and the divided portions are coupled to different wirings, respectively. Further, at least one of the divided portions is coupled to a corresponding second electrode through a solder.
    Type: Grant
    Filed: August 21, 2012
    Date of Patent: March 10, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Shuuichi Kariyazaki
  • Publication number: 20150060127
    Abstract: A combined printed wiring board includes a multilayer printed wiring board, and a wiring film fixed to a surface of the multilayer printed wiring board and including a first wiring structure formed to connect multiple semiconductor elements and a second wiring structure formed to connect the multilayer printed wiring board and each of the semiconductor elements.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Applicant: IBIDEN CO., LTD.
    Inventors: Makoto Terui, Takashi Kariya, Yoshinori Shizuno, Masatoshi Kunieda
  • Patent number: 8969730
    Abstract: Printed circuits may be electrically and mechanically connected to each other using connections such as solder connections. A first printed circuit such as a rigid printed circuit board may have solder pads and other metal traces. A second printed circuit such as a flexible printed circuit may have openings. Solder connections may be formed in the openings to attach metal traces in the flexible printed circuit to the solder pads on the rigid printed circuit board. A ring of adhesive may surround the solder connections. The flexible printed circuit may be attached to the rigid printed circuit board using the ring of adhesive. An insulating tape may cover the solder connections. A conductive shielding layer with a conductive layer and a layer of conductive adhesive may overlap the solder joints. The conductive adhesive may connect the shielding layer to the metal traces on the rigid printed circuit board.
    Type: Grant
    Filed: August 16, 2012
    Date of Patent: March 3, 2015
    Assignee: Apple Inc.
    Inventors: Anthony S. Montevirgen, Emery A. Sanford, Stephen Brian Lynch
  • Patent number: 8964402
    Abstract: An electronic device includes a wiring board including a first electrode and a second electrode, a semiconductor device mounted on the wiring board and including a first terminal and a second terminal, an interposer provided between the wiring board and the semiconductor device, the interposer including a conductive pad and a sheet supporting the conductive pad, the conductive pad having a first surface on a side of the wiring board and a second surface on a side of the semiconductor device, a first solder connecting the first electrode positioned outside of an area in which the interposer is disposed with the first terminal positioned outside of the area, a second solder connecting the second electrode positioned inside of the area with the first surface of the conductive pad, and a third solder connecting the second terminal positioned inside of the area with the second surface of the conductive pad.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: February 24, 2015
    Assignee: Fujitsu Limited
    Inventors: Teru Nakanishi, Nobuyuki Hayashi, Masaru Morita, Yasuhiro Yoneda