Abstract: An electrical structure and method of forming. The electrical structure includes a first substrate, a first dielectric layer, an underfill layer, a first solder structure, and a second substrate. The first dielectric layer is formed over a top surface of the first substrate. The first dielectric layer includes a first opening extending through a top surface and a bottom surface of said first dielectric layer. The first solder structure is formed within the first opening and over a portion of the top surface of said first dielectric layer. The second substrate is formed over and in contact with the underfill layer.

Abstract: A wiring board has predetermined numbers of wiring layers and insulating layers among the respective wiring layers. The wiring board has an external connecting pad and a surface plating layer for connecting to an external circuit is arranged on the external connecting pad. An area of an external connecting pad is smaller than an area of a surface plating layer thereof.

Abstract: A wiring board has a first wiring board having a first solder-resist layer, a second wiring board connected to the first wiring board and positioned in a first opening portion formed in the first solder-resist layer of the first wiring board, and a third wiring board connected to the first wiring board and positioned in a second opening portion formed in the first solder-resist layer of the first wiring board such that the second wiring board and the third wiring board are on the same side of the first wiring board. The first opening portion of the first wiring board and the second opening portion of the first wiring board form either a common opening portion accommodating the second and third wiring boards in the first solder-resist layer or separate opening portions separately accommodating the second wiring board and the third wiring board in the first solder-resist layer.

Abstract: Disclosed is a connection structure for a circuit board using a solder bump to arrange circuit boards. The circuit board connection structure includes a solder bump prepared on one of two circuit boards and a perforated part formed at the other of the circuit boards to receive the solder bump. Facing both circuit boards towards each other and inserting the solder bump into the perforated part, the circuit boards are desirably arranged.

Abstract: A wiring board (package) has a structure in which multiple wiring layers are stacked one on top of another with insulating layers each interposed between corresponding two of the wiring layers, and the wiring layers are connected to each other through vias formed in the insulating layers. In the peripheral region around the chip mounting area of the outermost insulating layer on one of both surfaces of the board, a pad is formed in a bump shape to cover a surface of a portion of the outermost insulating layer, the portion being formed to protrude, and a pad whose surface is exposed from the insulating layer is arranged in the chip mounting area. A chip is flip-chip bonded to the pad of the package, and another package is bonded to the bump shaped pad in a peripheral region around the chip (package-on-package bonding).

Abstract: A component can include a substrate having a first surface and a second surface remote therefrom, an opening extending in a direction between the first and second surfaces, and a conductive via extending within the opening. The substrate can have a CTE less than 10 ppm/° C. The conductive via can include a plurality of base particles each including a first region of a first metal substantially covered by a layer of a second metal different from the first metal. The base particles can be metallurgically joined together and the second metal layers of the particles can be at least partially diffused into the first regions. The conductive via can include voids interspersed between the joined base particles. The voids can occupy 10% or more of a volume of the conductive via.

Abstract: According to an aspect of the invention, there is provided a circuit board assembly including a first circuit board including a first circuit pattern formed on a surface of the first circuit board, and an opening that is adjacent to the first circuit pattern; and a second circuit board including a second circuit pattern corresponding to the first circuit pattern and a protection film that is applied to a surface of the second circuit board so as to form a hollow place located corresponding to the opening, wherein the first circuit board and the second circuit board are combined with each other.

Abstract: Micro-vias that are conventionally used for vertical connections in wire or circuit boards may be used for an entirely different purpose; the micro-vias may be used in the creation of solder joints to initiate the controlled formation of voids that increase the reliability of the solder joints.

Abstract: A multilayer printed wiring board includes a first interlaminar resin insulating layer, a first conductor circuit formed on the first interlaminar resin insulating layer, a second interlaminar resin insulating layer formed on the first interlaminar resin insulating layer and the first conductor circuit, a second conductor circuit formed on the second interlaminar resin insulating layer. A via conductor can be formed in the opening portion. The opening portion of the second interlaminar resin insulating layer can expose a face of the first conductor circuit. The via conductor connects the first conductor circuit and the second conductor circuit. The via conductor includes an electroless plating film formed on inner wall face of the opening portion and includes an electrolytic plating film formed on the electroless plating film and on the exposed face of the first conductor circuit exposed by the opening portion.

Abstract: A multilayer printed wiring board including a first interlayer resin insulation layer, a pad formed on the first interlayer resin insulation layer, a solder resist layer formed on the first interlayer resin insulation layer and the pad, a protective film formed on a portion of the pad exposed by an opening of the solder resist layer, and a coating layer formed between the pad and the solder resist layer. The pad mounts an electronic component. The coating layer has a metal layer and a coating film. The metal layer is formed on the surface of the pad and the coating film is formed on the metal layer.

Abstract: A wiring board with lead pins includes: connection pads formed on a wiring board, and lead pins bonded through a conductive material to the connection pads, wherein each of the lead pins has a head portion that is formed in one end of a shaft portion to be larger in diameter than the shaft portion, the head portions are bonded to the connection pads by the conductive material, a face of the wiring board on which the connection pads are formed is resin-sealed by a first resin to be thicker than the head portions, except portions to which the head portions are bonded, and sides of faces of the head portions to which the shaft portions are connected are sealed to be in close contact with the first resin by a second resin.

Abstract: A solder pad structure with a high bondability to a solder ball is provided. The present invention provides a larger contact area with the solder ball so as to increase the bondability according to the principle that the bondability is positive proportional with the contact area therebetween. The solder pad structure includes a circuit board having a solder pad opening defined by a solder resist layer surrounding a circuit layer. The circuit layer within the solder pad opening is defined as a solder pad. In such a way, after filling the solder ball into the solder pad opening, besides walls of the solder pad opening, there is an extra contact area provided by a geometric shape of the solder pad for further improving the bondability of the solder pad and the solder ball.

Abstract: This relates to systems and methods for providing one or more vias through a module of an electrical system. For example, in some embodiments, the module can include one or more passive and/or active elements of the electrical system around which a packaging has been plastic molded. The module can be stacked under another component of the electrical system. Vias can then be provided that extend through the module. The vias can include, for example, electrically conductive pathways. In this manner, the vias can provide electrical pathways for coupling the component stacked on top of the module to other entities of an electronic device including the electrical system. For example, the component can be coupled to other entities such as other components, other modules, printed circuit boards, other electrical systems, or to any other suitable entity.

Abstract: In a wiring board, insulation layers and wiring conductors are alternately laminated, and a plurality of strip-shaped wiring conductors for connecting semiconductor elements are arranged side by side on the outermost insulation layer. Each of the wiring conductors partly has a connection pad to which the electrode terminals of the semiconductor elements are connected by flip-chip bonding. In the wiring board, a solder resist layer is deposited over the outermost insulation layer and the strip-shaped wiring conductors so as to have slit-shaped openings for exposing the upper surfaces of the connection pads. The solder resist layer fills up the space between the connection pads adjacent to each other and exposed within the slit-shaped openings.

Abstract: A package substrate having landless conductive traces is proposed, which includes a core layer with a plurality of plated through holes formed therein, and a plurality of conductive traces formed on at least a surface of the core layer. Each of the conductive traces has a connection end, a bond pad end, and a base body connecting the connection end and the bond pad end, the conductive trace is electrically connected to a corresponding one of the plated through holes through the connection end, and the connection end has a width greater than that of the base body but not greater than the diameter of the plated through hole, thereby increasing the contact area between the conductive trace and the plated through hole and preventing the contact surface of the conductive trace with the plated through hole from cracking.

Abstract: A printed circuit board (PCB) can prevent electrostatic discharge. A number of vias are embedded in the PCB. A circular insulated member is disposed between each via and the number of vias. Each via includes a layer of metal coated on an inner wall of a corresponding insulated member and a through hole bounded by the corresponding insulated member. An acute angle between two tangents which pass through a point of intersection of two overlapped insulated members is greater than twenty degrees.

Abstract: A method of manufacturing a connector is provided. Firstly, a substrate having a first surface, a second surface opposite to the first surface and a through hole is provided. Next, a first conductive layer covering the inside wall of the through hole is formed on the substrate. Then, a filler is filled in the through hole to form a filler post. Next, a conductive elastic cantilever is formed over the first surface and electrically connected to the first conductive layer. Then, a gold layer is formed on the conductive elastic cantilever and over the first surface. A solder ball electrically connected to the first conductive layer is formed over the second surface.

Abstract: A modem, in particular for subsea power line communication, has electronic components on a circuit board, and a metal encapsulation, wherein the encapsulation forms at least two chambers separated by at least one wall, wherein each of the chambers surrounds at least one of the electronic components.

Abstract: A structure for transmission in a power supply, particularly to a power structure for transmission for bearing large DC current, wherein the power supply includes a power input port for connecting to DC input power and a DC/DC conversion circuit for converting the DC input power into DC output power. The architecture including at least one power transmission board for disposing the power input port, wherein the power transmission board is electrically connected to the power process board with the DC/DC conversion circuit mounted thereon by at least one power conduction element. Therefore, through the power conduction elements replacing the conventional connecting wires with large diameter to connect the power input port and the power process board without disobeying the safety regulation, not only the space occupied by the bent connection wires can be reduced, but the collisions and damage to other components caused therefrom also can be avoided.

Abstract: A battery pack configured to prevent excess solder material from flowing down onto a protective circuit module (PCM) is disclosed. According to some aspects, the battery pack includes at least one battery cell, a protective circuit module (PCM) electrically connected to the battery cell, and a conductive tab configured to electrically connect the battery cell to the PCM. A tapered through hole is formed in the PCM so that the conductive tab is inserted into and fixed to the through hole.

Abstract: A packaging system having a housing for providing a hermetically sealed interior space for receiving and supporting optoelectronic components. The housing has at least one section of wall comprising a layer of liquid crystal polymer (LCP). At least one hermetically sealed electrical port is formed in the LCP wall section over a predetermined area and comprises a layer of metal adhered to and overlying the predetermined area on the of the LCP wall section. An electrode passes through the metal from the exterior of the system to the interior space to provide an electrical communication path between the optoelectronic components and the exterior of said packaging system. A solder joint is formed between the electrode and the layer of metal to provide a hermetic connection between the layer of metal and the electrode to assure that the hermeticity of the housing remains unchanged with the electrical port present.

Abstract: A conductive substrate structure includes a substrate unit, a conductive pad unit, and a conductive layer unit. The substrate unit has a top surface, a bottom surface, two opposite lateral surfaces, and a front surface. The conductive pad unit has at least two first conductive pads separated from each other and disposed on the top surface, and at least two second conductive pads separated from each other and disposed on the bottom surface. The conductive layer unit has at least two first conductive layers formed on the front surface and respectively electrically connected to two front sides of the two first conductive pads, and at least two second conductive layers respectively formed on the two opposite lateral surfaces and respectively electrically connected to two opposite lateral sides of the two second conductive pads. The two first conductive layers are respectively electrically connected with the two second conductive layers.

Abstract: A printed circuit board can support different connectors by selectively setting connection components on the printed circuit board without changing wiring of transmission lines or making new vias in the printed circuit board.

Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

Abstract: Provided is a wiring structure and the like which can completely connect a wiring layer to a body to be wired while keeping insulation between two adjacent wiring layers and realize high density packaging due to a narrowed pitch. In a semiconductor-embedded substrate, a conductive pattern is formed on both sides of a core substrate and a semiconductor device is placed in a resin layer stacked over the core substrate. The resin layer has via-holes so that the conductive pattern and a bump of the semiconductor device protrude from the resin layer. Inside the via-holes, the bump and conductive pattern are respectively connected to via-hole electrode portions whose cross-sectional area has been increased toward the bottom of the via-hole. A void is defined between the via-hole electrode portion and upper portion of the inner wall of the via-hole.

Abstract: A coreless packaging substrate includes: a substrate body including an auxiliary dielectric layer having opposing first and second surfaces, an inner wiring formed on the second surface, and a built-up structure formed on both the second surface of the auxiliary dielectric layer and the inner wiring; and a plurality of conductive bumps including metal pillars having opposing first and second ends and a solder layer formed on the first end, wherein the second ends of the metal pillars are disposed in the auxiliary dielectric layer and electrically connecting with the inner wiring, and the first ends of the metal pillars with the solder layer protrude from the first surface of the auxiliary dielectric layer, thereby achieving ultra-fine pitch and even-height conductive bumps. A method for fabricating the coreless packaging substrate as described above is further provided.

Abstract: A substrate for mounting a semiconductor includes a first insulation layer having first and second surfaces on the opposite sides and having a penetrating hole penetrating through the first insulation layer, an electrode formed in the penetrating hole in the first insulation layer and having a protruding portion protruding from the second surface of the first insulation layer, a first conductive pattern formed on the first surface of the first insulation layer and connected to the electrode, a second insulation layer formed on the first surface of the first insulation layer and the first conductive pattern and having a penetrating hole penetrating through the second insulating layer, a second conductive pattern formed on the second insulation layer and for mounting a semiconductor element, and a via conductor formed in the penetrating hole in the second insulation layer and connecting the first and second conductive patterns.

Abstract: A wiring board includes: an uppermost wiring layer formed on a prescribed number of underlying wiring layers, a portion of the uppermost wiring layer being exposed and used as a pad for connection with a component to be mounted; and an insulation resin layer covering the uppermost wiring layer, wherein the thickness of the portion of the uppermost wiring layer is larger than that of other portions thereof.

Abstract: A surface mounting method includes applying an active resin composition to at least part of a surface of a printed wiring substrate; mounting a surface mount device on the substrate; performing reflow soldering; applying an under-filling resin into a space of interest; before and/or after applying the under-filling resin, performing a vacuum treatment and/or heating at a temperature lower than the curing reaction-initiating temperature of any of the applied active resin composition and the under-filling resin; and subsequently, thermally curing the resin composition and the under-filling resin. The active resin composition contains an epoxy resin in an amount of 100 parts by weight, a blocked carboxylic acid compound in an amount of 1-50 parts by weight and/or a carboxylic acid compound in an amount of 1-10 parts by weight, and a curing agent which can initiate curing reaction at 150° C. or higher, in an amount of 1-30 parts by weight.

Abstract: Embodiments of an integrated passive device include a high-aspect ratio conductive line positioned on a carrier, a substrate, and a bump that secures the high-aspect ratio conductive line to the substrate.

Abstract: An enhanced contact metallurgy construction for plastic land grid array (PLGA) modules and printed wiring boards (PWBs). The PWB may, for example, have subcomposite laminate construction and/or a double-sided LGA site. A plurality of preform contacts are each respectively soldered to one of a plurality of metal pads on a PLGA module carrier and/or a PWB. Each of the preform contacts comprises a metal preform base (e.g., copper, nickel) soldered to one of the plurality of metal pads and an electrolytic noble metal plating (e.g., gold) over the metal preform base. An electrolytic non-noble metal underplating (e.g., nickel) may be interposed between the metal preform base and the electrolytic noble metal plating. In one embodiment, the electrolytic non-noble metal underplating is 80-400 microinches thick to provide an enhanced diffusion barrier, and the electrolytic noble metal plating is 30-60 microinches thick and incorporates one or more hardening agents to provide enhanced wear and corrosion resistance.

Abstract: An exemplary printed circuit board preform (20) includes at least two printed circuit board units (211), at least one boundary (201, 202) formed on the junction of the at least two printed circuit board units, and at least one conductor (206, 208) configured on a surface of the printed circuit board preform and crossing the at least one boundary of the at least two printed circuit board units.

Abstract: A chip adapter used to install a chip on a first chip arranging area of a circuit board includes a board. The size of the board has the same size as the first chip arranging area of the circuit board. Edges of the chip adapter define a number of gaps corresponding to first pads of the circuit board. A second chip arranging area of the same size as the chip is arranged in a center of the chip adapter. A number of second pads are arranged around the second chip arranging area of the chip adapter corresponding to pins of the chip. Each second pad is electrically connected to a sidewall of the corresponding gap of the chip adapter.

Abstract: An integrated circuit package system includes: providing a package substrate; mounting an interposer chip containing active circuitry over the package substrate; attaching a conductive bump stack having a base bump end and a stud bump end, the base bump end on the interposer chip; connecting a stack connector to the interposer chip and the package substrate; and applying a package encapsulant over the interposer chip, the stack connector, and the conductive bump stack with the stud bump end of the conductive bump stack substantially exposed.

Abstract: The present invention provides a plating film 50 including a nickel plating layer containing phosphorus and a gold plating layer formed on the nickel plating layer, wherein the nickel plating layer has a phosphorus content of 11 to 16 mass %, and wherein (3×?×100)/X is 10 or less, where X and ? are the average value and standard deviation of the phosphorus content in a surface of the nickel plating layer on the gold plating layer side, respectively; and a module substrate 100 having the plating film 50.

Abstract: A wiring board includes: wiring layers; insulating layers disposed between the wiring layers; and external connection pads respectively including surface plated layers, for connecting to an external circuit. In each of the external connection pads in one face of the wiring board, an outer peripheral edge of the external connection pad is retracted from an outer peripheral edge of the surface plated layer toward a center of the external connection pad.

Abstract: A socket contact terminal for electrical connection between a connection portion formed of a metal conductor on a printed circuit board and a connection terminal of an IC package. The contact terminal comprises a metal terminal composed of a main columnar portion and arm portions on both sides and having an angular U shape and an elastomeric member attached to the metal terminal. A metal surface is exposed from the outer surface of each arm portion. The elastomeric member is firmly held between the arm portions of the metal terminal and exhibits a repulsive force when the arm portions are pressed in the direction that the arm portions approach each other.

Abstract: An interposer and a method of manufacturing the same are provided. The interposer includes a substrate and a conductor portion formed inside the substrate. At least one insulating layer is formed on the substrate and on the conductor portion. A signal wiring portion is formed inside the insulating layer or on the insulating layer. A first pad is configured to receive an electronic part, and is formed on an outermost insulating layer of the at least one insulating layer. A connection conductor is formed in the at least one insulating layer so as to electrically connect the conductor portion to the first pad.

Abstract: A cut-edge positioning type soldering structure and a method for preventing a pin deviation can prevent a plurality of pins of an electronic component from being deviated when the pins are soldered onto a printed circuit board by a solder, and each of at least two solder pads includes at least two cut edges, and the solder pads are installed in an alignment direction on the printed circuit board, such that the cut-edge positioning type soldering structure and the method for preventing a pin deviation can improve the efficiency of manufacturing processes and reduce the manufacturing cost.

Abstract: Inspection windows are cut or formed into the tail section of the flexure circuit tail in a hard disk drive Head Gimbal Assembly (HGA), or CIS, to enable visual inspection of the alignment of the CIS to the head preamp circuit, or FPC. The holes are made in the steel backing and base polyimide, and are positioned between adjacent conductive pads. In addition to facilitating visual inspection, the windows also enable rework of solder. Additionally, solder wicking holes may also be provided in the conductive pads and/or the polyimide and steel backing.

Abstract: A printed circuit board (PCB) ball grid array (BGA) system is provided. In one embodiment, the PCB BGA system includes a PCB, a PCB BGA pad formed on the PCB, a plated through-hole via disposed at least partially through the PCB proximate the PCB BGA pad, and a soldermask disposed over the PCB. The soldermask includes: (i) a BGA pad opening through which the PCB BGA pad is exposed, and (ii) a via opening through which a central portion of the plated through-hole via is exposed. The via opening has an inner diameter that is less than the outer diameter of the plated through-hole via.

Abstract: It is an object to form a conductive intermediate layer having a function of maximally preventing a solder leaching phenomenon with a low environment load and with good productivity. There are provided an insulative base material 2, a wiring circuit pattern 3 formed on at least one surface of the insulative base material 2, an electronic part mounting land 31 which is formed as part of the wiring circuit pattern 3 and on which an electronic part 7 is to be mounted, and a conductive intermediate layer 5 made of a sintered conductive ink film on the electronic part mounting land 31.

Abstract: The present disclosure relates to assessing coverage of a connection joint, such as a solder joint, between a device and a printed circuit board (PCB). In accordance with various embodiments, a PCB includes a conductive thermal pad adapted to be electrically and mechanically connected to an exposed pad of a component by an intervening connection joint to establish a thermal path to dissipate thermal energy from the component. An isolated test via that extends through the conductive thermal pad in non-contacting relation thereto, the test via adapted to mechanically and electrically contact said intervening connection joint. A coverage characteristic of the intervening connection joint can be determined in relation to application of an electrical signal to the test via.

Abstract: An electronic part mounting board includes an insulating board, a pad formed on the insulating board, a bump formed on the pad, and a film having heat resistance and electrical insulating properties and formed on the insulating board except the pad and the bump. A method of mounting an electronic part on the mounting board is also disclosed.

Abstract: According to one embodiment, there is provided a printed circuit board, including a frame ground portion in which conductor patterns are formed around a board-fixation hole, and a plurality of through-holes formed around the board-fixation hole in the frame ground portion.

Abstract: A method of electrically interconnecting a semiconductor chip to another electronic device including providing a carrier including contact pins and a chip attached to the carrier, the chip having a copper contact pad that faces away from the carrier, extending a copper electrical connector between the contact pins and the contact pad, and diffusion soldering the copper electrical connector to the active area with a solder material including tin to form a solder connection including a contiguous bronze coating disposed between and in direct contact with both the copper electrical connector and the contact pad.

Abstract: A method for electrically interconnecting two substrates, each having a corresponding set of preformed electrical contacts, the substrates comprising an electronic circuit, and the resulting module, is provided. A liquid curable adhesive is provided over the set of contacts of a first substrate, and the set of electrical contacts of the second substrate is aligned with the set of electrical contacts of the first substrate. The sets of electrical contacts of the first and second substrate are compressed to displace the liquid curable adhesive from the inter-contact region, and provide electrical communication between the respective sets of electrical contacts. The liquid curable adhesive is then cured to form a solid matrix which maintains a relative compression between the respective sets of electrical contacts. One embodiment of the module comprises a high-speed superconducting circuit which operates at cryogenic temperatures.

Abstract: When U-shape formed electronic components having an axial lead shape are mounted upright on a printed board, two U-shape formed electronic components having an axial lead shape are arranged so as not to be in the same straight line, and a wiring pattern is formed in a state where bent-side lead wires have the same electric potential, and the electronic components are inclined so as to place the bent-side lead wires close to each other, whereby the electronic components that tend to fall in the inclined direction can be mutually supported by the bent-side lead wires. Thus, the electronic components can be prevented from falling without spoiling a heat dissipation performance of the electronic component and the board, and without greatly deteriorating an assembly performance of the board.

Abstract: A wiring board has a wiring board main body, a solder resist and solder bumps. The solder resist is formed on a top surface of the wiring board main body, and includes first openings, and second openings that have a diameter larger than that of the first openings. The solder bumps are disposed in the first openings and in the second openings. In addition, top portions of the solder bumps disposed in the first openings have a flat face, while top portions of the solder bumps disposed in the second openings have a non-flat face.

Abstract: The invention relates to a method of interconnecting electronic components of a first wafer (T1) with electronic components of a second wafer (T2), each wafer having metallized vias (1) which pass through the wafer in the thickness direction. The method includes deposition of a drop (3) of conductive ink containing solvents on each via (1) of the first wafer (T1); stacking of the second wafer (T2) on the first so that the vias (1) of the second wafer (T2) are substantially superposed on the vias (1) of the first wafer (T1); removal of 50 to 90% of the solvents contained in the drops (3) by heating or applying a vacuum, so as to obtain a pasty ink; and laser sintering of the pasty ink drops (3) so as to produce electrical connections (31) between the superposed metallized vias (1).