Abstract: A protective heat sink for an electronic component dissipates heat generated thereby. A first heat conductive member is mounted to the top side of the electronic component. A protective cap having an aperture formed therein is mounted on the printed circuit board such that it extends over the electronic component and the first heat conductive member. A second heat conductive member is mounted to the first heat conductive member and extends through the aperture in the cap such that heat generated by the electronic component is transmitted to the first heat conductive member and then dissipated to the environment by the second heat conductive member.

Abstract: A method and apparatus to encapsulate a device and joints coupled to conductive leads with an encapsulating material. A fixture has a recess to hold via a vacuum the device in place. Conduits in the fixture supply air around the device to form an air dam that flows outward around the device and the leads. A nozzle supplies a metered amount of material to the surface of the device. By controlling the temperature of the fixture and/or the air forming the air dam, the flow of material can be confined to the surface of the device and the joints as it cures. The method can also provide encapsulant edge capping to reduce device stresses.

Abstract: An IC socket having internal MOV devices for protecting an integrated circuit from damage due to transient overvoltages.Each MOV device is coupled between a lead of the socket and a common metallic grounding strip contained within the IC socket. The grounding strip has an output lead which is brought through the socket for connection to a convenient system grounding point.

Abstract: A device for hermetically protecting integrated circuits is disclosed. The device includes a plastic housing which has a cavity. The cavity forms an opening at the top of the housing and extends toward the bottom of the housing where a metallic slug is positioned. The cavity also includes one or more bond shelves descending from the top of the housing toward the bottom of the housing. The bond shelves support conducting bond pads which are coupled to connecting pins which extend from the housing. An integrated circuit with a number of integrated circuit bond pads is attached by an epoxy to the bottom of the cavity. Bond wires couple the integrated circuit bond pads and the bond shelf pads. A liquid is dispensed in the cavity such that the liquid extends from the bottom of the cavity to a position above the bond wires. A properly selected liquid provides protection for the integrated circuit and its electrical connections.

Abstract: A method of forming an enclosure for an electric circuit and the enclosure wherein there is provided a boat of material having a bottom and side wall, placing a material having a substantially higher thermal conductivity and a lower melting point than that of the boat in the boat bottom, heating the material to a temperature above the melting point thereof and below the melting point of the boat to cause the material to flow along the bottom to form a layer of the material thereon and join the layer to the bottom and side wall and removing a sufficient amount of the bottom of said boat to expose the layer. In accordance with a second embodiment, a depression is formed in the bottom, and when the material flows along the bottom, it fills the depression and becomes joined to the bottom. Plural such depressions can be provided. The exterior portion of the bottom is removed to expose the material if the depressions do not extend completely through the bottom.

Abstract: An IC is provided with supply pins extending beyond the chip's encapsulation. The location of the supply pins is chosen so as to minimize the length of the associated bonding wires. Moreover the supply pins are located next to each other so as to reduce the effective inductance of the associated bonding wires. Output pins connected with on-chip buffers are located next to the supply pins so as to reduce the length of the buffer's supply lines, giving rise to a further reduction is inductive parasitic effects.

Abstract: A film carrier is used for fabricating a semiconductor device, and comprises an insulating film and a plurality of conductive leads each extending on the insulating film and having a front side surface and a reverse side surface, and a bump is formed in each of the conductive leads and has a projecting surface projecting from the reverse side surface and a depressed surface defining a recess open to the front side surface, so that the bump has a dome-shaped configuration and is much liable to deform in a thermocompression bonding stage.

Abstract: A generic chip carrier is described which includes, as integral parts, a voltage bus and a plurality of terminating resistors connected between the voltage bus and signal traces on the carrier. The voltage bus wraps around the chip carrier, thus providing a large area of metal. Through the selective use of the terminating resistors, the generic carrier can be customized for a particular type of integrated circuit, i.e., source or destination termination of signals. A signal trace may be customized by "operating" the terminating resistor with a current spike applied by a standard electrical probe. Spare bonding pads and terminating resistors are placed at intervals about the periphery of the carrier as insurance against defective or mistakenly removed terminating resistors.

Abstract: A hermetically sealed surface mount electronic component package can be manufactured by converting standard, readily available flat-packs. The package has a base, with an opening through which a primary transmission lead extends, a glass-to-metal seal surrounding the transmission lead in the opening, and a secondary transmission lead extends from the primary transmission lead so that it is spaced from the base and its end is at least flush with the bottom of the base. An insulator can be provided between the primary transmission lead and the secondary transmission lead. A method of converting a standard flat-pack by providing a composite piece having a dielectric insulator, a secondary transmission lead for connection to the transmission lead of the flat-pack, and a connecting member for connecting the insulator and secondary transmission lead to the base of the flat-pack is also described.

Abstract: A lead frame and an electronic device incorporating the lead frame wherein the lead frame includes a chip support and a plurality of leads arranged around the chip support with each of the plurality of leads having one end disposed proximate to the chip support. The one end of at least one of the plurality of leads includes a first lead portion extending in a direction toward the chip support and a second lead portion contiguous with the first lead portion. The second lead portion extends in a direction away from the chip support so that the one of the lead has a bent shape.

Abstract: A tape automated bonding (TAB) frame and a process for testing the same. The frame is designed to receive a die, an integrated chip or other similar components having output leads. The frame generally comprises a relatively thin film of dielectric material, a pattern of substantially adjacent inner lead bonds, a pattern of substantially adjacent outer lead bonds for providing input/output ports to the die, and a pattern of substantilly adjacent probe points for providing test points to the frame and the die thereon. A generally flat and rigid plate is mounted on a prober for supporting both a cut-out portion of the frame and the die thereon. The testing process includes the steps of excising the die from the frame in the form of a coupon, such that the coupon contains the pattern of scrap probe points on the TAB frame and the die; placing the excised coupon onto the prober; aligning the coupon; and testing the coupon and the die.

Abstract: A TO-8 surface-mount package assembly for R.F. and microwave devices is disclosed. The assembly includes a lead-frame positioned beneath an alumina base. The alumina base supports a number of solid metal vias. The vias electrically connect the lead-frame to an R.F. or microwave device which is attached to the vias. The assembly also includes a gold plated Kovar seal-ring positioned over the base. The seal-ring and base are brazed together. A cover is then positioned over the seal-ring and welded to the seal-ring.

Abstract: A hermetically sealed chip carrier including a lead frame for use with an EEPROM chip, the carrier including a pre-molded plastic beam and an ultra violet transparent cover.

Abstract: An SMT electronic component is mounted to a solder-bearing floatation plate by fusible or other heat-responsive releasable mounting means which suspend the component above the floatation plate. The bottom of the floatation plate is effectively substantially the mirror image of a component-positioning pad formed on the board surface adjacent the solder-bearing contact pads corresponding to the electrical contacts on the component. In the assembly process, the floatation plate is placed on the positioning pad. The solder on the bottom of the floatation plate has a melting point lower than the release temperature of the mounting means and the melting point of the solder on the contact pads. With the floatation plate on the component-positioning pad, on heating the solder on the floatation plate liquifies first, wetting the component-positioning pad and floating the floatation plate and component on a thin film of molten solder.

Abstract: An hermetic package for power semiconductor devices is disclosed. The package includes a generally rectangular cavity with leads extending through the walls thereof. The bottom of the cavity is defined by a base which includes a pair of mounting tabs protruding from opposite corners thereof. The mounting tabs are configured to allow the packages to be nested together. A cover attached to the walls provides a hermetically sealed package.

Abstract: An electronic package including a first circuitized substrate (e.g., printed circuit board) and a flexible circuitized substrate wherein the flexible substrate is precisely aligned in removable manner relative to the first substrate. This is accomplished utilizing a retention member and associated frame member, the flexible circuitized substrate being precisely aligned and secured to the frame member. Elastomeric pressure exertion members are utilized to exert pressure against each of a plurality of individual circuitized sections of the flexible circuit member to thus effect engagement between the flexible substrate's contacts and respective conductors which constitute part of the circuit on the first substrate. Moveable clamp members may also be used to engage extending posts of the retention member, said clamp members also possibly acting against a stiffener member located on the first substrate's opposite surface from the flexible substrate.

Abstract: A grounding method for use in high frequency electrical circuitry has a conductive elastomeric member with a low resistivity per square. The conductive elastomeric member is placed in contact with the ground plane of a circuit board and a conductive housing within which the circuit board is situated. The conductive elastomeric member is deformed to flow into discontinuities of a ground path between the ground plane and the conductive housing so that the discontinuities do not act as antennae to radiate energy in response to high frequency signals.

Abstract: A metal cover plate for covering a semiconductor chip mounted on a package base plate comprises an upper central portion, a flange extending outwardly from outer edges of the central portion, and a side wall portion extending perpendicularly from the flange along all sides thereof. The central portion has at least one portion in parallel with the package base plate. The central portion is formed with reinforcing portions in the form ridges of gable roofs and valleys in cross section, formed along diagonal lines of the central portion or in the form of a ridge or rib substantially semicircular in cross section extending upwardly or downwardly along each diagonal line. Deflection of the top wall portion of the package during pressure application is thus be minimized.

Abstract: A heat-resistant package for electrical components comprises a housing composed of a plurality of independent side walls made of heat resistant ceramic material. Sealed-in leads are provided in one or more of the side walls. After the leads are installed, the ends of the side walls are brazed together to form a closed ring and that ring is brazed to the housing bottom wall. Also, a continuous metal ring may be brazed to the tops of the side walls. The brazings provide hermetic seals between the housing walls and they, along with the seal ring, provide compliance between the walls making the housing resistant to thermal shocks.

Abstract: Disclosed is a method for making a semiconductor device in which the Pin Grid Array (PGA) is improved so that a plurality of lead pins project from the undersurface of a metal base of a package substrate as input and output terminals of a Large Scale Integrated-circuit (LSI). The method comprises mounting a semiconductor chip on a heat sink to the base, superposing a printed circuit board on the base and connecting electrical lead pins to the outer ends of wiring patterns which are formed radially and downwardly projecting through the base, and assembling a metal shell to the upper surface of the base and covering the chip, bonding wires and wiring patterns, wherein the patterns are formed such that the outer ends of the patterns are located within the vicinity over the outermost rows and columns of through holes for connecting lead pins.

Abstract: A method and apparatus for bonding external leads of a solid state device to a lead frame, where a positional discrepancy between the solid state device and the lead frame is corrected not only in X-Y directions but also in the rotational direction so as to perform a high accuracy bonding. Discrepancies in the rotational direction are calculated after detecting two points of the solid-state device, and a sunction head holding such solid-state device is rotated to correct such discrepancy. One portion of the solid-state device is further detected and the discrepancy in X-Y direction is calculated so as to correct the relative positional discrepancy of the solid-state device and the lead frame.

Abstract: A method and apparatus for attaching the outer leads of a semiconductor package (preferably a Tape Automated Bonded circuit) to the traces on a printed circuit board is described. The outer leads of the package are configured in an angled orientation so that the tip of each lead extends downwardly below the lower surface of the package. As a result, placement of the package against the circuit board causes the leads to be biased downwardly against the traces. In order to accomplish this, the package is secured to the board using a rigid frame structure. The frame structure urges the edges of the package against the board. This insures that the leads make electrical contact with the traces in a fast and efficient manner, while avoiding problems associated with a lack of lead coplanarity.

Abstract: An integrated circuit package encapsulates a volatile memory chip and a backup battery for preserving data in the event of loss of main power supply. The package includes a finger lead assembly encapsulated within a body of non-conductive material, with a central base support finger lead being offset within an interconnect region. One terminal of the battery is welded to the offset base finger lead, and the integrated circuit chip is bonded directly onto the other battery terminals by a layer of conductive epoxy. The stacked assembly of the integrated circuit chip, the battery and the offset base finger lead is centered longitudinally and vertically within the interconnect region whereby the stacked assembly, including gold interconnect wires, are completely encapsulated within the molded package body, without increasing the standoff height of the package.

Abstract: A TAB tape or tape-like carrier used for an automatic bonding process when manufacturing high-frequency semiconductor devices has a plurality of electrically conductive circuit patterns on a flexible insulative film having a plurality of holes located in gaps between adjacent circuit pattterns. A ground layer is formed on a back surface of the insulative film, and electrically conductive layers or material are formed on inner peripherals walls of the holes or filled in the holes, so that the ground layer is electrically connected to the respective conductive layers or material.

Abstract: A semiconductor device assembly is made without a molded package by using a tape having a patterned insulating layer and a conductive layer joined thereto. A semiconductor die is seated on the conductive layer and electrically connected to leads of the patterned conductive layer. A body frame is positioned around the die and electrical leads and connections, and an encapsulant material is distributed over the frame and within the frame over the die and electrical leads and connections.

Abstract: A ceramic base used for a semiconductor device is plate-shaped and is made of a material consisting essentially of ceramic. In plan view, the base is rectangular and has four corner portions each located between two adjacent side walls. The corner portion comprises a main bevel and two auxiliary bevels located at respective sides of the main bevel and extending to the two side walls, respectively, so that two first corners are defined between the main bevel and the auxiliary bevels, respectively, and two second corners are defined between the auxiliary bevels and the side walls of the base, respectively.

Abstract: An integrated circuit package and method of making the package which allows an integrated circuit die to be bonded to a substrate without need of a carrier. The integrated circuit die has opposed active and passive surfaces and has lateral surfaces. An electrically insulative layer of material is deposited on the passive and lateral surfaces. A metal mask is formed to cover the active surface and the coated lateral surfaces. The metal mask includes slots which extend up the lateral surfaces and onto the active surface. The array of slots corresponds to an array of input/output contact pads on the active side. Metal is sputtered into the slots, whereafter the mask is removed to provide L-shaped conductive traces from the contact pads along the active and lateral sides. The assembly can then be rested on a substrate on the passive surface and the L-shaped traces bonded to contact pads on the substrate. The assembly allows testing at the die level.

Abstract: A sealable hermetic microchip package includes a vent therein that permits gas to escape during the sealing operation, but then itself is sealed at the completion of the sealing operation to render the package hermetic. The venting of gas from the interior of the package avoids the buildup of internal pressure during the sealing operation that can introduce bubbles and other faults into the sealing material. The vent may be a channel in the sealing surface of the lid of the package that is initially open, and then fills with the seal material as it flows to effect the seal. The vent may also be a hole in the lid that is sealed by the flow of a bead of the seal material. An equivalent approach to venting provided that the lid be mounted on standoffs that flow during sealing to permit the lid to settle onto the base of the package.

Abstract: A planar connector holder for optical fibers having storage compartments for incoming fibers and a mounting region for connectors to outgoing fibers. Two storage compartments lie back-to-back on each side of a planar base of the holder, the compartments being interconnected for fiber to pass from compartment-to-compartment. The mounting region and the storage compartments are aligned from end-to-end of the holder. With connector mounts mounted in the mounting region, the mounts lie in planes common with the two storage compartments in a depth direction of the holder. Also included is a distribution frame and holder combination in which the holders are mounted in two banks with patch cords extending between the banks and selectively between connectors.

Abstract: A four quadrant leadframe, base and window assembly and assembly method therefor are disclosed which are suited for fabrication of leaded integrated circuit (IC) chip carriers having electrical contacts on all four sides of the package, lead spacing as small as 0.020 inch, and lead counts exceeding 164 total leads.

Abstract: Disclosed is a semiconductor chip package comprising a plurality of programmable pads located on a surface of the package, each pad being adapted for interconnection with a semiconductor chip. The package also includes a plurality of signal connectors located on a surface of the package. In addition the package includes a plurality of signal connections, each signal connection providing an electrically conductive path between an individual programmable pad and a corresponding individual signal connector. A plurality of dedicated power or ground connectors are also located on a surface of the package. Conductive paths within the package provide apparatus for selectively connecting any programmable pad to a power or ground connector, any pad so connected also remaining connected to a corresponding signal connector.

Abstract: A method of manufacturing a circuit board, comprising the steps of providing an electric conductor on one surface of a substrate made of flexible synthetic resin and selectively irradiating a laser beam onto the substrate from the other surface of the substrate so as to sublimate a portion of the substrate such that an opening is formed on the substrate, with the electric conductor traversing the opening.

Abstract: A carrier tape includes a film having an opening for receiving a semiconductor chip to be resin-molded by a pair of mold halves and outer lead holes formed around the periphery of the opening, a plurality of leads for mounting the semiconductor chip on the film, and a resin running portion cooperating, when the mold halves are closed with the film held between the mold halves, with a gate formed on a parting surface of one of the mold halves to define a resin running path which extends from a portion of the film outside the outer lead holes to the opening for guiding a molten resin into the mold halves while preventing the resin from entering the outer lead holes.

Abstract: An integrated circuit package includes a rectangular base, and a continuous sidewall which extends upwardly from the periphery of the base. Microelectronic circuit components are mounted on the base in a cavity defined within the sidewall. A domed lid includes a resilient central domed portion which arches above the cavity. A peripheral edge portion of the lid extends downwardly into the cavity by a small distance, adjacent to the inner surface of the sidewall. A lip extends outwardly from the edge portion and is sealingly welded at its periphery to the upper surface of the sidewall. The joint between the lip and edge portion is resilient and acts as a hinge, such that when a force or pressure is applied to the domed portion, the edge portion rotates about the hinge into abutment with the inner surface of the sidewall. This transfers a major component of the applied force to the sidewall, and resists deflection of the domed portion into the cavity.

Abstract: An electronic circuit component housing assembly adapted to be mounted mechanically on a printed circuit, using a single mechanical fastener to attach the circuit component housing assembly in a unique alignment with the printed circuit, and simultaneously using the fastener to provide force to press physically compliant electrical contacts included in the circuit component housing assembly into electrical contact with terminal contact pads on the printed circuit. Several electronic circuit components may be housed in separate hermetically sealed cavities and can be biased independently of one another. Thermal conductors are included in the base member and a convection cooler is mounted atop the assembly. The mechanical fastener also acts as a thermal conductor. A test probe assembly including multiple contacts mounts on the electronic circuit component housing.

Abstract: Disclosed is a radial solution to integrated circuit chip carrier pitch deviation. The invention comprises a chip carrier comprising a carrier body with a plurality of fine pitch metalizations. Each of the metalizations includes an axis with an extension line that intersects a point common to all axes so that each metalization may be functionally utilized independent of carrier body shrinkage tolerances.

Abstract: A ladder-type electric filter apparatus having at least one electric filter unit wherein each electric filter unit includes a casing into which piezoelectric resonator elements and an input, output and earth terminal plates are mounted, one or two of said terminal plates are integrally formed together with the casing, the connecting leg(s) of said terminal plate(s) integrally formed together with the casing are protruded through the wall portion opposite to the opening of the casing, and the remaining terminal plate(s) have a connecting leg(s) protruded from the opening side, all of the connecting legs being connected to a printed circuit board.

Abstract: A package for a heat generating, high voltage hybrid circuit is disclosed which comprises a package housing having a sidewall structure formed from an electrically insulative, thermally conductive ceramic material that obviates the need for using separate insulator structures between the sidewalls of the package and the electrical feedthroughs which afford electrical access to the circuit contained within the package housing. The feedthroughs include a layer of hardenable material for sealingly mounting a terminal connector through the sidewalls of the package. In one embodiment of the invention, the hardenable material sealingly mounts the terminal connectors of the electrical feedthroughs within circular openings in the sidewall structure.

Abstract: A microwave semiconductor device includes a lead frame including a die pad and pairs of ground leads formed integrally with the die pad, a microwave semiconductor element mounted on the die pad, and a signal lead disposed between and spaced by a predetermined distance from the pair of ground leads. The signal lead is coplanar with the pair of ground leads to form a coplanar high frequency transmission path.

Abstract: A capacitor structure in a hybrid multilayer circuit having a plurality of insulating layers, the capacitor structure including a dielectric via fill in a via formed in one of the insulating layers, a first conductive element overlying the dielectric via fill, and a second conductive element underlying said dielectric via fill. Each of the first and conductive elements comprises a conductive via fill or a conductive trace.

Abstract: A Demountable Tape-Automated Bonding System for providing connections to a chip is disclosed. The chip is attached to or is held in place on a TAB frame that includes a generally flexible dielectric film which bears a pattern of conductive traces. A multitude of closely-spaced contacts which protrude downward from the chip contact the conductive traces on the TAB frame. The chip may be maintained in its proper location on the TAB frame by either a bonding agent or by compressive forces supplied by a cap which is fastened to the TAB frame and to a substrate, such as a printed circuit board, below the TAB frame. The substrate carries an array of conductive traces around the edges of the substrate. These traces match the traces on the TAB frame. The conductor traces on the TAB frame and on the substrate are held in contact with each other by compressive forces supplied by the cap which is fastened to the TAB frame and to the substrate.

Abstract: An optical isolator is fabricated upon a lead frame having an LED section which is rotated 180.degree. to position the LED over the photodiode. Prior to rotation both the LED and the photodiode attachment portions (81,83) of the leads are down set a predetermined amount to fix the size of the isolation gap between the LED and the photodiode. Dielectric sheets are attached to the outer surfaces of the LED and photodiode leads and an optically transmissive resin is injected therebetween to form a light guide and to encapsulate the LED and photodiode dice and their associated bond wires. In an alternate embodiment a sheet is attached to the outer surface of one lead and a dielectric sheet thereagainst is positioned at a tilted angle between the LED and the photodiode.

Abstract: An IC mounting method and its resulting structure, such as an IC card is provided. An IC card includes a metal plate formed with at least one hole, and an IC chip is located fixed in position in the hole with a filler material filling the gap between the hole and the IC chip. An interconnect pattern is provided on the plate with an electrically insulating film sandwiched therebetween, and the interconnect pattern is in electrical contact with a contact pad of the IC chip. Preferably, the surface of the IC chip on which the contact pad is provided is substantially flush with one surface of the plate. When an electrically insulating film is fixedly attached to a substrate having a hole, in which an IC chip is fixedly provided, by an adhesive agent, the material of the film is selected to be similar to the material of the adhesive agent.

Abstract: A plurality of leads and two islands are arranged on a lead frame made of a conductive metal. Semiconductor chips, substrates of which have different thicknesses, are mounted on the two islands, and the lead frame is bent and formed such that the chip mounting surfaces of both the islands are lower than the upper surfaces of the corresponding leads by different amounts.

Abstract: A pin grid array package having a substrate formed from a ceramics containing a 90% or higher alumina composition. The substrate has an palladium-silver layer on an upper surface thereof with a silver layer further provided on the Pd-Ag layer and a gold bonding pad on a outer periphery of a cavity of the substrate so as to provide electrical connection between pins and chip. The Ag layer is covered with a dielectric layer to prevent contamination from moisture.

Abstract: The invention relates to a process for coating sintered cermet or cerglass articles with a metal or metal alloy. The process is particularly useful to eliminate pores and cavities from the surface of the article. During hermeticity testing, these pores and cavities trap tracer gas and result in an erroneous leak rate measurement. In one embodiment, the coated surfaces are subsequently coated with a second metal layer by immersion plating followed by electrolytic deposition. The process is particularly suited to the manufacture of cermet and cerglass components for semiconductor packages.

Abstract: A package for a two-switching-device half bridge circuit comprises an insulating substrate having first, second and third external power terminals along with control terminals bonded to the substrate. The power terminals are configured to provide a straight-through-the package current path from the first external power terminal to the second or common external power terminal and from the second or common external power terminal to the third external power terminal. The control terminals are preferably Kelvin terminal pairs in order to minimize feedback from the power current paths to the control circuits. The power devices are preferably bonded to the first external power terminal and the second external power terminal, respectively, with their connections respectively to the second power terminal and third power terminal substantially identical in order to provide power current paths through the package having substantially identical electrical and thermal impedances.

Abstract: Disclosed is a cover for a semiconductor chip package. The cover comprises a sealing surface for providing a seal between the cover and a semiconductor chip package. A mounting surface for mounting a capacitor to the surface of cover is provided. The mounting surface comprises metalization including a metalized power pad and a metalized ground pad for mounting at least one capacitor on the surface of the cover.

Abstract: A metal electronic package is provided having improved electromagnetic interference shielding. Metal base and cover components are electrically interconnected to remain at same voltage potential thereby reducing EMI induced mutual inductance. An electrically conductive conduit, such as a contact pin, provides interconnection. If the electronic device is mounted on a chip pad attach, the conductive conduit also connects to the support pads of the chip attach.

Abstract: A method for mounting a LSI chip (1) with conductive bumps (2, 3, 4) as terminals into a hole (15) of a card (5) and for interconnecting them. The card and therefore one end of the hole is first covered by a layer (16) of a conductive material. Then the conductive bumps of the chip placed in the hole are soldered to the layer while being pressed against this layer. Thus protrusions (17, 18, 19) are created on the external surface of the layer. These protrusions are ussed to facilitate the alignment of the mask used during the subsequent etching operation of the layer.The invention also concerns a process for creating the conductive bumps (2, 3, 4) on the terminal pads (6, 7, 8) of the LSI chip (1).