Abstract: A semiconductor device comprising a lead frame, a semiconductor chip on the lead frame, a wiring provided between the lead frame and the semiconductor chip, a silicon nitride film formed on the semiconductor chip, the wire, and the lead frame, and a mold formed from a plastic material to enclose the silicon nitride film therein and having a vent hole formed on the undersurface of the lead frame, so that the lead frame is partly exposed to the outside.

Abstract: An oscillator package includes a header substrate with a number of through holes formed therein, a copper post passed through each through hole, a ceramic substrate securely mounted to and supported by the copper posts for mounting a die and a crystal thereon, a substantially L-shaped lead securely attached to an underside as well as a lateral side of the header substrate and contacting each copper post, and a ceramic cover housing the die and crystal. A metal film is applied to an inner periphery of the hole, and the copper posts are mounted in the holes after the metal-film is sintered. An outer periphery of the copper post is plated by nickel then gold. The lead is mountable to a circuit board by soldering, and the solder covers an overall area of the lead. The ceramic cover has at least a 90% weight of aluminum oxide.

Abstract: An electronic device (10) includes a package (16) having two posts (30) suitable for insertion in PCB holes. Package (16) presents a lengthwise molding plane (32) along which the upper portion (42) and bottom portion (44) of package (16) are mated during the molding process. Posts (30) are disposed substantially exclusively in bottom portion (44) so that posts (30) are asymmetric about lengthwise molding plane (32). Thus, even if a top mold (42a) and a bottom mold (44a) are misaligned there will be no effect on the dimensional tolerance of posts (30) and thus the tolerance of post (30) can be closely matched with a PCB hole (20) tolerance to insure a snug fit. Thus, device (10) is mounted edgewise on a PCB (18) by insertion of posts (30) into PCB holes (20) so that tips (24) of lead fingers (14) can be connected to PCB (18) by surfacing-mounting techniques or the like.

Abstract: A method for assembling multilayer packages of semi-conductor elements comprising double molding of the multilayer structure. The method comprises the steps of primarily molding inner leads of a lead frame, secondarily molding the inner leads to form a desired package, and performing in turn die bonding, wire bonding, trimming and forming processes. The double molding process is performed by using an inexpensive molding compound, thereby obtaining packages having a structure equivalent to that of expensive ceramic packages. Accordingly, the manufacture cost of packages is inexpensive and the assembling process is simplified.

Abstract: An electric circuit device comprises an electric connecting member comprising a support member made of an electrically insulating material and a plurality of electrically conductive members buried in the support member and being isolated from one another. The ends of one side of the electrically conductive members are exposed at one surface of the support member, and the ends on the other side of the electrically conductive members are exposed at another surface of the support member. A first electric circuit component has connecting regions connected to the one set of ends of the electrically conductive members, and a second electric circuit component has connecting regions connected to the other set of ends of the electrically conductive members. Some of the electrically conductive members can be arranged in a zigzag pattern, and the pattern of the exposed ends of at least one electrically conductive member is wave-like or S-like.

Abstract: A lead of a lead frame cannot be made close to a very small semiconductor chip in view of processing dimensions. If a TAB technique is used to directly connect the semiconductor chip and the lead in order to improve in reliability, a device for forming a bump on an electrode of the chip is required, which increases the cost of investment in equipment. A printed circuit board is formed between the lead and bed and a bonding wire is used to shorten the length of wiring and thus to decrease in cost and improve in reliability. Since an electrode pad of the semiconductor chip, the printed circuit board, and the lead are connected to each other using the TAB techique, the productivity of semiconductor device is increased. Using the TAB technique, no bumps are formed anywhere and the cost of investment in equipment is not so increased.

Abstract: A semiconductor package includes a lead frame with a die or chip mounted on a die pad, a base made of a thermoplastic material and having a cavity, and a lid made of thermoplastic material ultrasonically welded to the base to cover the cavity and protect the electronic device in the package. The package may include a substrate with conductive traces. A method of attaching a lid to a semiconductor package base includes the steps of providing a semiconductor package base having an open cavity, providing a thermoplastic lid that covers the open cavity, placing the lid on the semiconductor package base so that the lid covers the open cavity, applying pressure to hold the lid and body together, and attaching the lid to the base by ultrasoncially welding them together.

Abstract: An improved electric device and manufacturing method for the same are described. The device is for example an IC chip clothed with moulding. In advance of the moulding process, the rear surface of lead frame of the IC chip is cleaned and coated with an antioxidation film made of silicon nitride in order to avoid the oxidation of the lead frame. The antioxidation film ensures the connection of the moulding and the lead frame and protect the IC chip from moisture invaded through cracks or gaps. The coating of silicon nitride is carried out after cleaning the lead frame.

Abstract: A method for simultaneously manufacturing metallized carriers from wafer-shaped substrates is described, wherein such wafer-shaped substrates permit the use of standard IC fabrication apparatus and methods. As a result, very thin and finely dimensioned traces can be deposited. Thin-film manufacturing techniques are used to create the high-density traces on the surface of the chip carriers, thereby permitting direct connections from the IC to the periphery of the carrier without the need for vias. A lid hermetically seals and protects the package. The traces are comprised of a plurality of metals to facilitate bonding, each of the metals homogeneous for a portion of the trace. One metal portion of the trace is of a type compatible with an IC chip placed in the carrier. Another metal portion of the trace is of a type compatible with a trace on a printed circuit board. A metal barrier is interposed between the metals to prevent metal diffusion from one metal to an adjoining portion of another metal.

Abstract: An induction heating module encapsulation apparatus and method for its use is disclosed. The apparatus comprises a substantially airtight chamber which is composed of ceramic or some other high temperature insulating material in which a cap and a ceramic substrate having semiconductor chips joined thereon are placed. A sealband of solder or other brazing material is placed at the periphery of the cap where the cap end substrate are to be joined. An RF coil, which serves as inductor in the apparatus, is energized by a high frequency generator, generating an electromagnetic field in the radio frequency spectrum. The RF coil is oriented to localize the inducted current at the periphery of the cap and the sealband. The inducted current is dissipated in the form of heat until the sealband is molten. The RF power is then turned off.

Abstract: A chip carrier socket comprises a one piece insulating housing with a rectangular frame-like body portion surrounding a rectangular base-plate. Rows of contacts are force-fitted in cavities in the body portion with contact spring portions extending inwardly for electrical connection to leads on respective sides of a chip carrier inserted in the socket and with rows of soldering tabs extending inwardly at the circuit board engaging face for reflow soldering to pads of the circuit board. The base-plate is supported on the body portion with respective perimetrical edges thereof located spaced apart from the respective adjacent sides of the body portion, defining therewith apertures aligned over the respective rows of solder tabs, by bridge portions which extend between respective corners of the base-plate and adjacent respective corners of the frame-like body portion without obstruction of the field of view along the apertures.

Abstract: A lead wire array for a leadless chip carrier which functions to mount and electrically interconnect a leadless chip carrier to a printed wiring board. The array is formed from a length of bare wire which is appropriately folded and bent to provide interconnections between the contact pads on the leadless chip carrier and contact pads on the printed wiring board, which are then separated by removing portions of the lead wire array after its attachment to the leadless chip carrier.

Abstract: A hermetically sealed package for one or more integrated circuit chips that is made of three metal, thick-film layers, and one dielectric, thick-film layer to form a mounting surface for the chip. The first applied metal layer includes the power plane, and the fan-out leads including power and ground leads. The dielectric layer overlays the power plane and includes an annular rectangle overlaying a portion of all the leads of the first layer and an outer boundary strip overlaying extreme ends of the leads. The second screened metallic layer serves as the ground plane, and electrically engages the ground leads of the first metallic layer and the extreme outer ends of the signal leads.

Abstract: A CMOS integrated circuit assembly for providing reduced power supply and ground inductances has a first conducting layer which is formed over an insulating layer formed on top of the integrated-circuit chip. The first conducting layer is connected to wire bond pads which are wirebonded to a package. This first conducting layer forms a single, low-inductance conductor for a VDD supply voltage and extends over a substantial area so that it has an inductance significantly less than the inductance of a conventional conductor. A second conducting layer is forms a low-inductance VSS conductor. Power can be selectively distributed through conductive layers of this to provide power supply isolation between selected circuits of the integrated circuit.

Abstract: A soldering connector and a method for manufacturing an electric circuit with this soldering connector. The soldering connector serves to bridge several contact surfaces. The soldering connector includes several soldering jumpers which include a common support and are of an electrically conductive material and are formed in a single piece with the support and are constructed in a cantilevering manner. Predetermined breaking points are provided between the support and the soldering jumpers, so that the common support can be severed after the soldering procedure by simply tearing it off from the soldering jumper.

Abstract: A stackable surface mount electronic component assembly 100 allowing for the stacking of electronic components 108, and 112 is disclosed. The stackable surface mount electronic component assembly 100 includes electronic component carriers 102, and 114, each having an electronic component 108, and 112 respectively. The two carriers 102, and 114, are electrically interconnected by the use of solder balls 106. Electronic component carrier 114 is in turn attached to an external printed circuit board by the use of solder balls 110. Optionally, each of the electronic components 108, 112 can be encapsulated using encapsulation material prior to the joining of the two carriers 102, and 114. In an alternate embodiment recesses 302 are located on top of the elevated peripheral edge 116 allowing for the proper alignment of the two carriers 102, and 114.

Abstract: A low-inductance package for multiple paralleled devices includes an electrically insulating substrate having three power terminals direct-bonded to the upper surface thereof and a conductive pad direct-bonded to the lower surface thereof for connection to a heat sink. Two groups of multiple parallel-coupled devices are each soldered to one of the three power terminals and are further connected in a half-bridge configuration such that one of the three power terminals is common to both groups of devices. The package further includes a pair of first Kelvin terminals, i.e., a first Kelvin control terminal and a first Kelvin source terminal, and a pair of second Kelvin terminals, i.e., a second Kelvin control terminal and a second Kelvin source terminal. The Kelvin terminals are soldered to the appropriate power terminals, depending upon the particular circuit configuration.

Abstract: A package is provided for connecting a plurality of molded carriers each having an integrated circuit which has been previously bonded to the electrical leads of a TAB tape. The package flexibly and sequentially connects a plurality of the carriers, so as to form a flexible and continuous chain of the carriers. The package preferably utilizes a flexible conductive tape which is continuously provided on parallel ends, or edges, of each carrier, so as to link the plurality of carriers together. The package permits continuous feeding of the carriers into subsequent test and assembly machines utilized to attach the integrated circuit to a printed circuit board.

Abstract: Disclosed is a container package for a semiconductor element, which comprises a vessel having in the interior thereof a space for containing a semiconductor element, which comprises an insulating substrate and a lid member, an external lead terminal for connecting the semiconductor element contained in the vessel to an electric circuit and a sealing agent for sealing the vessel and external lead terminal, wherein the external lead terminal is composed of an electroconductive material having a thermal expansion coefficient of from 5.times.10.sup.-6 to 12.times.10.sup.-6 /.degree.C. and an electroconductivity of at least 10% (International Annealed Copper Standard).

Abstract: A radial lead type electronic component includes a couple of plate-type lead terminals projecting from a protective resin member in the same direction. These lead terminals are provided with inclined edges, which make the body portions gradually narrowed toward leg portions, in leg-side edges of body portions. Among inclined edges, inclinations .theta..sub.1 of the outer ones with respect to the leg-projecting direction are greater than inclinations .theta..sub.2 of the inner ones with respect to the same direction. Thus, the electronic component is relieved from stresses which are applied thereto upon insertion in a printed circuit board or a cut-and-clinch operation.

Abstract: A hermetic semiconductor package includes a ceramic lid with the device leads extending vertically through the lid. The leads are mechanically retained within the apertures in the lid and direct bonded to the lid to provide a hermetic seal and a substantial lead density.

Abstract: A transformer winding form includes an insertion-type leader frame which is attached to the transformer winding form during the process of molding the winding form. The leader frame can be produced in a T-shaped or L-shaped configuration for attachment at the proper position on the transformer winding form. Due to a the lower curved section in the T-shaped leader frame, the thus equipped transformer winding form can be soldered firmly to a PC board, while also having horizontal side terminals which facilitates other connections to the transformer winding form. The horizontal side terminals of the T-shaped configuration also conform to the special layout holes of a PC board, as a result of which the overall height of the transformer winding form is also decreased. In the L-shaped leader frame, the lower vertical terminals underneath can also be inserted into the holes of a PC board and thereby comply with the requirements of large-volume output automatic soldering machines.

Abstract: A small, lightweight, efficient, very low cost AC adaptor for consumer electronics applications is realized by combining a switching regulator integrated circuit along with a leadframe adapted to mount the switching regulator integrated circuit off-center, a single-sided printed circuit board and high frequency ferrite cores. These components are assembled onto a substrate, such as a printed circuit board, by means of well-known, low-cost automatic insertion assembly machines. The novel structural aspects result in formation of a transformer from the leadframe and traces on the printed circuit board. The power supply resulting from this assembly method may be small enough to be molded into the plug portion of a standard AC power cord.

Abstract: A package for containing an integrated circuit component is provided which includes one or more layers with exposed edges surrounding a central opening. The integrated circuit component is positioned in the central opening. Bond wires connect the bond pads of the integrated circuit component to the continuous shelves of the various stepped-back stadium-like layers as well as to individual insulated leads. The layers are spaced apart by beads or columns of insulative material and the major portion of the layers are separated from each other by a gaseous dielectric, preferably air. The R-C constant is reduced and the speed of transmission is increased by the presence of the low dielectric material providing a device which can function rapidly. The stepped portions of the layers are exposed to allow for electrical interconnections within the layers, as well as from each layer to the integrated circuit.

Abstract: A hermetically sealed surface mount electronic component package can be manufactured by converting standard, readily available flat-packs. The package has a base, with an opening through which a primary transmission lead extends, a glass-to-metal seal surrounding the transmission lead in the opening, and a secondary transmission lead extends from the primary transmission lead so that it is spaced from the base and its end is at least flush with the bottom of the base. An insulator can be provided between the primary transmission lead and the secondary transmission lead. A method of converting a standard flat-pack by providing a composite piece having a dielectric insulator, a secondary transmission lead for connection to the transmission lead of the flat-pack, and a connecting member for connecting the insulator and secondary transmission lead to the base of the flat-pack is also described.

Abstract: The present invention relates to a semiconductor package which is loaded with a plurality of high-performance integrated circuits for high-performance systems such as super computers and large-sized computers. According to the invention, the packaging density of the semiconductor is doubled by stacking upper and lower members and forming substrates loaded with a plurality of chips in a multistep structure so that the size of computers can be minimized and heat emission efficiency can be improved by forming heat sinks in a fin-pin shape.

Abstract: A semiconductor device having both bottom-side contacts and peripheral contacts provides surface mounting options. In one form, a semiconductor device die is positioned at a die receiving area of a leadframe. The leadframe also has a plurality of leads, each lead having a first and a second contact portion which are separated by an intermediate portion. A package body encapsulates the semiconductor device die and intermediate portions of the plurality of leads. The first contact portions of the leads are partially exposed on the bottom surface of the package body. The second contact portions extend from the package body along a portion of the package body perimeter. The first contact portions provide bottom-side contacts to the device, while the second contact portions provide peripheral contacts. The second contact portions are shaped into a desired lead configuration or are severed to establish a leadless device.

Abstract: A semiconductor device comprising a semiconductor unit with leads extending therefrom is placed on a bottom packaging tray having a die-shaped upper surface. A top lubricating type film is used over the device 10 and below a punch unit that is used to bend the leads. A process of assembling the semiconductor device on a die type package is disclosed which includes placing the semiconductor device with leads on a packaging tray with upper lead-shaped baring surfaces, placing an anti-friction film sheet over the tray and over the device with its leads extending therefrom, and actuating a punch unit disposed above the film sheet, thereby forming or bending the leads and simultaneously using the die type tray for packaging the semiconductor device.

Abstract: The degree of wire sweep and wire clearance over the buss bars in the 16 Mega Bit LOC package is found to be dependent on the angle of the bond wires. A positive wire angle range of 5 to 15 degrees is recommended for minimum wire sweep and maximum wire clearance over the buss bars. This is so because they offer the least resistance to the flow of the mold compound during transfer molding. A staggered gating system ensures that the wire angles in all cavities are positive with respect to the gate. This invention is also applicable to conventional packages.

Abstract: A molded heat sink for plastic packages constructed for housing semi-conductor devices. Heat is removed from the semiconductor device by direct heat transfer from the device through upstanding members integrally molded in the top of the plastic housing. The integrally molded heat dissipation members facilitate cooling of the semi-conductor die which is not available by normal dissipation by convection and radiation through a generally planar external surface of the package. The molded members permit effective heat dissipation without the thermal coefficient of expansion mismatch which may occur between conventional molded packages and heat sinks secured thereto.

Abstract: The present invention relates to a packagae adapted to house an electronic device, such as a semiconductor integrated circuit. The package components are comprised of aluminum based alloy. At least a portion of the surfaces of the package components are anodized to enhance corrosion resistance and increase bond strength. The aluminum based packages are characterized by lighter weight than cooper based packages and better thermal conductivity than plastic based packages.

Abstract: A shielded low-profile electronic component assembly 100 providing shielding for electronic components is disclosed which includes a substrate 124, and shield 102. In a first embodiment the shield 102 is chamfered at each shield corner 110 and is attached to the substrate 124 at ground pad patterns 114, which are found at each corner of the substrate 124 on surface 128. A ground paddle 120 is also located in substrate 124 which lies substantially underneath the electronic component 112, and is utilized in maximizing shielding. In an alternate embodiment a substrate 124 is overmolded with encapsulation material 302 after the electronic component 112 is affixed to the substrate 124, with each of the encapsulation material corners 306 being chamfered exposing ground pads 114. The metallized shield 310 is then placed over the overmolded encapsulant and attached to the substrate 124 at ground pad patterns 114. The overmolded encapsulant 302 adding protection to the electronic component 112.

Abstract: A plastic package that includes a cavity for holding an integrated circuit die. The package also includes several singel-piece leads that each have bonding pad area on one end and an area for connecting to external circuitry on the other end. The package's plastic body supports the leads, separates them from each other, and includes a ridge that substantially encircles the cavity and separates the bonding pad areas from the cavity. The package may be made by forming a first portion including alignment protrusions sized to receive lead bonding pad ends, placing the leads with their bonding pads so that they are spaced apart by the protrusions, and securing them, preferably by supplying heat to the protrusions. A second portion of the package may then be molded around the first portion, the leads, and, preferably, a heat sink.

Abstract: A structure and method are disclosed for tape automated bonding (TAB) assembly processes which provide for reduced manufacturing costs, greater film strength, and greater usable film area so that larger chips can be accommodated on a given size film. Common lines, which prevent the buildup of voltage differences between leads, are cut away before electrical testing by means of a knife that slices away the common line conductors parallel to the film surface rather than punching through the conductive leads attached to the common lines and underlying film. By eliminating the punch-outs more room is made available for large chips, film strength is not reduced because of multiple punch-outs, and manufacturing costs are reduced because product-specific punching tools are no longer required.

Abstract: This is a semiconductor chip in which the conductive path between the chip and the lead frame via wires can be easily and reproduceably improved. This is accomplished by improving the bond between the wires and the lead frame members to which the wires are joined and by creating additional contacts between each wire and its respective lead even if the bonded contact breaks or fails at or immediately adjacent to the bonding point. This is accomplished by placing an insulating layer on the active surface of each chip, carrying input and output bonding pads thereon, to which lead frame conductors have been connected by bonding wires.

Abstract: A lead frame cutting apparatus for various sized integrated circuit packages and method therefor is disclosed. This apparatus employs punches in conjunction with a thin L-shaped cutting plate, which is also symmetrical, allowing both sides to be used. This thin cutting plate is fabricated as one of a plurality of thin cutting plates using a relatively inexpensive single cutting process that cuts all the thin cutting plates in one cutting operation thereby saving money and time compared to the machined, thick cutting plate of the prior art. The L-shape of the cutting plate and the use of the associated punches allows integrated circuit packages of different sizes to be processed with the apparatus of the present invention using a two-pass approach. The integrated circuit package is positioned correctly on the L-shaped cutting plate, and the punches perform the cutting function on two of the four sides of the lead frame.

Abstract: A Demountable Tape-Automated Bonding System for providing connections to a chip is disclosed. The chip is attached to or is held in place on a TAB frame that includes a generally flexible dielectric film which bears a pattern of conductive traces. A multitude of closely-spaced contacts which protrude downward from the chip contact the conductive traces on the TAB frame. The chip may be maintained in its proper location on the TAB frame by either a bonding agent or by compressive forces supplied by a cap which is fastened to the TAB frame and to a substrate, such as a printed circuit board, below the TAB frame. The substrate carries an array of conductive traces around the edges of the substrate. These traces match the traces on the TAB frame. The conductor traces on the TAB frame and on the substrate are held in contact with each other by compressive forces supplied by the cap which is fastened to the TAB frame and to the substrate.

Abstract: Disclosed is a container package for a semiconductor element, which comprises a vessel having in the interior thereof a space for containing a semiconductor element, which comprises an insulating substrate and a lid member, an external lead terminal for connecting the semiconductor element contained in the vessel to an electric circuit and a sealing agent for sealing the vessel and external lead terminal, wherein the external lead terminal is composed of an electroconductive material having a permeability lower than 210 (CGS) and a thermal expansion coefficient of from 9.times.10.sup.-6 to 12.times.10.sup.-6 /.degree.C.

Abstract: An improved housing for an electronic device such as a small-sized portable communication device, comprising a case, a main cover and a sub cover, in which one portion of an opening of the case is covered with the main cover by engaging the main cover with the case and fixedly securing a screw portion of the main cover with the case by a screw, while the other portion of the opening of the case is covered with the sub cover by engaging the sub cover with the case and by engaging the sub cover with the main cover via elastic engaging portions provided in the sub cover thereby to cover the screw with the sub cover. According to this engagement, since the opening of the case is covered with the main cover and the sub cover, and the screw is entirely covered with the case, the screw is not exposed to the exterior of the housing so that the appearance of the housing can substantially be improved and undesirable introduction of electrostatics into the interior of the housing can be prevented reliably.

Abstract: A method of forming enclosures for microwave and hybrid devices and the enclosure itself wherein the metals to be joined are thin (i.e., less than 40 mils thick) and/or thick (up to several inches) and wherein metallurgical hermetic bonds are provided between adjacent metals which are generally difficult to bond to each other and may be bonded by a select number of bonding processes.

Abstract: An integrated circuit package and method of making the package which allows an integrated circuit die to be bonded to a substrate without need of a carrier. The integrated circuit die has opposed active and passive surfaces and has lateral surfaces. An electrically insulative layer of material is deposited on the passive and lateral surfaces. A metal mask is formed to cover the active surface and the coated lateral surfaces. The metal mask includes slots which extend up the lateral surfaces and onto the active surface. The array of slots corresponds to an array of input/output contact pads on the active side. Metal is sputtered into the slots, whereafter the mask is removed to provide L-shaped conductive traces from the contact pads along the active and lateral sides. The assembly can then be rested on a substrate on the passive surface and the L-shaped traces bonded to contact pads on the substrate. The assembly allows testing at the die level.

Abstract: A logic module design is disclosed which incorporates an unencapsulated wafer section or sections. The disclosed module is an improvement over previous designs in that it is less expensive and easier to manufacture due to the reduced number of components and the complexity of the components, is faster and consumes less power because of its shorter trace lengths and smaller size, and is more reliable as a result of its greatly reduced number of interconnects.

Abstract: A partially coated assembly structure and a method for making a ceramic lid for a hermetically sealed package for an EPROM circuit are disclosed. The assembly structure includes, in combination, a ceramic lid, a UV transparent lens, and two fixtures for supporting the lens in the lid. The two fixtures are coated with a non-lens wetting film in predetermined areas where contact is made between the fixtures and the lens, and between the fixtures and the lid. The UV transparent lens is hermetically sealed to the ceramic lid by firing the assembly structure. The assembly structure prevents the lens from attracting foreign particulate matter during firing, thereby leaving the surfaces of the lens clean. The method provides a ceramic lid having a UV transparent lens hermetically sealed thereto, which finds wide use in integrated circuit packages for high-density EPROM's because of the untainted surfaces of the lens.

Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Abstract: A surface mount leaded chip connector plug for mating with a standard leaded chip connector socket is described. The plug includes an insulator having an outer circumference and a depth, and a multiplicity of electrical contacts disposed about the outer circumference. Each of the electrical contacts has a body and two arms. The body has a back side, a midline and two ends, and slopes inwardly from the ends toward the midline such that the body slidably locks with the leaded chip connector socket. One of the arms adjoins one of the body ends and the other of the arms adjoins the other of the body ends. Each of the arms extends toward the back side. The arms are separated by a distance greater than the insulator depth such that the electrical contact may be securely disposed about the insulator.

Abstract: A ceramic chip carrier package for integrated circuits is described which provides reduced interlead capacitance. A cavity for the placement of the integrated circuit chip is centrally located on a substrate. The leads of the package are bridged between the cavity and the outer periphery of the substrate. The leads are bonded to the substrate using adhesive glass placed on the substrate at the outer periphery of the cavity and at the outer periphery of the substrate. Sealing glass is placed on the outer periphery of the substrate over the leads to provide a bonding material for a lid to the package. The area between the cavity and the outer periphery of the substrate has no adhesive or sealing glass which thus provides an air dielectric between the leads so that interlead capacitance is reduced.

Abstract: A process for preparation of electronic packages including printed circuits wherein the circuit portions of the package are formed from a web including a plurality of circuits maintained in an array during processing. Holding tabs are provided to maintain the integrity of the array, with the holding tabs being in the form of releasable retention tabs for temporarily holding the array together and accommodating multiple-up processing of the electronic package. For certain portions of the process, the web is separated into multiple-up circuit packages wherein the circuits are disposed within the central portion of the panel, and with the lateral edges and ends collectively defining an annular circuit-free zone. Multiple fiducial points are located within or around the circuit patterns, thereby eliminating or reducing the requirement for circuit-specific tooling and permitting multiple-up handling of the circuits in each array.

Abstract: A ceramic-glass integrated circuit package utilizing low temperature sealing glass and having reduced lead to lead capacitance. The inventive package includes a cap and a base. The base includes a ceramic base substrate, a first layer of conductive material adjacent the ceramic base substrate to serve as a ground plane, and a second layer of conductive material adjacent the ceramic base to serve as a power plane. A glass material is selectively deposited on the base substrate to form at least one discrete void for housing an integrated circuit chip, and a lead frame having a plurality of leads is embedded in the glass material and electrically connected to the ground and power planes but physically separated therefrom. In one embodiment, integral decoupling capacitors are further included on the base substrate. Incorporation of ground and power planes and decoupling capacitors into a ceramic-glass integrated circuit package adapts these low cost packages to high-speed applications.

Abstract: A transport medium for orderly, in-process transportation of assembled electrical devices during backend processing. A carrier tray is comprised of a plurality of carrier units held in coplanar relationship by a frame. Preferably the carrier units are polyethersulfone inserts latchable into a coordinate matrix of carrier unit holes defined by a metallic sheet. Each carrier unit carries one or more electrical devices in device seats which expose a top and a bottom of each device sufficiently to eliminate any necessity for removing the devices from the medium during all backend processing. Each carrier unit has a standardized perimeter but a core which is adapted to a particular device size and form, and there can be as many different carrier units as there are different device forms and sizes, but all carrier units fit into a standard carrier unit hole. The frames and carrier units are robotically manipulable.

Abstract: In a photoelectric converter module, a chip carrier which carries a photoelectric converter chip on a side surface thereof is fixed on a metal base of the module via a metal member by means of welding, and the photoelectric converter chip is connected electrically with a pre-amplifier via a conductor pattern provided on a surface of the chip carrier and a bonding wire, so that parasitic capacities generated between the photoelectric converter chip and the pre-amplifier are considerably reduced, and the chip carrier is fixed firmly without causing deviation of an optical axis between the photoelectric converter chip and optical systems including a lens.