Plural Layers Patents (Class 174/524)
  • Patent number: 5460319
    Abstract: A lead for achieving solder joining with great vibration strength includes an upper lead portion having a clip and a lower lead portion having a thin tip for insertion into an electrode in a lower substrate and an oblong through hole in the body of the lower lead portion for inducing capillarity of soldering flux.
    Type: Grant
    Filed: June 22, 1993
    Date of Patent: October 24, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hazime Kato
  • Patent number: 5461197
    Abstract: Since an electronic device comprises an electronic component, an external connection terminal electrically connected to the electronic component, and an envelope for sealing the electronic part and having a thickness less than about 0.5 mm, the electronic device is miniaturized even in the case where it is provided with a large number of terminals. Further, since the electronic component is sealed by the envelope, moisture, etc. is not admitted into the electronic component, resulting in high reliability. In addition, since the thickness of the envelope is thin, the external terminal can be shortened. Thus, the inductance or capacitance of this terminal can be reduced.
    Type: Grant
    Filed: June 17, 1994
    Date of Patent: October 24, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoichi Hiruta, Yasuhiro Yamaji
  • Patent number: 5461196
    Abstract: A unitized integrally fused multilayer circuit package having a substrate, walls disposed on the substrate to form a central circuit package cavity, and circuit traces contained in the walls.
    Type: Grant
    Filed: December 2, 1992
    Date of Patent: October 24, 1995
    Assignee: Hughes Aircraft Company
    Inventors: Kathleen Virga, Terry Cisco, Joseph N. Owens, Craig Shoda
  • Patent number: 5455385
    Abstract: A packaging assembly for a semiconductor circuit chip is formed of a hermetically sealable, `tub`-like structure. The tub-like structure is comprised a laminated stack of thin layers of low temperature co-fired ceramic (LTCC) material. The laminated stack of LTCC layers contains an internally distributed network of interconnect links through which a semiconductor die, that has been mounted at a floor portion of the tub, may be electrically connected to a plurality of conductive recesses or pockets located at top and bottom sidewall edge portions of the tub, thereby allowing multiple tubs to be joined together as a hermetically sealed assembly and electrically interconnected at the conductive pockets of adjacent tubs.
    Type: Grant
    Filed: June 28, 1993
    Date of Patent: October 3, 1995
    Assignee: Harris Corporation
    Inventors: Charles M. Newton, Edward G. Palmer, Albert Sanchez, Christopher A. Myers
  • Patent number: 5455386
    Abstract: There is disclosed an adhesively sealed electronic package in which a compensation apparatus is provided for excess adhesive. As a result, excess adhesive does not extend beyond the package perimeter, squeeze-out, or travel along the inner lead fingers interfering with wire bonding. The compensation is a chamfer on the peripheral edges and/or interior edges of the package base component and cover component.
    Type: Grant
    Filed: January 14, 1994
    Date of Patent: October 3, 1995
    Assignee: Olin Corporation
    Inventors: George A. Brathwaite, German J. Ramirez, Michael A. Holmes, Paul R. Hoffman, Dexin Liang
  • Patent number: 5455745
    Abstract: A transfer molded high lead count plastic semiconductor package is described. The packaged IC chip is mounted upon a suitable leadframe and the bonding pads wire bonded to the leadframe fingers. To avoid wire shorting, due to wire sweep during transfer molding, the wires are first coated with an insulative material.
    Type: Grant
    Filed: July 26, 1993
    Date of Patent: October 3, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Peter M. Weiler, Thomas S. Burke
  • Patent number: 5455387
    Abstract: An electronic package with a semiconductor chip, a lead frame, a metal casing, and a redistribution interposer. The chip is mounted on the interposer and wirebonded to first ends of redistribution leads of the interposer. The redistribution leads have second ends orientated in a general flipped orientation relative to their corresponding first ends. The second ends are wirebonded to pads of the lead frame. The interposer allows smaller chips to be used in the package without changing the lead frame. The interposer also allows the chip to be flip-mounted in the package without changing the lead frame or casing, this allows redirection of the chip's thermal path.
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: October 3, 1995
    Assignees: Olin Corporation, Cyrix Corporation, International Business Machines Corporation
    Inventors: Paul R. Hoffman, Keshav B. Prasad, Thomas Caulfield, Sean T. Crowley
  • Patent number: 5451716
    Abstract: An electronic component is provided which comprises a resin package for enclosing inside parts, and at least one lead terminal projecting out from the resin package to have a bonding end. The lead terminal is bent to provide an armpit-like portion between the lead terminal and the resin package for retaining a solder wire in a sandwiched state. At the time of mounting the electronic component to a circuit board, the solder wire be caused to melt at a soldering temperature for merging with solder fillets along the bonding end of the lead terminal.
    Type: Grant
    Filed: September 9, 1994
    Date of Patent: September 19, 1995
    Assignee: Rohm Co., Ltd.
    Inventors: Miki Hasegawa, Yasuo Kanetake
  • Patent number: 5451715
    Abstract: A packaged integrated circuit and method of manufacturing the same is disclosed. The semiconductor integrated circuit chip is mounted and bonded to a lead frame in the conventional fashion, and an inner molded body is formed therearound. The leads of the lead frame have inner and outer dambars, with the inner dambars located so as to prevent bleedout of mold compound during the molding of the inner body. Upon removal of the inner dambars, two tie bars become floating and are then formed to extend above the inner molded body so as to make contact to an electrochemical cell that is attached to the inner molded body. An outer body is then molded to surround the inner molded body and the cell, with the outer dambars located so as to prevent bleedout of mold compound. Removal of the outer dambars and formation of the leads into the desired shape completes the assembly of the packaged integrated circuit.
    Type: Grant
    Filed: August 11, 1993
    Date of Patent: September 19, 1995
    Assignee: SGS-Thomson Microelectronics, Inc.
    Inventors: Michael J. Hundt, Krishnan Kelappan, Harry M. Siegel
  • Patent number: 5446246
    Abstract: A semiconductor ceramic packaging substrate has the usual vias of sintered electrically conductive metal extending through the substrate. There are the usual metal conductor lines comprising conductive elements on the surface of the substrate. Each via is connected to the conductive elements in a predetermined pattern through a conductive via cap on the surface of the ceramic package. The caps join each conductive element and each via. The cap has a width substantially larger than the diameter of the via at the point of contact of the via and the conductive element in contact with it. The caps are also substantially thicker and wider than the conductive elements.
    Type: Grant
    Filed: January 24, 1994
    Date of Patent: August 29, 1995
    Assignee: International Business Machines Corporation
    Inventors: Kamalesh S. Desai, Donald W. DiAngelo
  • Patent number: 5444602
    Abstract: An electronic package which has a heat sink that is attached to the lead frame of the package with a material that is both electrically and thermally conductive. The lead frame is also coupled to a first surface of an integrated circuit die with tape automated bonded (TAB) leads. The low thermal resistance of the heat sink increases the thermal performance of the package. The heat sink may also be mounted directly to the die with a conductive material so that the die is electrically grounded to the heat sink. The heat sink is then bonded to the leads of the lead frame that are dedicated to ground. In this embodiment, the heat sink provides the dual functions of a ground plate and a heat spreader.
    Type: Grant
    Filed: February 25, 1994
    Date of Patent: August 22, 1995
    Assignee: Intel Corporation
    Inventors: Koushik Banerjee, Siva Natarajan, Debendra Mallik, Praveen Jain
  • Patent number: 5442134
    Abstract: Disclosed is a semiconductor device such as a DIP (Dual In-line Package) or PGA (Pin Grid Alley), which has a plurality of leads protruding only from one surface of a flat package. A single independent lead protrudes from the surface of the package at the position which is aligned with a guide hole formed in the package. The independent lead has a bore which penetrates through the lead lengthwise and connects to the guide hole. A wiring member of an electronic part or the like placed in the bore via the guide hole is soldered to the inner wall of the independent terminal.
    Type: Grant
    Filed: December 1, 1994
    Date of Patent: August 15, 1995
    Assignees: Kabushiki Kaisha Toyoda Jidoshokki Seisakusho, Toyota Jidosha Kabushiki Kaisha, Kyocera Corporation
    Inventors: Yukiyasu Miyazaki, Nobuyoshi Sugitani, Yoshiaki Shimojo
  • Patent number: 5440451
    Abstract: A memory assembly, comprises a wiring board having wiring patterns, the wiring patterns having a plurality of electrodes, each of the wiring patterns having a connecting terminal formed on a single main surface of the wiring board, a memory device mounted to the wiring board and having a plurality of electrodes connected to the electrodes of the wiring patterns, and an electrical insulator mounted to the main surface of the wiring board and having a shape to expose the connecting terminal to the atmosphere. The insulator insulates the wiring patterns, the electrodes of the wiring patterns and the connecting terminal from possible electrical charges on a surface of the memory assembly to protect the memory device from being electrically charged and discharged. Even if the exterior surface of the memory assembly is charged with possible static electricity, the interior of the memory assembly is protected from being electrically charged and discharged.
    Type: Grant
    Filed: December 8, 1993
    Date of Patent: August 8, 1995
    Assignee: Casio Computer Co., Ltd.
    Inventors: Hirokazu Saito, Takeshi Iijima
  • Patent number: 5437095
    Abstract: A method of making an integrated circuit package is disclosed herein along with the package itself, which package is encapsulated by plastic that is caused to flow in a given direction during the package's formation. The package itself includes an IC chip having an army of chip output/input terminals, and means for supporting the chip including an array of electrically conductive leads, all of which are provided for connection with the output/input terminals of the IC chip. In addition, the overall package includes bonding wires connecting the chip output/input terminals with respective ones of the leads such that each bonding wire extends in a direction that defines an acute angle of less than 45 degrees with the given flow direction of the plastic material used to encapsulate the IC chip, support means and bonding wires. In a preferred embodiment, at least a portion and most preferably substantially all of the bonding wires are substantially parallel with the given flow direction of the plastic material.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: August 1, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Luu T. Nguyen, Hem P. Takiar
  • Patent number: 5438305
    Abstract: A high frequency module is disclosed which comprises a high frequency device in a package, a circuit formed on a flexible substrate in the package, the circuit, the high frequency device and input/output terminals of the package being connected electrically.
    Type: Grant
    Filed: August 3, 1992
    Date of Patent: August 1, 1995
    Assignees: Hitachi, Ltd., Hitachi Denshi Kabushiki Kaisha, Hitachi Video & Information System, Inc.
    Inventors: Mitsutaka Hikita, Atsushi Sumioka, Takatoshi Akagi, Toyoji Tabuchi, Nobuhiko Shibagaki
  • Patent number: 5438222
    Abstract: A miniaturized electronic device and a manufacturing method for the same is disclosed. Solder is provided on pads provided on leads and corresponding pads provided on an electronic part chip of the electronic device are placed on the solder. The solder is radiated with infrared rays and thereby melted. Then connecting parts are completed. This electronic device does not have a die and wires for bonding. Therefore, it is more miniaturized than a conventional electronic device.
    Type: Grant
    Filed: March 8, 1993
    Date of Patent: August 1, 1995
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 5436407
    Abstract: An improved metal semiconductor package is described. The semiconductor package includes a lead frame with a top side and a bottom side. A semiconductor is positioned on the top side of the lead frame. Bond wires electrically couple the lead frame to the semiconductor die. A metallic base is positioned at the bottom side of the lead frame. A metallic cap is positioned over the top side of the lead frame. The metallic cap includes a central aperture that is aligned with the semiconductor die. An external plastic seal is used to join the metallic base, lead frame, and metallic cap. The external plastic seal may be in the form of a perimeter seal or a body seal.
    Type: Grant
    Filed: June 13, 1994
    Date of Patent: July 25, 1995
    Assignee: Integrated Packaging Assembly Corporation
    Inventors: Gerald K. Fehr, Victor Batinovich
  • Patent number: 5435058
    Abstract: A method of forming enclosures for microwave and hybrid devices and the enclosure itself wherein the metals to be joined are thin (i.e., less than 40 mils thick) and/or thick (up to several inches) and wherein metallurgical hermetic bonds are provided between adjacent metals which are generally difficult to bond to each other and may be bonded by a select number of bonding processes.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Henry F. Breit, Premkumar R. Hingorany, John A. Haug
  • Patent number: 5434358
    Abstract: A ceramic feedthrough for a package for an electronic device provides a plurality of electrical connections through an opening in the package. A method of making the feedthrough and of packaging the electronic device includes electrically conductive paths that are formed from a metal paste applied between green sheets that are joined and cofired to form a ceramic body. Vias extend from an exterior surface of the ceramic body to the paths to complete the electrical connection from outside the package to inside the package. A density of 50 paths per inch or greater may be achieved. The ceramic body may be hermetically sealed into an opening in the package and the body may have a peripheral extension to facilitate attachment of the feedthrough to the package.
    Type: Grant
    Filed: December 13, 1993
    Date of Patent: July 18, 1995
    Assignee: E-Systems, Inc.
    Inventors: Timothy J. Glahn, Mark J. Montesano
  • Patent number: 5434745
    Abstract: Disclosed is a stacked die carrier assembly and method for packaging and interconnecting silicon chips such as memory chips. The carrier is constructed from a metalized substrate onto which the chip is attached. The chip is wire bonded to the conductor pattern on the substrate. Each conductor then is routed to the edge of the substrate where it is connected to a half-circle of a metalized through hole. A frame is attached on top of this substrate. This frame has also a pattern of half-circle metalized through holes that aligns with the holes on the bottom substrate. The combination of the bottom substrate with the silicon die, and the frame on top, forms a basic stackable unit. Several such units can be stacked and attached on top of each other. The top unit can finally be covered with a ceramic lid that also has a matching half-circle metalized through hole pattern along its edge.
    Type: Grant
    Filed: July 26, 1994
    Date of Patent: July 18, 1995
    Assignee: White Microelectronics Div. of Bowmar Instrument Corp.
    Inventors: Hamid Shokrgozar, Leonard Reeves, Bjarne Heggli
  • Patent number: 5430250
    Abstract: Single, continuous bonding wires for an integrated-circuit die are supported in mid-span by a support ring which is snap-fit or adhesively bonded to a die-attach paddle of a leadframe. The support member includes a groove formed in its distal end for receiving an adhesive material, if necessary, for securing the bonding wires in position to prevent wire-wash and electrically shorting of the bonding wires when a plastic molding compound is formed around the die and leadframe. Alternatively the bonding wires are contained within notches formed in the distal end of the support ring. A lid placed over the support ring provides an enclosure for the integrated-circuit die. Stacking of support rings on each other and concentric support rings provide various optional arrangements for supporting bonding wires.
    Type: Grant
    Filed: April 8, 1994
    Date of Patent: July 4, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon
  • Patent number: 5426263
    Abstract: An electronic assembly has a double-sided leadless component (10) and one or more printed circuit boards (30, 32). The component has a plurality of electrical terminations or pads (18) on both opposing major surfaces. Each of the printed circuit boards has a printed circuit pattern that has a plurality of pads (34, 36) that correspond to the electrical terminations on both sides of the double-sided leadless component. The electrical terminals on one side of the component are attached to the pads on the first substrate and the electrical terminals on the other side of the leadless component are attached to the pads on the second substrate. The printed circuit boards are joined together to form a multilayered circuit board (44) so that the double-sided leadless component is buried or recessed inside. The component is attached to the pads of the printed circuit board using solder.
    Type: Grant
    Filed: December 23, 1993
    Date of Patent: June 20, 1995
    Assignee: Motorola, Inc.
    Inventors: Scott G. Potter, Michael J. Watkins
  • Patent number: 5422788
    Abstract: Adhesion between a heat spreader (15) and a substance (19) to be adhered to the heat spreader can be enhanced by using thermal spray deposition to apply a coating (23) to the heat spreader. The substance to be adhered is applied to the coated heat spreader.
    Type: Grant
    Filed: July 6, 1994
    Date of Patent: June 6, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Katherine G. Heinen, Brenda C. Gogue, Henry F. Breit
  • Patent number: 5422435
    Abstract: A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: June 6, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Peng-Cheng Lin, Luu T. Nguyen
  • Patent number: 5421081
    Abstract: A method for producing an electronic part mounting structure in which electronic parts such as IC packages are electrically connected to the surface of a printed circuit board utilizes a low-melting point metal. More particularly, the method provides an electronic part mounting structure capable of sufficiently and assuredly supplying solder to a portion between the terminal of a printed circuit board and the leads of an electric part while maintaining a predetermined thickness required to connect the printed circuit board and the electronic part to each other. By arranging the structure such that a gap, in which a solder layer having a predetermined thickness can be formed between the terminal of the printed circuit board and the lead of the electronic part to be connected to the terminal, is formed, the solder required to solder-connect the two elements can be sufficiently and assuredly supplied to the gap. Therefore, a reliable solder connection can be established.
    Type: Grant
    Filed: May 13, 1993
    Date of Patent: June 6, 1995
    Assignee: Hitachi, Ltd.
    Inventors: Suguru Sakaguchi, Toshiharu Ishida, Kooji Serizawa, Hiroyuki Tanaka, Ichiro Miyano, Hiroshi Nakamura
  • Patent number: 5420757
    Abstract: A method of forming an environmentally sealed transponder type circuit wherein the circuit components are mounted on a lead type substrate frame, the components are encapsulated in a plastic housing in a plastic molding process so that the housing is supported in the frame only by a plurality of the leads, and then severing the leads at the periphery of the housing to provide a leadless package. The frame may be formed of a conductive material, an insulating material or as a printed circuit board. A novel printed circuit type lead frame whereby a coil of the circuit may be mechanically attached and directly secured to the frame is additionally disclosed.
    Type: Grant
    Filed: June 11, 1993
    Date of Patent: May 30, 1995
    Assignee: Indala Corporation
    Inventors: Noel H. Eberhardt, Jean-Marc Delbecq
  • Patent number: 5413489
    Abstract: An integrated circuit package for demountable attachment to a printed circuit board or like device is formed from an integrated assembly of an IC chip and socket, The IC chip is permanently mounted to a chip carrier which spreads the contact area from a first area to a larger second area. The chip carrier or spreader is contained in a plastic socket formed of a cover and a base. The base has an array of apertures therethrough each of which is equipped with wadded wire/plunger contacts for conformal contact with both pads on the bottom of the chip carrier and pads on a circuit board.
    Type: Grant
    Filed: April 27, 1993
    Date of Patent: May 9, 1995
    Assignee: Aptix Corporation
    Inventor: Andrew Switky
  • Patent number: 5414214
    Abstract: An apparatus (105, 301) for enclosing a microfabricated component (225) includes a package base (120, 405, 910), a package lid (110, 510, 950) and a seal (215) coupled to the package base (120, 405, 910) and to the package lid (110, 510, 950). The apparatus (105, 301) further includes a conductive loop (210, 610, 920) thermally coupled to the seal (215). Electrical energy is supplied to the conductive loop (210, 610, 920) to heat the conductive loop (210, 610, 920) and seal (215) to melt the seal (215) and thereby to seal the package base (120, 405, 910) to the package lid (110, 510, 950), providing a sealed environment for the microfabricated component (225).
    Type: Grant
    Filed: June 27, 1994
    Date of Patent: May 9, 1995
    Assignee: Motorola, Inc.
    Inventors: Frederick Y.-T. Cho, Michael J. Anderson, Howard D. Knuth
  • Patent number: 5412540
    Abstract: The contacts extending from the four sides of a flat-pack are releasably held against corresponding contacts extending from the sides of a socket for the flat-pack, by means of a cover comprising four arms pivotally mounted on the socket each near one of its four corners; by pivoting the arms downwardly against the tops of the flat-pack contacts, these contacts are pressed against, and held in positive contact with, the underlying socket contacts, and by pivoting the arms upwardly, the flat-pack can be released for removal and subsequent replacement. In addition, the cover is usefully mounted in position on the flat-pack even when the flat-pack is free of the socket, in which use it serves to protect the leads of the flat-pack in handling and during storage, for example.
    Type: Grant
    Filed: July 20, 1993
    Date of Patent: May 2, 1995
    Assignee: The Whitaker Corporation
    Inventors: Arkadiy Y. Golubchik, Donald K. Harper, Jr., Michael F. Laub, David W. McMullen
  • Patent number: 5412157
    Abstract: A semiconductor device includes a molded resin encapsulating a semiconductor chip, outer leads extending from the molded resin and having free ends, and a resin layer connecting and supporting the outer leads along the entire length of the outer leads. The resin layer may have an activating ability for soldering. A method for manufacturing a semiconductor device includes preparing a semiconductor device having a molded resin and a plurality of outer lead portions extending from the molded resin and connected to a lead frame, forming a resin film on and between the outer lead portions; cutting the lead portions to provide cantilevered outer leads having free ends; lead-forming the outer leads with lead-forming dies while heating the resin film to form a resin layer connecting and supporting the outer leads along the entire lengths of the outer leads, and taking the semiconductor device out of the lead-forming dies after the resin layer has been cured.
    Type: Grant
    Filed: July 16, 1993
    Date of Patent: May 2, 1995
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hideya Yagoura, Noriaki Higuchi, Haruo Shimamoto
  • Patent number: 5410450
    Abstract: External lead-through terminals of a semiconductor device, such as a power transistor module, are internally wired to a circuit assembly by a wiring block consisting of one or more conductive lead frames interposed between the lead-through terminals and the circuit assembly.
    Type: Grant
    Filed: December 3, 1992
    Date of Patent: April 25, 1995
    Assignee: Fuji Electric Co., Ltd.
    Inventors: Kiyoshi Iida, Hisashi Fujitaka
  • Patent number: 5403975
    Abstract: A process for producing electronic package components from an aluminum alloy is disclosed. The components have a black color through integral color anodization. The desired color, thickness and surface finish are achieved by regulation of amperage during anodization. The amperage is rapidly raised to in excess of 80 amps per square foot and then allowed to gradually decrease as a function of oxide growth.
    Type: Grant
    Filed: August 31, 1993
    Date of Patent: April 4, 1995
    Assignee: Olin Corporation
    Inventors: Anthony M. Pasqualoni, Deepak Mahulikar, Satish K. Jalota, Andrew J. Brock
  • Patent number: 5404273
    Abstract: A semiconductor-device package includes: a printed circuit board which has a chip-accommodating hole in its center portion and which has external connection terminals formed on its one side and a flexible substrate which has a supporting film having a central hole coaxial with the chip-accommodating hole, a given circuit pattern which is formed on the supporting film and inner leads which project inside the central hole and which have micro patterns, the flexible substrate being bonded on the other side of the circuit pattern of the printed circuit board with electrical conduction between them.
    Type: Grant
    Filed: March 23, 1994
    Date of Patent: April 4, 1995
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Masatoshi Akagawa
  • Patent number: 5399809
    Abstract: A multi-layer lead frame for a semiconductor device includes a signal layer made of a metal strip having a signal pattern including a plurality of lead lines. A power supply or ground layer is adhered and laminated to the signal layer by means of an adhesive film. The adhesive film is an electrically insulation connector tape having through holes extending in a thickness direction. Conductive metal vias are filled in the through holes for electrically connecting the power supply or ground layer particular leads among the plurality of lead lines.
    Type: Grant
    Filed: May 26, 1993
    Date of Patent: March 21, 1995
    Assignee: Shinko Electric Industries Company, Limited
    Inventor: Toshikazu Takenouchi
  • Patent number: 5399805
    Abstract: There is provided an electronic package where the package components define a cavity. A semiconductor device and a portion of a leadframe occupy part of the cavity. Substantially the remainder of the cavity is filled with a compliant polymer, such as a silicone gel. Since the cavity is no longer susceptible to gross leak failure, the seal width of adhesives used to assemble the package may be reduced, thereby increasing the area available for mounting the semiconductor device.
    Type: Grant
    Filed: September 27, 1993
    Date of Patent: March 21, 1995
    Assignee: Olin Corporation
    Inventors: Derek E. Tyler, Deepak Mahulikar, Anthony M. Pasqualoni, Jeffrey S. Braden, Paul R. Hoffman
  • Patent number: 5399804
    Abstract: A semiconductor device includes a stage, a semiconductor chip which is mounted on the stage, a plurality of electrode members which are wire bonded to the semiconductor chip, where a first gap is formed between the stage and one electrode member and a second gap is formed between two electrode members, a plurality of leads including inner leads which are wire bonded to at least one of the semiconductor chip and the electrode members and electrically connected thereto, and a resin package which encapsulates the semiconductor chip, the stage, the electrode members and the inner leads by a resin. The resin fills the first and second gaps, so that the stage and the one electrode member are isolated and the two electrode members are isolated.
    Type: Grant
    Filed: January 4, 1993
    Date of Patent: March 21, 1995
    Assignee: Fujitsu Limited
    Inventors: Yoshiyuki Yoneda, Kazuto Tsuji, Junichi Kasai, Hideharu Sakoda
  • Patent number: 5396032
    Abstract: Multi-chip module (MCM) (10) includes package body (12) having cavity (20) for accepting a plurality of devices and substrates and seal ring (26) to ensure the integrity of the package. Lead frame (18) having a plurality of individual leads (28) is coupled to the package body (12). Plurality of test points (38) or test pins (30) are located on the external surface of package body (12). A plurality of bond pads are located in cavity (20), including a first set or tier and a second set or tier of bond pads for electrically coupling the devices and substrates in the cavity (20) external to package body (12). The first set or tier of bond pads provides electrical connection between the individual devices in MCM (10) to plurality of test points (38) or test pins (30), and the second set or tier of bond pads provides electrical connection between the individual devices in MCM (10) and plurality of individual leads (28).
    Type: Grant
    Filed: May 4, 1993
    Date of Patent: March 7, 1995
    Assignee: Alcatel Network Systems, Inc.
    Inventors: Harry B. Bonham, Jr., Charles R. Pratt, III, Bryan K. Douglas
  • Patent number: 5394303
    Abstract: The present invention comprises a semiconductor chip 1, chip electrodes 2 provided on one surface of the semiconductor chip 1, and connected to semiconductor elements formed in the semiconductor chip, a flexible insulating film 3 wrapping the chip electrodes, wiring layers 5 formed in the insulating film 3, and electrically connected to the chip electrodes 2, and terminal electrodes 6 provided on that surface of the insulating film 3 which extends on the upper surface of the chip 1, the electrodes 6 being electrically connected to the wiring layers 5, and functioning as external terminals of the chip 1. Thus, the terminal electrodes 6 are introduced, by means of the wiring layers 5 formed in the insulating film 3, onto that surface of the insulating film 3 which extends on the upper surface of the chip 1.
    Type: Grant
    Filed: September 9, 1993
    Date of Patent: February 28, 1995
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuhiro Yamaji
  • Patent number: 5392197
    Abstract: The electric device has a printed circuit board (10) which carries an electronic circuit with electronic components (12). The circuit is provided with a plug connector strip (14) for making electrical contact. In addition to the housing cover (27) and housing base (32), additional plastic coverings (16, 23) which are tight against moisture are provided to protect the circuit against moisture in a reliable manner and cover the printed circuit board on the upper side (11) and the underside (22) in the manner of a hood. These plastic parts are connected with the printed circuit board so as to be tight against moisture. The housing cover (27) and housing base (30) need not carry out any sealing functions and serve exclusively to protect against mechanical damage and, under certain circumstances, for shielding.
    Type: Grant
    Filed: March 18, 1993
    Date of Patent: February 21, 1995
    Assignee: Robert Bosch GmbH
    Inventors: Harald Cuntz, Martin Rau, Dieter Karr
  • Patent number: 5389738
    Abstract: A tamperproof arrangement for an integrated circuit device. The arrangement includes a package and lid fabricated of heavy metals to prevent X-radiation or infrared detection of circuit operation. Sensors and control circuitry are located on the integrated circuit die itself which detect increased temperature and radiation and clear or zeroize any sensitive information included within the integrated circuit device. Electrode finger grids above and below the integrated circuit die detect physical attempts to penetrate the integrated circuit die. Critical circuit functions are segregated from non-critical functions. Power applied to the integrated circuit device is monitored and separated for critical and non-critical circuit functions.
    Type: Grant
    Filed: May 4, 1992
    Date of Patent: February 14, 1995
    Assignee: Motorola, Inc.
    Inventors: Gerald V. Piosenka, David M. Harrison, Ronald V. Chandos
  • Patent number: 5389739
    Abstract: An electronic device package assembly including a base member; a cover member; a lead frame having a plurality of leads disposed between the base member and the cover member; an electronic device disposed between the base member and the cover member and electrically attached to the leads; bonding rings for bonding the base member and the cover member to the lead frame; and spacers disposed between the lead frame and the base member and the lead frame and the cover member for maintaining the base member and the cover member at a predetermined spacing from the lead frame.
    Type: Grant
    Filed: December 15, 1992
    Date of Patent: February 14, 1995
    Assignee: Hewlett-Packard Company
    Inventor: Louis T. Mills
  • Patent number: 5387762
    Abstract: An electronic component is provided which comprises a resin package for enclosing inside parts, and at least one lead terminal projecting out from the resin package to have a bonding end. The lead terminal is bent to provide an armpit-like portion between the lead terminal and the resin package for retaining a solder wire in a sandwiched state. At the time of mounting the electronic component to a circuit board, the solder wire be caused to melt at a soldering temperature for merging with solder fillets along the bonding end of the lead terminal.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: February 7, 1995
    Assignee: Rohm Co., Ltd.
    Inventors: Miki Hasegawa, Yasuo Kanetake
  • Patent number: 5388029
    Abstract: In a semiconductor chip carrier which has a rectangular insulating substrate having four corners and electrode leads deposited on a peripheral surface of the substrate and which is mounted onto a circuit board with each electrode lead being connected to the corresponding board electrode through a solder mass, widths of the electrode leads are wider at each of the four corners than those of the electrode leads located at positions except the four corners. An area of the contact through the solder between each electrode lead positioned at each corner and the corresponding board electrode is wider than that between each of the other electrode lead and each corresponding board electrode. As each electrode lead positioned at each corner is strongly connected to the board electrode, it is seldom peeled off from the board electrode even when the circuit board is twisted or warped during or after the process of mounting the chip carrier onto the circuit board.
    Type: Grant
    Filed: November 12, 1992
    Date of Patent: February 7, 1995
    Assignee: NEC Corporation
    Inventor: Yoshifumi Moriyama
  • Patent number: 5386625
    Abstract: A method of assembling an integrated circuit (IC) by a TAB (Tape Automated Bonding) system, and an IC assembled thereby. Leads extending from a TAB tape and connected to an IC are each partly reduced in width. Hence, even when the end portions of the leads are deformed by some object by accident, it is not necessary to correct the shape of the leads since such end portions will be eventually cut off and discarded in the event of packaging of the IC.
    Type: Grant
    Filed: March 9, 1994
    Date of Patent: February 7, 1995
    Assignee: NEC Corporation
    Inventor: Kenji Tsukamoto
  • Patent number: 5384690
    Abstract: Disclosed is a parallel processor packaging structure and a method for manufacturing the structure. The individual logic and memory elements are on printed circuit cards. These printed circuit boards and cards are, in turn, mounted on or connected to circuitized flexible substrates extending outwardly from a laminate of the circuitized, flexible substrates. Intercommunication is provided through a switch structure that is implemented in the laminate. The printed circuit cards are mounted on or connected to a plurality of circuitized flexible substrates, with one printed circuit card at each end of the circuitized flexible circuit. The circuitized flexible substrates connect the separate printed circuit boards and cards through the central laminate portion. This laminate portion provides XY plane and Z-axis interconnection for inter-processor, inter-memory, inter-processor/memory element, and processor to memory bussing interconnection, and communication.
    Type: Grant
    Filed: July 27, 1993
    Date of Patent: January 24, 1995
    Assignee: International Business Machines Corporation
    Inventors: Charles R. Davis, Thomas P. Duffy, Steven L. Hanakovic, Howard L. Heck, John T. Kolias, John S. Kresge, David N. Light, Ajit K. Trivedi
  • Patent number: 5384692
    Abstract: A socket for mounting an external integrated circuit on a printed circuit board is described. The socket includes a base having a bottom that can be mounted on the printed circuit board and a top that can receive the external integrated circuit. A plurality of connectors are located on the top of the base for coupling to the external integrated circuit. An in-socket embedded integrated circuit is embedded inside the base for providing a predetermined electronic function. The external integrated circuit and the in-socket embedded integrated circuit occupy substantially minimized space on the printed circuit board. The external integrated circuit can be a microprocessor and the in-socket integrated circuit can also include a microprocessor. The socket can be used for a computer system that allows the embedded microprocessor functioning when the external microprocessor is not coupled to the plurality of connectors of the base.
    Type: Grant
    Filed: December 16, 1993
    Date of Patent: January 24, 1995
    Assignee: Intel Corporation
    Inventor: Kosar A. Jaff
  • Patent number: 5380952
    Abstract: A stabilizer bar made of non-conductive material (such as a poly enid plastic) is secured to the top side of extended leads on each side of a flat high density integrated circuit package. The bar is located intermediate the length of the leads, and is used as a lead form during a subsequent forming operation. The leads are formed around the stabilizer bar, which remains in place throughout the forming operation and during subsequent mounting of the integrated circuit package.
    Type: Grant
    Filed: November 24, 1993
    Date of Patent: January 10, 1995
    Assignee: VLSI Technology, Inc.
    Inventor: Paul S. Levy
  • Patent number: 5379188
    Abstract: There is provided a mounting arrangement for an integrated circuit chip carrier 7. The carrier 7 is retained in a holder 5 using the lateral forces created by the interference between leads 12 of the carrier and the walls 17 of the holder 5. A lid 6 is applied to the carrier 5 and leaf springs 3 are disposed in between. The lid 6 clips on to a circuit board 8 by virtue of barbed legs 4 and holes 11. The springs 3 urge the leads 12 against contact pads 9 on the circuit board 8.
    Type: Grant
    Filed: May 3, 1993
    Date of Patent: January 3, 1995
    Assignee: Winslow International Limited
    Inventor: David W. G. Winslow
  • Patent number: 5375320
    Abstract: A method for forming a small outline "J" lead for a semiconductor device having a main body and a lead comprises three bend steps. The lead comprises a surface attached to the body, a distal end away from the body, and a proximal area interposed between the attached surface and the distal end. The method consists of the lead bend steps of rounding the distal end of the lead in a single bend step to form an are in the distal end having a radius of between 0.030" and 0.040", the arc terminating toward the proximal area of the leads in a substantially straight lead portion. Next, the proximal area of the lead is bent close to the attached surface such that the proximal area of the lead forms an angle of between about 60.degree. and 90.degree. with the attached surface of the lead. Finally, the arc in the distal end is increased to a radius of between about 0.035" and 0.045".
    Type: Grant
    Filed: June 9, 1992
    Date of Patent: December 27, 1994
    Assignee: Micron Technology, Inc.
    Inventors: Larry D. Kinsman, Michael P. Grant, Gregory M. Chapman
  • Patent number: 5376756
    Abstract: Single, continuous bonding wires for an integrated-circuit die are supported in mid-span by a support ring which is snap-fit or adhesively bonded to a die-attach paddle of a leadframe. The support member includes a groove formed in its distal end for receiving an adhesive material, if necessary, for securing the bonding wires in position to prevent wire-wash and electrically shorting of the bonding wires when a plastic molding compound is formed around the die and leadframe. Alternatively the bonding wires are contained within notches formed in the distal end of the support ring. A lid placed over the support ring provides an enclosure for the integrated-circuit die. Stacking of support rings on each other and concentric support rings provide various optional arrangements for supporting bonding wires.
    Type: Grant
    Filed: December 20, 1991
    Date of Patent: December 27, 1994
    Assignee: VLSI Technology, Inc.
    Inventor: Young I. Kwon