Abstract: A fuel cell separator includes a metal substrate having a surface; an ion penetration layer including carbon diffusion-inhibiting ions extending from the surface of the metal substrate into the metal substrate; and a carbon coating layer disposed on the surface of the metal substrate.

Abstract: A method for forming a patterned film on a substrate includes: step of patterning a mask material on the substrate, thereby covering, with the mask material, the region except a patterned film forming region on a substrate surface on which the patterned film is to be formed; step of covering, with a protective member, at least a part of the surface of the mask material opposite to the substrate so as to allow the patterned film forming region to communicate with outside air, thereby forming a workpiece to be subjected to film formation in following step; step of forming a film on at least the patterned film forming region of the surface of the workpiece communicating with the outside air; step of releasing the protective member from the mask material; and step of removing the mask material and a part of the film on the mask material.

Abstract: The present disclosure provides an etching mask, a method for manufacturing the same, a method for manufacturing a porous membrane using the same, a porous membrane, a fine dust blocking mask including the same, and a method for manufacturing a surface enhanced Raman scattering active substrate. In this connection, the etching mask includes an organic film; and a pattern layer disposed on the organic film, wherein the pattern layer has openings defined therein having a uniform size, wherein each of the openings includes a micro-scale or nano-scale hole.

Abstract: Systems and methods are provided for determining a clean endpoint time for a current run of a chamber. The clean endpoint time for the current run may be determined by determining that a chamber parameter, such as a chamber pressure, has stabilized. Historical clean endpoint time data is updated by adding the clean endpoint time for the current run of the chamber. A recommended clean endpoint time is then determined for the chamber based on the updated historical clean endpoint time data.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a sealing resin layer containing an inorganic filler so as to seal a semiconductor chip, removing a portion of the surface of the sealing resin layer by dry etching such that a portion of the inorganic filler is exposed, and forming a shield layer so as to cover at least the sealing resin layer.

Abstract: [Object] To provide a radical generator which can produce radicals at higher density. [Means for Solution] The radical generator includes a supply tube 10 made of SUS, a hollow cylindrical plasma-generating tube 11 which is connected to the supply tube 10 and which is made of pyrolytic boron nitride (PBN). A first cylindrical CCP electrode 13 and a second cylindrical CCP electrode 30 are disposed outside the plasma-generating tube 11. A coil 12 is provided so as to wind about the outer circumference of the plasma-generating tube 11 at the downstream end of the first CCP electrode 13. A thin connecting tube 23 extending from the bottom of the plasma-generating tube 11 is inserted into the supply tube 10.

Abstract: A three-dimensional diffraction grating is generated by selective deposition and/or selective etching. The three-dimensional diffraction grating includes a substrate and a plurality of structures located at different positions on the substrate. The structures have different materials. Edges of at least some of the structures are aligned. The three-dimensional diffraction grating includes different materials and aligned edges in all three dimensions. With the different materials and aligned edges, the three-dimensional diffraction gratings is configured to eliminate display artifacts, such as ghost, rainbow, etc.

Abstract: A method of forming a semiconductor device structure is provided. The method includes successively forming first and second hard mask layers over a trench pattern region of a material layer. The second hard mask layer has a first tapered opening corresponding to a portion of the trench pattern region and a passivation spacer is formed on a sidewall of the first tapered opening to form a second tapered opening therein. The method also includes forming a third tapered opening below the second tapered opening and removing a portion of the passivation spacer in a first etching process. The method also includes forming a vertical opening in the first hard mask layer below the bottom of the third tapered opening in a second etching process. The vertical opening has a width that is substantially equal to a bottom width of the third tapered opening.

Abstract: A method for producing an optoelectronic component is disclosed. In an embodiment the method includes a metallization with first mask structures is deposited directionally, and then a first passivation material is deposited non-directionally onto the metallization. Further, cutouts are introduced into the semiconductor body, such that the cutouts extend right into an n-type semiconductor region, and a second passivation material is applied on side faces of the cutouts. Furthermore, an n-type contact material is applied, structured and passivated. Moreover, contact structures are arranged on the semiconductor body and electrically connected to the n-type contact material and the metallization, wherein the contact structures and the semiconductor body are covered with a potting.

Abstract: This disclosure relates to a plasma processing system and methods for high precision etching of microelectronic substrates. The system may include a combination of microwave and radio frequency (RF) power sources that may generate plasma conditions to remove monolayer(s). The system may generation a first plasma to form a thin adsorption layer on the surface of the microelectronic substrate. The adsorbed layer may be removed when the system transition to a second plasma. The differences between the first and second plasma may be include the ion energy proximate to the substrate. For example, the first plasma may have an ion energy of less than 20 eV and the second plasma may have an ion energy greater than 20 eV.

Abstract: A substrate processing apparatus includes a rotary table arranged in a vacuum chamber, a first reaction gas supply unit that supplies a first reaction gas to a surface of the rotary table, a second reaction gas supply unit that is arranged apart from the first reaction gas supply unit and supplies a second reaction gas, which reacts with the first reaction gas, to the surface of the rotary table, and an activated gas supply unit that is arranged apart from the first and second reaction gas supply units. The activated gas supply unit includes a discharge unit that supplies an activated fluorine-containing gas to the surface of the rotary table, a pipe that is arranged upstream of the discharge unit and supplies the fluorine-containing gas to the discharge unit, and at least one hydrogen-containing gas supply unit arranged at the pipe for supplying a hydrogen-containing gas into the pipe.

Abstract: Methods are disclosed for etching a substrate. The method includes preferentially coating cover ring relative other chamber components in the processing chamber, while under vacuum, and while a substrate is not present in the processing chamber. The substrate is subsequently etched the processing chamber. After etching, the interior of the processing chamber is cleaned after the substrate has been removed.

Abstract: Semiconductor structures including isolation regions and methods of forming the same are provided. A first layer is formed over a substrate, where the first layer comprises a semiconductor material. First and second trenches are etched, with each of the first and second trenches extending through the first layer and into the substrate. A wet etchant is introduced into the trenches, and the wet etchant etches a first opening below the first trench and a second opening below the second trench. Each of the first and second openings extends laterally below the first layer. The first and second openings are separated by a portion of the substrate adjoining the first and second openings. An oxidation process is performed to oxidize the portion of the substrate adjoining the first and second openings. An insulating material is deposited that fills the openings and the trenches.

Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.

Abstract: An electrical discharge machining oil composition of the invention includes an organic acid metal salt and a base oil, in which the organic acid metal salt is an organic acid salt of a metal having an electronegativity on Pauling scale of 2 or less, and the present composition has a volume resistivity at 80 degrees C. of 2×10?5 T?·m or more and a kinematic viscosity at 40 degrees C. in a range from 0.5 mm2/s to 10 mm2/s.

Abstract: Process for providing structures for an improved protein adherence on the surface of a body including the steps of a) providing a basic body made of titanium or a titanium alloy, b) acid-etching the basic body, c) storing the acid-etched basic body in an aqueous solution, whereby nanostructures are formed on the surface of the basic body, and d) drying the basic body with the nanostructures formed on its surface.

Abstract: According to one embodiment of a semiconductor device, the semiconductor device includes a semiconductor substrate having a first surface, an insulation layer having a laterally varying thickness on the first surface, and a metal layer on the first surface. The insulation layer has ripples in its surface facing the metal layer. According to another embodiment of a semiconductor device, the semiconductor device includes a semiconductor substrate having a first surface and including at least one of a laterally varying thickness and an inclined first surface. The first surface of the semiconductor substrate has ripples.

Abstract: A semiconductor manufacturing apparatus includes a stage, and an exhaust duct having an annular passage surrounding a processing space over the stage, an annular slit through which a gas supplied to the processing space is led into the annular passage, and an exhaust port through which the gas in the annular passage is discharged to the outside, wherein the opening-area percentage of the slit is increased with increase in distance from the exhaust port.

Abstract: In one embodiment, a processing apparatus may include a process chamber configured to house a substrate and a hybrid source assembly that includes a gas channel coupled to a molecular source; and a plasma chamber configured to generate a plasma and isolated from the gas channel. The processing apparatus may also include an extraction assembly disposed between the hybrid source assembly and process chamber, coupled to the gas channel and plasma chamber, and configured to direct an ion beam to a substrate, the ion beam comprising angled ions wherein the angled ions form a non-zero angle with respect to a perpendicular to a substrate plane; and configured to direct a molecular beam comprising molecular species received from the gas channel to the substrate.

Abstract: An apparatus for shielding a controlled pressure environment, including a shield assembly with: a gate disc arranged for location in a chamber and including a first continuous surface facing an opening in the chamber and including an outer circumference extending past the opening in a radial direction orthogonal to a longitudinal axis passing through the chamber and the opening; and an at least one actuator arranged to displace the gate disc in an axial direction parallel to the longitudinal axis. The opening is arranged for connection to an inlet of a vacuum pump. In an example embodiment, the thermal system attains and maintains thermal equilibrium in the chamber and/or to shields the chamber from unwanted thermal affects by heating or cooling the gate disc to offset cooling or heat generated by the vacuum pump. For example, the gate disc is cooled to offset heat generated by a turbo-molecular pump.

Abstract: A physical vapor deposition (PVD) chamber, a process kit of a PVD chamber and a method of fabricating a process kit of a PVD chamber are provided. In various embodiments, the PVD chamber includes a sputtering target, a power supply, a process kit, and a substrate support. The sputtering target has a sputtering surface that is in contact with a process region. The power supply is electrically connected to the sputtering target. The process kit has an inner surface at least partially enclosing the process region, and a liner layer disposed on the inner surface. The substrate support has a substrate receiving surface, wherein the liner layer disposed on the inner surface of the process kit has a surface roughness (Rz), and the surface roughness (Rz) is substantially in a range of 50-200 ?m.

Abstract: A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

Abstract: A method for forming the semiconductor device structure is provided. The method includes forming a metal layer in a first dielectric layer over a substrate and forming an etch stop layer over the metal layer. The etch stop layer is made of metal-containing material. The method also includes forming a second dielectric layer over the etch stop layer and removing a portion of the second dielectric layer to expose the etch stop layer and to form a via by an etching process. The method further includes performing a plasma cleaning process on the via and the second dielectric layer, and the plasma cleaning process is performed by using a plasma including nitrogen gas (N2) and hydrogen gas (H2).

Abstract: Hydrogen energy systems for obtaining hydrogen gas from a solid storage medium using controlled lasers. Also disclosed are systems for charging/recharging magnesium with hydrogen to obtain magnesium hydride. Other relatively safe systems assisting storage, transport and use (as in vehicles) of such solid storage mediums are disclosed.

Abstract: An etching method is provided. In the etching method, a temperature of a chiller configured to cool a pedestal is controlled so as to become ?20 degrees C. or lower. Plasma is generated from a hydrogen-containing gas and a fluoride-containing gas supplied from a gas supply source by supplying first high frequency power having a first frequency supplied to the pedestal from a first high frequency power source. A silicon oxide film deposited on a substrate placed on the pedestal is etched by the generated plasma. Second high frequency power having a second frequency lower than the first frequency of the first high frequency power is supplied to the pedestal from a second high frequency power source in a static eliminating process after the step of etching the silicon oxide film.

Abstract: A method for manufacturing a wafer on which are formed resonators, each resonator including, above a semiconductor substrate, a stack of layers including, in the following order from the substrate surface: a Bragg mirror; a compensation layer made of a material having a temperature coefficient of the acoustic velocity of a sign opposite to that of all the other stack layers; and a piezoelectric resonator, the method including the successive steps of: a) depositing the compensation layer; and b) decreasing thickness inequalities of the compensation layer due to the deposition method, so that this layer has a same thickness to within better than 2%, and preferably to within better than 1%, at the level of each resonator.

Abstract: Planarization processing methods are disclosed. In one aspect, the method includes patterning a material layer and planarizing the patterned material layer by using sputtering. Due to the patterning of the material layer, the loading requirements of nonuniformity on a substrate for sputtering the material layer are reduced, compared with that before the patterning.

Abstract: A system for substrate deposition is disclosed. The system includes a wafer pallet and an anode. The wafer pallet has a bottom and a top. The top of the wafer pallet is configured to hold a substrate wafer. The anode has a substantially fixed position relative to the wafer pallet and is configured to move with the wafer pallet through the deposition chamber. The anode is electrically isolated from the substrate wafer.

Abstract: Etching gases are disclosed for plasma etching channel holes, gate trenches, staircase contacts, capacitor holes, contact holes, etc., in Si-containing layers on a substrate and plasma etching methods of using the same. The etching gases are trans-1,1,1,4,4,4-hexafluoro-2-butene; cis-1,1,1,4,4,4-hexafluoro-2-butene; hexafluoroisobutene; hexafluorocyclobutane (trans-1,1,2,2,3,4); pentafluorocyclobutane (1,1,2,2,3-); tetrafluorocyclobutane (1,1,2,2-); or hexafluorocyclobutane (cis-1,1,2,2,3,4). The etching gases may provide improved selectivity between the Si-containing layers and mask material, less damage to channel region, a straight vertical profile, and reduced bowing in pattern high aspect ratio structures.

Abstract: The present disclosure provides a semiconductor device that includes, a substrate; a first conductive line located over the substrate and extending along a first axis, the first conductive line having a first length and a first width, the first length being measured along the first axis; a second conductive line located over the first conductive line and extending along a second axis different from the first axis, the second conductive line having a second length and a second width, the second length being measured along the second axis; and a via coupling the first and second conductive lines, the via having an upper surface that contacts the second conductive line and a lower surface that contacts the first conductive line. The via has an approximately straight edge at the upper surface, the straight edge extending along the second axis and being substantially aligned with the second conductive line.

Abstract: Apparatus for controlling the flow of a gas in a process chamber is provided herein. In some embodiments, an apparatus for controlling the flow of a gas in a process chamber having a processing volume within the process chamber disposed above a substrate support and a pumping volume within the process chamber disposed below the substrate support may include an annular plate surrounding the substrate support proximate a level of a substrate support surface of the substrate support, wherein the annular plate extends radially outward toward an inner peripheral surface of the process chamber to define a uniform gap between an outer edge of the annular plate and the inner peripheral surface, wherein the uniform gap provides a uniform flow path from the processing volume to the pumping volume.

Abstract: Memory cell array architectures and methods of forming the same are provided. An example method for forming an array of memory cells can include forming a plurality of vertical structures each having a switch element in series with a memory element in series with a top electrode, and forming an interconnection conductive material between the respective top electrodes of the plurality of vertical structures. The interconnection conductive material is etched-back and chemical-mechanical polished (CMPed). A conductive line is formed over the interconnection conductive material after CMPing the interconnection conductive material.

Abstract: An arrangement is provided for feeding in HF current for rotatable tubular cathodes in a vacuum chamber of a plasma coating system as well as a high frequency current source. Located inside the tubular cathode is a magnet arrangement that extends along said tubular cathode for generating a magnetic field. The arrangement enables a low loss infeed of HF current, so that a particularly homogeneous sputter removal from the tubular cathode is guaranteed. The HF current source is coupled to the tubular cathode inside the vacuum chamber by a capacitive infeed of HF current in the form of a coupling capacitor. The coupling capacitor includes a part of the surface of the tubular cathode and a metal plate or metal film that surrounds the tubular cathode, at least partially, at a specified distance.

Abstract: A planarization process, the process including performing first sputtering on a material layer, with an area of the material layer which has a relatively low loading condition for sputtering shielded by a first shielding layer, removing the first shielding layer, and performing second sputtering on the material layer to planarize the material layer.

Abstract: A substrate processing apparatus in which an improved film quality is obtained is disclosed. A precursor gas supply process of supplying a precursor gas to a process chamber while maintaining a substrate accommodated in the process chamber at a first temperature, a first removal process of removing the precursor gas remaining in the process chamber by supplying an inert gas, which is heated at a second temperature higher than the first temperature, to the process chamber, a reaction gas supply process of supplying a reaction gas to the process chamber, and a second removal process of removing the reaction gas remaining in the process chamber by supplying an inert gas to the process chamber are performed.

Abstract: An elastic wave filter device includes a transmission elastic wave filter chip and a reception elastic wave filter chip. The transmission elastic wave filter chip includes an insulating support substrate, a piezoelectric layer directly or indirectly supported by the support substrate, and an IDT electrode in contact with the piezoelectric layer. The reception elastic wave filter chip includes a piezoelectric substrate and an IDT electrode provided on the piezoelectric substrate. The thermal conductivity of the support substrate is higher than the thermal conductivity of either of the piezoelectric layer and the piezoelectric substrate.

Abstract: Resonances can be tuned in dielectric resonators in order to construct single-resonator, negative-index metamaterials. For example, high-contrast inclusions in the form of metallic dipoles can be used to shift the first electric resonance down (in frequency) to the first magnetic resonance, or alternatively, air splits can be used to shift the first magnetic resonance up (in frequency) near the first electric resonance. Degenerate dielectric designs become especially useful in infrared- or visible-frequency applications where the resonator sizes associated with the lack of high-permittivity materials can become of sufficient size to enable propagation of higher-order lattice modes in the resulting medium.

Abstract: Processing equipment for the metallization of a plurality of semiconductor workpieces. A controlled atmospheric non-oxidizing gas region comprises at least two enclosed deposition zones, the controlled atmospheric non-oxidizing gas region is isolated from external oxidizing ambient. A temperature controller adjusts the temperature of the semiconductor workpiece in each of the at least two enclosed deposition zones. Each of the enclosed deposition zones comprising at least one spray gun for the metallization of the semiconductor workpiece. A transport system moves the semiconductor workpiece through the controlled atmospheric non-oxidizing gas region. A batch carrier plate carries the semiconductor workpiece through the controlled atmospheric non-oxidizing gas region. The controlled atmospheric non-oxidizing gas region further comprises a gas-based pre-cleaning zone.

Abstract: A method for patterning a metal substrate includes a series of surface treatments to control tunnel initiation at a micron or sub-micron level. In particular, the series of surface treatments include forming a hydration layer which acts as a mask while etching the surface of the metal substrate. The hydration layer mask enables control of the tunnel initiation on a micron or sub-micron level because the etching does not undercut the interface between the metal substrate and the hydration layer. As a result, the tunnels can be initiated in an orthogonal direction and closer together, thereby increasing the tunnel density.

Abstract: A method for fabricating an inductor structure having an increased quality factor (Q) is provided. In one embodiment, a substrate is provided and a plurality of metal layers are formed on the substrate. A spirally patterned conductor layer is formed over and in the substrate and in the metal layers to produce a planar spiral inductor. A via hole is formed over and in the substrate and in the metal layers within the spirally patterned conductor layer, the via hole being formed by a through silicon via (TSV) process. Thereafter, the via hole is filled with a core layer, wherein the core layer extends from a bottom surface of the substrate to a top surface of the metal layers.

Abstract: Disclosed is an apparatus and method for low-temperature plasma immersion processing of a variety of workpieces using accelerated ions, wherein low-temperature plasma is distributed around a cylindrical workpiece placed in a chamber, the workpiece is enclosed with a housing including a multi-slot extracting electrode to isolate the workpiece from plasma, and a negative potential sufficient to induce sputtering is applied to the workpiece and the electrode, so that ions from plasma are accelerated within the sheath formed between the extracting electrode and plasma, pass through the slot part of the electrode and bombard the workpiece, thus polishing the surface of the workpiece. This apparatus and method is effective for surface smoothing to ones of nm of large cylindrical substrates particularly substrates for micro or nanopattern transfer.

Abstract: A method of fabricating a magnetoresistive element, the method comprising: forming a first plurality of layers without breaking a vacuum, the first plurality of layers sequentially comprising: a first nonmagnetic conductive layer; a first ferromagnetic layer comprising an amorphous structure and a first magnetization direction; a nonmagnetic tunnel barrier layer; a second ferromagnetic layer comprising an amorphous structure and a second magnetization direction, and a getter layer having a direct contact with the second ferromagnetic layer; annealing the first plurality of layers; removing the getter layer and a portion of the second ferromagnetic layer adjacent to the getter layer; forming above the second ferromagnetic layer a second plurality of layers such that interface between the second ferromagnetic layer and the second plurality of layers is formed without breaking a vacuum after removing the getter layer and the portion of the second ferromagnetic layer, the second plurality of layers sequentially c

Abstract: Embodiments of the invention generally relate to a process kit for a semiconductor processing chamber, and a semiconductor processing chamber having a kit. More specifically, embodiments described herein relate to a process kit including a cover ring, a shield, and an isolator for use in a physical deposition chamber. The components of the process kit work alone and in combination to significantly reduce particle generation and stray plasmas. In comparison with existing multiple part shields, which provide an extended RF return path contributing to RF harmonics causing stray plasma outside the process cavity, the components of the process kit reduce the RF return path thus providing improved plasma containment in the interior processing region.

Abstract: A photoelectric conversion device having a new anti-reflection structure is provided. The photoelectric conversion device includes a first-conductivity-type crystalline semiconductor region, an intrinsic crystalline semiconductor region, an intrinsic semiconductor region, and a second-conductivity-type semiconductor region that are stacked over a first electrode. An interface between the first electrode and the first-conductivity-type crystalline semiconductor region is flat. The intrinsic crystalline semiconductor region includes a crystalline semiconductor region, and a plurality of whiskers that are provided over the crystalline semiconductor region and include a crystalline semiconductor. In other words, the intrinsic crystalline semiconductor region includes the plurality of whiskers; thus, a surface of the second electrode is uneven.

Abstract: Methods for enabling or enhancing growth of carbon nanotubes on unconventional substrates. The method includes selecting an inactive substrate, which has surface properties that are not favorable to carbon nanotube growth. A surface of the inactive substrate is treated so as to increase a porosity of the same. CNTs are then grown on the surface having the increased porosity.

Abstract: A plasma processing apparatus 1 includes a central inlet unit that introduces a processing gas containing at least one of an Ar gas, a He gas and an etching gas toward a central portion of a wafer W; a peripheral inlet unit 61 that introduces the processing gas toward a periphery portion thereof; a flow rate adjusting unit that adjusts a flow rate of the processing gas introduced toward the central portion thereof from the central inlet unit 55 and a flow rate of the processing gas introduced toward the periphery portion thereof from the peripheral inlet unit 61; and a controller 49 that controls the flow rates of the processing gas adjusted by the flow rate adjusting unit such that a partial pressure ratio of the He gas to the Ar gas contained in the processing gas is equal to or higher than a preset value.

Abstract: Embodiments of the present technology may include a method of processing a semiconductor substrate. The method may include providing the semiconductor substrate in a processing region. Additionally, the method may include flowing gas through a cavity defined by a powered electrode. The method may further include applying a negative voltage to the powered electrode. Also, the method may include striking a hollow cathode discharge in the cavity to form hollow cathode discharge effluents from the gas. The hollow cathode discharge effluents may then be flowed to the processing region through a plurality of apertures defined by electrically grounded electrode. The method may then include reacting the hollow cathode discharge effluents with the semiconductor substrate in the processing region.

Abstract: In sputter etching to improve the adhesion between upper electrodes and lead electrodes, the sputter etching of surfaces of the upper electrodes under an Ar gas flow at a flow rate of 60 sccm or more can reduce the residence time of Ar ions on the surfaces of the upper electrodes because of the Ar gas flow. This can prevent the charging of the upper electrodes due to the buildup of ionized Ar gas on the surfaces, reduce the influence of charging on piezoelectric elements, and provide a method for manufacturing a piezoelectric actuator that includes the piezoelectric elements each including a piezoelectric layer having small variations in hysteresis characteristics and deformation characteristics.

Abstract: A plasma treatment installation including at least two stationary workpiece holders adapted for controlled rotation about their respective axis and having supporting plates for supporting workpieces for the treatment thereof, at least one hood to be set on a workpiece holder that is adapted to enclose each of a plurality of workpiece holders to form a sealed treatment space, and a manipulator for automatically equipping the supporting plates of a workpiece holder with workpieces, while the other workpiece holder is covered by the hood to perform the plasma treatment of the workpieces.

Abstract: In order to easily exchange a depleted dielectric member in a substrate processing apparatus, a faraday shield provided opposite to an antenna across a component member made of a dielectric, a first dielectric member provided opposite to the antenna across the component member and the faraday shield, and a second dielectric member provided opposite to the antenna across the component member, the faraday shield, and the first dielectric member are provided, and the second dielectric member is placed on a protrusion part formed on a vacuum container in the substrate processing apparatus.