Product Is Semiconductor Or Includes Semiconductor Patents (Class 205/123)
  • Patent number: 7270734
    Abstract: The invention relates to a method for electroplating a metal deposit on electroplatable portions of composite articles that have both electroplatable and non-electroplatable portions. In this method, the invention is an improvement which comprises treating the articles prior to electroplating to provide the electroplatable portions with enhanced electroplatability. This is achieved by passing a current though a near neutral pH solution that contains a conductivity agent and a buffer to reduce or remove surface oxides and contaminants from such portions without deleteriously affecting the non-electroplatable portions of the articles. When the treated surfaces are subsequently subjected to metal plating, a uniform, smooth metal deposit is achieved.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: September 18, 2007
    Assignee: Technic, Inc.
    Inventors: Robert A. Schetty, III, Kilbnam Hwang
  • Patent number: 7267749
    Abstract: A processing container (610) for providing a flow of a processing fluid during immersion processing of at least one surface of a microelectronic workpiece is set forth. The processing container comprises a principal fluid flow chamber (505) providing a flow of processing fluid to at least one surface of the workpiece and a plurality of nozzles (535) disposed to provide a flow of processing fluid to the principal fluid flow chamber. The plurality of nozzles are arranged and directed to provide vertical and radial fluid flow components that combine to generate a substantially uniform normal flow component radially across the surface of the workpiece. An exemplary apparatus using such a processing container is also set forth that is particularly adapted to carry out an electroplating process.
    Type: Grant
    Filed: March 26, 2003
    Date of Patent: September 11, 2007
    Assignee: Semitool, Inc.
    Inventors: Gregory J. Wilson, Paul R. McHugh, Kyle M. Hanson
  • Patent number: 7254885
    Abstract: A method is used for fabricating sliders for use in a disc drive actuation system, the sliders having bonds pads formed on either a top surface or side faces of the slider. The method comprises providing a substrate having a top surface. Trenches are formed in the substrate and filled with a bond pad material to form slider bond pads. Excess bond pad material is removed from the trenches such that the slider bond pads are flush with the top surface of the substrate. A transducer is fabricated on the top surface of the substrate. Finally, the slider bond pads are exposed.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: August 14, 2007
    Assignee: Seagate Technology, LLC
    Inventors: Roger L. Hipwell, Jr., Wayne A. Bonin, Kyle M. Bartholomew, John R. Pendray, Zine-Eddine Boutaghou
  • Patent number: 7252750
    Abstract: A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.
    Type: Grant
    Filed: September 16, 2003
    Date of Patent: August 7, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Wen Liu, Jung-Chih Tsao, Ke-Wei Chen, Ying-Lang Wang
  • Patent number: 7232513
    Abstract: An electroplating solution contains a wetting agent in addition to a suppressor and an accelerator. In some embodiments, the solution has a cloud point temperature greater than 35° C. to avoid precipitation of wetting agent or other solute out of the plating solution. In some embodiments, the wetting agent decreases the air-liquid surface tension of the electroplating solution to 60 dyne/cm2 or less to increase the wetting ability of the solution with a substrate surface. In some embodiments of a method for plating metal onto substrate surface, the electroplating solution has a measured contact angle with the substrate surface less than 60 degrees.
    Type: Grant
    Filed: June 29, 2004
    Date of Patent: June 19, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Eric G. Webb, Jonathan D. Reid, John H. Sukamto, Yuichi Takada
  • Patent number: 7224039
    Abstract: In accordance with certain embodiments consistent with the present invention, diamond nanoparticles are mixed with polymers. This mixture is expected to provide improved properties in interlayer dielectrics used in integrated circuit applications. This abstract is not to be considered limiting, since other embodiments may deviate from the features described in this abstract.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: May 29, 2007
    Assignee: International Technology Center
    Inventors: Gary E. McGuire, Olga Alexander Shenderova
  • Patent number: 7220347
    Abstract: An electrolytic copper plating bath used for via-filling plating of blind via-holes formed on a substrate, containing a water-soluble copper salt, sulfuric acid, chloride ions, and a leveler as an additive, wherein the leveler is either one or both of a quaternary polyvinylimidazolium compound represented by the following formula (1) and a copolymer, represented by the following formula (2), of vinylpyrrolidone and a quaternary vinylimidazolium compound: where R1 and R2 are each an alkyl group, m is an integer of not less than 2, and p and q are each an integer of not less than 1, and a copper electroplating method for via-filling plating of blind via-holes formed on a substrate by use of the electrolytic copper plating bath.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: May 22, 2007
    Assignee: C. Uyemura & Co., Ltd.
    Inventors: Toshihisa Isono, Shinji Tachibana, Tomohiro Kawase, Naoyuki Omura
  • Patent number: 7217353
    Abstract: After bubbles adsorbed to a substrate are removed by rotating the substrate in a plating solution at a higher speed or after the wettability of the surface of the substrate to be plated is improved before the substrate is immersed in the plating solution, the substrate is rotated in the plating solution at a lower speed so that a plating process is performed with respect to the substrate.
    Type: Grant
    Filed: July 23, 2003
    Date of Patent: May 15, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shuji Hirao
  • Patent number: 7214305
    Abstract: Disclosed is a method of manufacturing an electronic device, comprising forming a concave portion on the surface of a base member, forming an electrically conductive seed layer on that surface of the base member on which a plated film is to be formed, and applying an electrolytic plating treatment with the seed layer used as a common electrode under the condition that a substance for accelerating the electrolytic plating is allowed to be present in the concave portion of the base member in an amount larger than that on the surface of the base member to form a plated film.
    Type: Grant
    Filed: August 8, 2003
    Date of Patent: May 8, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Hisashi Kaneko
  • Patent number: 7211175
    Abstract: Controlled-potential electroplating provides an effective method of electroplating metals onto the surfaces of high aspect ratio recessed features of integrated circuit devices. Methods are provided to mitigate corrosion of a metal seed layer on recessed features due to contact of the seed layer with an electrolyte solution. The potential can also be controlled to provide conformal plating over the seed layer and bottom-up filling of the recessed features. For each of these processes, a constant cathodic voltage, pulsed cathodic voltage, or ramped cathodic voltage can be used. An apparatus for controlled-potential electroplating includes a reference electrode placed near the surface to be plated and at least one cathode sense lead to measure the potential at points on the circumference of the integrated circuit structure.
    Type: Grant
    Filed: February 11, 2003
    Date of Patent: May 1, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Jonathan Reid, Robert Contolini
  • Patent number: 7204918
    Abstract: An improved apparatus for treating plate-like workpieces with a designated chemical solution, including printed circuit boards, includes: (1) a tray for holding the chemical solution, with the tray having an open top which is configured to receive a horizontally-oriented workpiece, with the tray having a top edge with a portion of the edge forming a dam over which the solution may flow and an opening in its lower portion where the solution can enter the tray, (2) a reservoir tank situated below the tray, (3) a feed line connecting the reservoir tank and tray opening, (4) a drain that returns the solution that overflows the tray top edge to the reservoir tank, and (5) a pump that circulates the solution from the tank to the tray and over the horizontally situated workpiece.
    Type: Grant
    Filed: March 10, 2003
    Date of Patent: April 17, 2007
    Assignee: Modular Components National, Inc.
    Inventor: Steven P. Glassman
  • Patent number: 7201829
    Abstract: The present invention includes a mask plate design that includes at least one or a plurality of channels portions on a surface of the mask plate, into which electrolyte solution will accumulate when the mask plate surface is disposed on a surface of wafer, and out of which the electrolyte solution will freely flow. There are also at least one or a plurality of polish portions on the mask plate surface that allow for polishing of the wafer when the mask plate surface is disposed on a surface of wafer.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: April 10, 2007
    Assignee: Novellus Systems, Inc.
    Inventors: Bulent M. Basol, Cyprian Uzoh, Jeff A. Bogart
  • Patent number: 7198705
    Abstract: An improved copper ECD process. After the copper seed layer (116) is formed, a first portion of copper film (118) is plated onto the surface of the seed layer (116). The surface of the first portion of the copper film (118) is then rinsed to equalize the organic adsorption on all sites to prevent preferential copper growth in dense areas. After rinsing, the remaining copper of the copper film (118) is electrochemically deposited.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: April 3, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Linlin Chen, Jiong-Ping Lu, Changfeng Xia
  • Patent number: 7189317
    Abstract: A method for forming a metallization layer. A first layer is formed outwardly from a semiconductor substrate. Contact vias are formed through the first layer to the semiconductor substrate. A second layer is formed outwardly from the first layer. Portions of the second layer are selectively removed such that the remaining portion of the second layer defines the layout of the metallization layer and the contact vias. The first and second layers are electroplated by applying a bi-polar modulated voltage having a positive duty cycle and a negative duty cycle to the layers in a solution containing metal ions. The voltage and surface potentials are selected such that the metal ions are deposited on the remaining portions of the second layer. Further, metal ions deposited on the first layer during a positive duty cycle are removed from the first layer during a negative duty cycle. Finally, exposed portions of the first layer are selectively removed.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: March 13, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Gurtej Singh Sandhu, Chris Chang Yu
  • Patent number: 7179361
    Abstract: The invention includes methods of electrochemically treating semiconductor substrates. The invention includes a method of electroplating a substance. A substrate having defined first and second regions is provided. The first and second regions can be defined by a single mask, and accordingly can be considered to be self-aligned relative to one another. A first electrically conductive material is formed over the first region, and a second electrically conductive material is formed over the second region. The first and second electrically conductive materials are exposed to an electrolytic solution while providing electrical current to the first and second electrically conductive materials. A desired substance is selectively electroplated onto the first electrically conductive material during the exposing of the first and second electrically conductive materials to the electrolytic solution. The invention also includes methods of forming capacitor constructions.
    Type: Grant
    Filed: February 8, 2005
    Date of Patent: February 20, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Dale W. Collins, Richard H. Lane, Rita J. Klein
  • Patent number: 7166232
    Abstract: According to a method for producing a solid body (1) including a microstructure (2), the surface of a substrate (3) is provided with a masking layer (6) that is impermeable to a substance to be applied. The substance is then incorporated into the substrate regions not covered by the masking layer (6). A heat treatment is used to diffuse the substance into a substrate region covered by the masking layer (6) such that a concentration gradient of the substance is created in the substrate region covered by the masking layer (6), proceeding from the edge of the masking layer (6) inward with increasing distance from the edge. The masking layer (6) is then removed to expose the substrate region under this layer, and a near-surface layer of the substrate (3) in the exposed substrate region is converted by a chemical conversion reaction into a coating (9) which has a layer thickness profile corresponding to the concentration gradient of the substance contained in this near-surface layer.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: January 23, 2007
    Assignee: Micronas GmbH
    Inventors: Guenter Igel, Mirko Lehmann
  • Patent number: 7163613
    Abstract: There is provided a semiconductor device comprising: a first plating layer formed on one surface of an interconnect pattern; a second plating layer formed within through holes in the interconnect pattern; a semiconductor chip electrically connected to the first plating layer; an anisotropic conductive material provided on the first plating layer; and a conductive material provided on the second plating layer, wherein the first plating layer has appropriate adhesion properties with the anisotropic conductive material, and the second plating layer has appropriate adhesion properties with the conductive material.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: January 16, 2007
    Assignee: Seiko Epson Corporation
    Inventor: Nobuaki Hashimoto
  • Patent number: 7147827
    Abstract: A chemical control system for controlling the chemistry of a chemical solution having predetermined chemical constituents in a plating system, such as a NiFe plating system, employs a mix container for containing a plating solution and a hold container for containing a plating solution delivered from the mix container. A precision delivery arrangement delivers a precise predetermined quantum of a predetermined constituent of the plating solution to multiple mix containers and the hold containers. Transfer of plating solution between the mix and hold containers is effected by a transfer pump. Nitrogen gas that has been humidified with deionized water protects the plating solution from either acquiring water or becoming dehydrated, the humidified nitrogen gas being humidified to a predetermined relative humidity with respect to the temperature of the plating solution in the mix container. This is achieved by urging the nitrogen gas through a column that is at the same temperature as the plating solution.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: December 12, 2006
    Assignee: Applied Materials, Inc.
    Inventor: Todd Alan Balisky
  • Patent number: 7147766
    Abstract: The present invention relates to a method for fabricating high performance chip interconnects and packages by providing methods for depositing a conductive material in cavities of a substrate in a more efficient and time saving manner. This is accomplished by selectively removing portions of a seed layer from a top surface of a substrate and then depositing a conductive material in the cavities of the substrate, where portions of the seed layer remains in the cavities. Another method includes forming an oxide layer on the top surface of the substrate such that the conductive material can be deposited in the cavities without the material being formed on the top surface of the substrate. The present invention also discloses methods for forming multi-level interconnects and the corresponding structures.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: December 12, 2006
    Assignee: ASM NuTool, Inc.
    Inventors: Cyprian Emeka Uzoh, Homayoun Talieh, Bulent Basol
  • Patent number: 7144490
    Abstract: A method for selective electroplating of a semiconductor input/output (I/O) pad includes forming a titanium-tungsten (TiW) layer over a passivation layer on a semiconductor substrate, the TiW layer further extending into an opening formed in the passivation layer for exposing the I/O pad, such that the TiW layer covers sidewalls of the opening and a top surface of the I/O pad. A seed layer is formed over the TiW layer, and portions of the seed layer are selectively removed such that remaining seed layer material corresponds to a desired location of interconnect metallurgy for the I/O pad. At least one metal layer is electroplated over the remaining seed layer material, using the TiW layer as a conductive electroplating medium.
    Type: Grant
    Filed: November 18, 2003
    Date of Patent: December 5, 2006
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, David E. Eichstadt, Jonathan H. Griffith, Sarah H. Knickerbocker, Rosemary A. Previti-Kelly, Roger A. Quon, Kamalesh K. Srivastava, Keith Kwong-Hon Wong
  • Patent number: 7125458
    Abstract: A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.
    Type: Grant
    Filed: September 12, 2003
    Date of Patent: October 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: Stephen W. Bedell, Kwang Su Choe, Keith E. Fogel, Devendra K. Sadana
  • Patent number: 7118664
    Abstract: The present invention provides a plating method and apparatus, which is capable of introducing plating solution into the fine channels and holes formed in a substrate without needing to add a surface active agent to the plating solution, and capable of forming a high-quality plating film having no defects or omissions. The plating method for performing electrolytic or electroless plating of an object using a plating solution comprises: conducting a plating operation after or while deaerating dissolved gas in the plating solution; and/or conducting a preprocessing operation using a preprocessing solution after or while deaerating dissolved gas in the preprocessing solution and subsequently conducting the plating operation.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: October 10, 2006
    Assignee: Ebara Corporation
    Inventors: Junichiro Yoshioka, Nobutoshi Saito, Tsuyoshi Tokuoka
  • Patent number: 7114251
    Abstract: A method of production of a circuit board able to prevent peeling of a conductive layer during polishing of the conductive layer including the steps of forming at least holes in one surface of a substrate; forming a plating power supply layer on the one surface of the substrate, the other surface, the sides, and inner surfaces of the holes; forming a metal layer formed on the one surface of the substrate, the other surface, and the sides and burying the holes by electroplating through the plating power supply layer; and polishing the metal layer to form interconnect patterns comprised of the metal layer buried in the holes.
    Type: Grant
    Filed: May 15, 2002
    Date of Patent: October 3, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Naohiro Mashino
  • Patent number: 7112268
    Abstract: A plating device and a plating method are provided that are capable of enhancing uniformity in plating on a treatment surface of an object to be treated.
    Type: Grant
    Filed: February 20, 2002
    Date of Patent: September 26, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Wataru Okase, Takenobu Matsuo
  • Patent number: 7105082
    Abstract: A composition for electrodeposition of a metal on a work piece, which electrodeposition is conducted at an electrodeposition temperature, is provided. The composition comprises a metal salt, a polymer suppressor having a cloud point, an accelerator and an electrolyte. If the cloud point is greater than the electrodeposition temperature, an anion is also present in an amount sufficient to lower the cloud point of the polymer suppressor to a temperature approximately no greater than the electrodeposition temperature.
    Type: Grant
    Filed: February 27, 2003
    Date of Patent: September 12, 2006
    Assignee: Novellus Systems, Inc.
    Inventor: Vishwas Hardikar
  • Patent number: 7070687
    Abstract: Apparatus and method for treating a surface of a substrate for electrolytic or electroless plating of metals in integrated circuit manufacturing. In one embodiment the method includes forming a barrier layer on a substrate. A metal-seed layer is then formed on the barrier layer. The method continues by performing in situ surface treatment of the metal-seed layer to form a passivation layer on the metal-seed layer. In another embodiment of a method of this invention, a substrate is provided into an electroplating tool chamber. The substrate has a barrier layer formed thereon, a metal seed layer formed on the barrier layer and a passivation layer formed over the metal seed layer. The method continues by annealing the substrate in forming gas to reduce the passivation layer. A conductive material is deposited on the substrate using an electrolytic plating or electroless plating process.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: July 4, 2006
    Assignee: Intel Corporation
    Inventors: Vinay B. Chikarmane, Chi-Hwa Tsang
  • Patent number: 7070686
    Abstract: In an electrochemical reactor used for electrochemical treatment of a substrate, for example, for electroplating or electropolishing the substrate, one or more of the surface area of a field-shaping shield, the shield's distance between the anode and cathode, and the shield's angular orientation is varied during electrochemical treatment to screen the applied field and to compensate for potential drop along the radius of a wafer. The shield establishes an inverse potential drop in the electrolytic fluid to overcome the resistance of a thin film of conductive metal on the wafer.
    Type: Grant
    Filed: October 21, 2002
    Date of Patent: July 4, 2006
    Assignee: Novellus Systems, Inc.
    Inventors: Robert J. Contolini, Andrew J. McCutcheon, Steven T. Mayer
  • Patent number: 7028399
    Abstract: The present invention provides a process for wiring electrical contact sites, in particular on the surface of an electronic or microelectronic component, with the following steps: applying and patterning at least one dielectric on the component surface; currentlessly depositing a conductor starting layer for producing metal wiring interconnects and substitute contact sites with short-circuit contacts for interconnecting the individual metal wiring interconnects and the corresponding electrical contact sites; reinforcing the conductor starting layer by a common electrodepositing process; and separating the short-circuit contacts for separating the electrical contact sites or the contact sites of the wiring from one another.
    Type: Grant
    Filed: May 14, 2002
    Date of Patent: April 18, 2006
    Assignee: Infineon Technologies AG
    Inventors: Klaus Lowack, Guenter Schmid, Recai Sezi, Ute Zschieschang
  • Patent number: 7025866
    Abstract: Methods for forming microelectronic workpieces used in electrochemical deposition processes, methods of depositing a conductive layer on a microelectronic workpiece, and articles for electrochemical deposition in semiconductor fabrication. One aspect of the invention is directed toward methods for forming microelectronic workpieces that are well-suited for electrochemical deposition processes. On embodiment of such a method comprises depositing a first conductive material on a workpiece to form an electrically conductive first layer that conforms to the workpiece. This embodiment further includes forming a seed region defined by a second layer of a second conductive material on the first layer, and forming a contact region defined by an exposed portion of the first layer that is not covered by the second layer. The contact region can extend around at least a portion of the perimeter of the workpiece.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: April 11, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Dale W. Collins
  • Patent number: 7018548
    Abstract: A high-precision conductive thin film pattern having a high aspect ratio and a method of forming the same are provided. Further, a method of manufacturing a thin film magnetic head, a thin film inductor, and a micro device each including such a conductive thin film pattern is provided. Since a stacked layer structure including two conductive layer patterns formed by plating growth using an underfilm pattern as an electrode film and an intermediate conductive layer pattern sandwiched by the two conductive layer patterns is provided, a thicker conductive thin film pattern is obtained. An intermediate conductive layer covering a first resist frame is formed and, after that, a second resist frame is formed in a position corresponding to the first resist frame. Consequently, without causing inter-mixing, the first and second resist frames can be stacked. Thus, a thicker conductive thin film pattern can be formed easily with high precision.
    Type: Grant
    Filed: July 11, 2003
    Date of Patent: March 28, 2006
    Assignee: TDK Corporation
    Inventor: Akifumi Kamijima
  • Patent number: 7005054
    Abstract: A method to make probes of a probe card includes providing a blocking plate on an electroplating tank. The blocking plate has a plurality of openings according to the layout of contact pads on a probe head. There are bumps on the contact pads of the probe head. Continuous electroplating process can be executed after bumps (contact pads) contact electroplating solution in the electroplating tank through the openings of the blocking plate. By continuously moving the probe head according to the desired shape of probes, probes were formed by electroplating. These probes can be made into different shapes with good uniformity in elasticity and heights to increase the quality of electrical contact during wafer probing. Moreover, the process lead time and fabrication cost are saved.
    Type: Grant
    Filed: August 20, 2002
    Date of Patent: February 28, 2006
    Assignees: Chipmos Technologies (Bermuda) Ltd., Chipmos Technologies Inc.
    Inventors: S. J. Cheng, An-Hong Liu, Yeong-Her Wang, Yuan-Ping Tseng, Y. J. Lee
  • Patent number: 7001498
    Abstract: An electroplating apparatus, in accordance with the present invention, includes a plurality of chambers. A first chamber includes an anode therein. The first chamber has an opening for delivering an electrolytic solution containing metal ions onto a surface to be electroplated. The surface to be electroplated is preferably a cathode. A second chamber is formed adjacent to the first chamber and has a second opening in proximity of the first opening for removing electrolytic solution containing metal ions from the surface to be electroplated. The plurality of chambers are adapted for movement in a first direction along the surface to be electroplated.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: February 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Evan George Colgan, John Christopher Flake, Lubomyr Taras Romankiw, Robert Luke Wisnieff
  • Patent number: 6984302
    Abstract: The invention discloses a method of electroplating a material onto a semiconductor substrate. A substrate is placed in a cylindrical processing chamber enclosure. A nozzle for spraying a liquid electroplating solution opposes the top surface of the substrate. The electroplating solution flows through the nozzle and outward angularly from the tip of the nozzle, so that the solution flows rotationally on the surface of the substrate.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: January 10, 2006
    Assignee: Intel Corporation
    Inventor: Kevin J. Lee
  • Patent number: 6974530
    Abstract: The flow of electrolyte and/or of ions is controlled by a diffuser element provided in a plating reactor, wherein, in one embodiment, the diffuser element comprises a mechanical adjustment mechanism to adjust the effective size of passages of the diffuser element. In another embodiment, the diffuser element comprises at least two patterns of passages that are movable relatively to each other so as to adjust an overlap and thus an effective size of the corresponding passages. Moreover, the path of ions within the plating reactor may be controlled by an electromagnetically driven diffuser element so that a required thickness profile on the workpiece surface may be obtained.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: December 13, 2005
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Matthias Bonkass, Axel Preusse
  • Patent number: 6972081
    Abstract: A process for fabricating a vertical spiral inductor within a multichip module package is disclosed. The process consists of depositing a pattern of bottom lines by electroplating copper on a substrate and then depositing an insulation pattern. Next, depositing a pattern of permeable material to form a core and then depositing polyimide to define vias and permeable core insulation. The vias are filled by electroplating copper. The vertical spiral inductor is formed and defined by next depositing a pattern of top metal (e.g. copper) lines by electroplating wherein the top metal lines are staggered with respect to the bottom metal lines. Lastly a top protective layer is deposited. The core is made from a permeable or non-permeable material.
    Type: Grant
    Filed: February 5, 2003
    Date of Patent: December 6, 2005
    Assignee: Xerox Corporation
    Inventor: Kaiser H. Wong
  • Patent number: 6969308
    Abstract: A polishing device is hermetically accommodated in a chamber containing an atmosphere having a composition different from the ambient air, so that the atmosphere around the polishing device is altered into the composition different from the ambient air, and voltage is applied between a wafer and a polishing pad to polish the wafer with an electrolytic effect. The polishing device has the atmosphere containing extremely less oxygen, preventing a surface of the wafer from oxidation and thereby providing a constant polishing rate.
    Type: Grant
    Filed: May 14, 2003
    Date of Patent: November 29, 2005
    Assignee: Tokyo Seimitsu Co., Ltd.
    Inventors: Toshiro Doi, Takashi Fujita
  • Patent number: 6953522
    Abstract: A contact is disposed to come into contact with a metal layer formed on a substrate being treated, the contact being in contact with a surface being treated from an opposite surface through a through hole present in a substrate. Alternatively, a contact is disposed to come into contact with a metal layer formed on a substrate, the contact coming into contact at an approximate center of the substrate. Alternatively, a plurality of needle bodies are disposed to be in electrical contact with a metal layer of a substrate being treated, thereby power supply for electrolytic polishing/plating to a substrate being treated being implemented, without restricting to a periphery of a substrate, from a plurality of points on a surface thereof. Due to any one of these, liquid treatment equipment enables to improve uniformity in plane of an electric current sent to a surface being treated and of liquid treatment.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: October 11, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Kyungho Park, Wataru Okase, Takenobu Matsuo
  • Patent number: 6951603
    Abstract: A two-layered anode (1?) has a lower layer (2) including a non-conductive carrier material to which a conductive electrode layer (3?) is applied. Non-conductive areas, formed by partial removal of the electrode layer, have a predetermined structure corresponding to the structure of a structured polymer film (11) to be formed. The anode (1?) is connected with a platinum cathode in an electrolyte into which compounds of low molecular weight, preferably monomers of the polymer film (11), are introduced. During current flow, a conductive polymer film (11) of the predetermined structure is formed on conductive areas brought into contact with the electrolyte. A non-conductive substrate layer (13) is applied to the structured polymer film (11). The structured polymer film (11) adheres to the non-conductive substrate layer (13) and can be released from the electrode (1?) without damaging the electrode.
    Type: Grant
    Filed: August 21, 2002
    Date of Patent: October 4, 2005
    Assignee: Technische Universitat Braunschweig
    Inventors: Eike Becker, Hans-Hermann Johannes, Wolfgang Kowalsky
  • Patent number: 6946065
    Abstract: Several techniques are described for reducing or mitigating the formation of seams and/or voids in electroplating the interior regions of microscopic recessed features. Cathodic polarization is used to mitigate the deleterious effects of introducing a substrate plated with a seed layer into an electroplating solution. Also described are diffusion-controlled electroplating techniques to provide for bottom-up filling of trenches and vias, avoiding thereby sidewalls growing together to create seams/voids. A preliminary plating step is also described that plates a thin film of conductor on the interior surfaces of features leading to adequate electrical conductivity to the feature bottom, facilitating bottom-up filling.
    Type: Grant
    Filed: November 16, 2000
    Date of Patent: September 20, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Vijay Bhaskaran, Evan E. Patton, Robert L. Jackson, Jonathan Reid
  • Patent number: 6946066
    Abstract: The present invention relates to a method for forming a planar conductive surface on a wafer. In one aspect, the present invention uses a no-contact process with electrochemical deposition, followed by a contact process with electrochemical mechanical deposition.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: September 20, 2005
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Cyprian E. Uzoh, Homayoun Talieh
  • Patent number: 6936153
    Abstract: A semiconductor workpiece holder used in electroplating systems for plating metal layers onto a semiconductor workpieces, and is of particular advantage in connection with plating copper onto semiconductor materials. The workpiece holder includes electrodes which have a contact face which bears against the workpiece and conducts current therebetween. The contact face is provided with a contact face outer contacting surface which is made from a contact face material similar similar to the workpiece plating material which is to be plated onto the semiconductor workpiece. The contact face can be formed by pre-conditioned an electrode contact using a plating metal which is similar to the plating materials which is to be plated onto the semiconductor workpiece.
    Type: Grant
    Filed: September 30, 1997
    Date of Patent: August 30, 2005
    Assignee: Semitool, Inc.
    Inventor: Thomas L. Ritzdorf
  • Patent number: 6936154
    Abstract: The methods and systems described provide for an in-situ detection of planarity of a layer that is deposited on or etched off the surface of a substrate. Planarity can be detected using various detection mechanisms, including optical, electrical, mechanical and acoustical, in combination with the electrochemical mechanical processing methods, including electrochemical mechanical deposition and electrochemical mechanical etching. Once planarity is detected, a planarity signal can be used to terminate or alter a process that has been previously initiated, or begin a new process. In a preferred embodiment, an optical detection system is used to detect planarity during the formation of planar conductive layers obtained by electrochemical mechanical processing.
    Type: Grant
    Filed: December 7, 2001
    Date of Patent: August 30, 2005
    Assignee: ASM Nutool, Inc.
    Inventors: Bulent M. Basol, Cyprian E. Uzoh
  • Patent number: 6926818
    Abstract: A method of forming a bump structure through the use of an electroplating solution, comprising the following steps. A substrate having an overlying conductive structure is provided. A patterned dry film resist is formed over the conductive structure. The patterned dry film resist having a trench exposing a portion of conductive structure. The patterned dry film resist adhering to the conductive structure at an interface. The structure is treated with a treatment that increases the adherence of the patterned dry film resist to the conductive structure at the interface. A conductive plug is over the exposed portion of the conductive structure within the trench through the use of the electroplating solution. The increased adhesion of the patterned dry film resist to the conductive structure at the interface preventing the electroplating solution from penetrating the interface of the patterned dry film resist and the conductive structure during the formation of the conductive plug.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: August 9, 2005
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yih-Ann Lin, Tung-Heng Shie, Kai-Ming Ching, Sheng-Liang Pan, Kuo-Liang Lu
  • Patent number: 6921551
    Abstract: The present invention relates to methods and apparatus for plating a conductive material on a workpiece surface in a highly desirable manner. Using a workpiece-surface-influencing device, such as a mask or sweeper, that preferentially contacts the top surface of the workpiece, relative movement between the workpiece and the workpiece-surface-influencing device is established so that an additive in the electrolyte solution disposed on the workpiece and which is adsorbed onto the top surface is removed or otherwise its amount or concentration changed with respect to the additive on the cavity surface of the workpiece. Plating of the conductive material can place prior to, during and after usage of the workpiece-surface-influencing device, particularly after the workpiece surface influencing device no longer contacts any portion of the top surface of the workpiece, to achieve desirable semiconductor structures.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: July 26, 2005
    Assignee: ASM Nutool, Inc.
    Inventor: Bulent M. Basol
  • Patent number: 6919013
    Abstract: A process for applying a metallization interconnect structure to a semiconductor workpiece having a barrier layer deposited on a surface thereof is set forth. The process includes the forming of an ultra-thin metal seed layer on the barrier layer. The ultra-thin seed layer having a thickness of less than or equal to about 500 Angstroms. The ultra-thin seed layer is then enhanced by depositing additional metal thereon to provide an enhanced seed layer. The enhanced seed layer has a thickness at all points on sidewalls of substantially all recessed features distributed within the workpiece that is equal to or greater than about 10% of the nominal seed layer thickness over an exteriorly disposed surface of the workpiece.
    Type: Grant
    Filed: February 3, 2003
    Date of Patent: July 19, 2005
    Assignee: Semitool, Inc.
    Inventor: LinLin Chen
  • Patent number: 6916412
    Abstract: An electrochemical processing chamber which can be modified for treating different workpieces and methods for so modifying electrochemical processing chambers. In one particular embodiment, an electrochemical processing chamber 200 includes a plurality of walls 510 defining a plurality of electrode compartments 520, each electrode compartment having at least one electrode 600 therein, and a virtual electrode unit 530 defining a plurality of flow conduits, with at least one of the flow conduits being in fluid communication with each of the electrode compartments. This first virtual electrode unit 530 may be exchanged for a second virtual electrode unit 540, without modification of any of the electrodes 600, to adapt the processing chamber 200 for treating a different workpiece.
    Type: Grant
    Filed: June 5, 2001
    Date of Patent: July 12, 2005
    Assignee: Semitool, Inc.
    Inventors: Daniel J. Woodruff, Kyle M. Hanson, Steve L. Eudy, Curtis A. Weber, Randy Harris
  • Patent number: 6913681
    Abstract: A cathode potential is applied to a conductive layer formed on a substrate having a depression pattern. A plating solution in electrical contact with an anode is supplied to the conductive layer to form a plating film on the conductive layer. At this time, the plating solution is supplied by causing an impregnated member containing the plating solution to face the conductive layer. Since the plating solution stays in the depression, a larger amount of plating solution is supplied than on the upper surface of the substrate, and the plating rate of the plating film in the depression increases. Consequently, the plating film can be preferentially formed in the depression such as a groove or hole.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: July 5, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tetsuo Matsuda, Hisashi Kaneko, Katsuya Okumura
  • Patent number: 6896784
    Abstract: A process for electroplating metallic features of different density on a surface of a substrate comprises providing an electroplating bath having an anode, immersing the substrate into the electroplating bath, spaced from the anode, the substrate comprising a cathode. Positioned in the electroplating bath between the substrate and the anode, and adjacent to and separated from the substrate surface is a second cathode that includes a wire mesh screening portion having openings of different sizes conforming to the metallic features to be electroplated. The second cathode screening portion has openings of larger size adjacent areas of higher density of features to be electroplated and openings of smaller size adjacent areas of lower density of features to be electroplated.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: May 24, 2005
    Assignee: International Business Machines Corporation
    Inventors: Tien-Jen Cheng, Todd M. Fowler, Ajay P. Giri, Anton Nenadic, Blessen Samuel, Keith Kwong Hon Wong
  • Patent number: 6893550
    Abstract: The present invention relates to a copper electroplating bath composition and method of using it for microelectronic device fabrication. In particular, the present invention relates to copper electroplating in the fabrication of interconnect structures in semiconductor devices. By use of the inventive copper electroplating bath composition, the incidence of voids in the interconnect structures is reduced.
    Type: Grant
    Filed: October 3, 2001
    Date of Patent: May 17, 2005
    Assignee: Intel Corporation
    Inventors: Valery Dubin, Kimin Hong, Nate Baxter
  • Patent number: 6878259
    Abstract: A smooth layer of a metal is electroplated onto a microrough electrically conducting substrate by immersing the substrate and a counterelectrode in an electroplating bath of the metal to be electroplated and passing a modulated reversing electric current between the electrodes. The current contains pulses that are cathodic with respect to said substrate and pulses that are anodic with respect to said substrate. The cathodic pulses have a duty cycle less than about 50% and said anodic pulses have a duty cycle greater than about 50%, the charge transfer ratio of the cathodic pulses to the anodic pulses is greater than one, and the frequency of said pulses ranges from about 10 Hertz to about 12000 Hertz. The plating bath is substantially devoid of levelers and may be devoid of brighteners.
    Type: Grant
    Filed: April 3, 2001
    Date of Patent: April 12, 2005
    Assignee: Faraday Technology Marketing Group, LLC
    Inventors: E. Jennings Taylor, Chengdong Zhou, Jenny J. Sun