Abstract: A gas chromatograph having a gas inlet port, a sealed fluid flow channel, a gas outlet port, a gas outlet port in fluid connection with a second end of the fluid flow channel, and a gas molecule detector in fluid connection with the gas outlet port, is disclosed. The first end of the sealed fluid flow channel is in fluid connection with the gas inlet port. The sealed fluid flow channel contains one or more pairs of electrodes running lengthwise along the inner surface of the fluid flow channel.

Abstract: A process for laser forming a blind via in at least one layer of a circuit substrate having a plurality of capture pads of varying geometry can include, for at least one blind via to be formed in at least one layer of a circuit substrate, evaluating a capture pad geometry value (such as area and/or volume) within a predetermined distance from a drilling location with respect to a blind via geometry value (such as area and/or volume) to be formed at the drilling location. The process can include setting at least one laser operating parameter based on the evaluation in order to obtain a desired capture pad appearance after blind via formation. The process can include imaging a capture pad area defined as an area within a predetermined distance from a blind via drilling location in at least one layer of a circuit substrate, quantifying at least one appearance value for the imaged capture pad area, and determining an acceptability of the imaged capture pad areas based on the quantified appearance value.

Abstract: Switchable and/or tunable filters, methods of manufacture and design structures are disclosed herein. The method of forming the filters includes forming at least one piezoelectric filter structure comprising a plurality of electrodes formed on a piezoelectric substrate. The method further includes forming a fixed electrode with a plurality of fingers on the piezoelectric substrate. The method further includes forming a moveable electrode with a plurality of fingers over the piezoelectric substrate. The method further includes forming actuators aligned with one or more of the plurality of fingers of the moveable electrode.

Abstract: This disclosure provides systems, methods and apparatus for glass electromechanical systems (EMS) electrostatic devices. In one aspect, a glass EMS electrostatic device includes sidewall electrodes. Structural components of a glass EMS electrostatic device such as stationary support structures, movable masses, coupling flexures, and sidewall electrode supports, can be formed from a single glass body. The glass body can be a photochemically etched. In some implementations, pairs of sidewall electrodes can be arranged in interdigitated comb or parallel plate configurations and can include plated metal layers and narrow capacitive gap spacing.

Abstract: The invention relates to a method of manufacturing an electrostatic clamp configured to electrostatically clamp an article to an article support in a lithographic apparatus. The method includes providing a first layer of material, etching a recess in the first layer of material, and disposing an electrode in the recess of the first layer of material.

Abstract: An exemplary method for manufacturing a circuit board includes, firstly, providing a substrate made of heat conductive, electrically insulative material. Then a copper layer is formed on the substrate. After that, nickel is plated on the copper layer to form a nickel layer. Finally, gold is and plated on the nickel layer to form a gold layer.

Abstract: Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

Abstract: Fundamental interconnect systems for connecting high-speed electronics elements are provided. The interconnect systems consists of signal line, dielectric system with open trench or slot filled up with air or lower dielectric loss material, and the ground plane. The signal line could be for example, microstripline, strip line, coplanar line, single line or differential pairs. The interconnect system can be used for on-chip interconnects or can also be used for off-chip interconnects. The fundamental techniques provided in this invention can also be used for high-speed connectors and high-speed cables.

Abstract: A compact touch sensor and a touch sensor stack are disclosed. The touch sensor can include a touch sensor circuit integrated with a ground layer on a single substrate. The touch sensor circuit can include two sets of conductive traces separated by a first insulation layer. A second insulation layer can be deposited over the top set of conductive traces of the touch sensor circuit. One or more vias can be included within the first insulation layer to route one or more conductive traces through the first insulation layer. One or more vias can also be included within the substrate to couple one or more conductive traces to the grounding layer. The touch sensor can be laminated to a cover material to form the touch sensor stack. Processes for making the touch sensor and touch sensor stack are also disclosed.

Abstract: Adjacent elementary cells are connected in series by connecting elements, each of which is arranged in an interconnection area. The connecting elements are separated from the respective electrolytic membranes of the two adjacent cells to be connected thereby. In this way, they are never in contact with these electrolytic membranes. For one of the two cells, the connecting element is separated from the electrolytic membrane by an empty space, whereas for the other cell, it is separated from the electrolytic membrane by a thin barrier layer designed to act as buffer area for variations in volume of said membrane when the cell is in operation. The thin barrier layer is formed by a polymer material having a lower water absorption capacity than that of the polymer material constituting the electrolytic membrane of the cell.

Abstract: The present invention relates to a method for filling a through hole of a substrate with a metal. The method includes a step of preparing a bonded substrate including a first substrate having conductivity in at least a surface thereof and a second substrate having a through hole, both substrates being bonded to each other through a nonionic surfactant; a step of exposing, in the bonded surface of the bonded substrate, the conductive surface of the first substrate, which is positioned at the bottom of the through hole, by removing the nonionic surfactant positioned at the bottom of the through hole of the second substrate; and a step of filling the through hole with a metal by applying an electric field to the conductive surface of the first substrate.

Abstract: The various embodiments of the present invention provide a stress-relieving, second-level interconnect structure that is low-cost and accommodates TCE mismatch between low-TCE packages and PCBs. The various embodiments of the interconnect structure are reworkable and can be scaled to pitches from about 1 millimeter (mm) to about 150 micrometers (?m). The interconnect structure comprises a dielectric body element and at least one interconnection array that provides a conductive path between two electronic components. Each interconnection array comprises a plurality of wires that provide both conductivity and compliance to the overall interconnect structure. The versatility and scalability of the interconnect structure of the present invention make it a desirable structure to utilize in current two-dimensional and ever-evolving three-dimensional IC structures.

Abstract: The thermoelectric device includes a first leg made from a first material, anchored at the level of its first end to a support, and a second leg made from a second material, anchored at the level of its first end to said support. In addition, an electric connecting element provided with first and second contact areas is respectively in electric contact with the first leg and second leg so as to form a thermocouple. The device includes means for varying the position of the first and contact areas at the level of the first and second legs.

Abstract: An embodiment of the disclosure provides an anisotropic conductive film including an insulating substrate and a plurality of conductive polymer pillars. The insulating substrate has a first surface and a second surface. Each of the conductive polymer pillars passes through the insulating substrate and is exposed at the first surface and the second surface, and the conductive polymer pillars include an intrinsically conducting polymer.

Abstract: A heating element mounting substrate includes a substrate including a first surface and a second surface, a plurality of wiring patterns formed on the first surface of the substrate, and a plurality of filled portions including a conductive material filled in a plurality of through-holes, the plurality of through-holes penetrating through the substrate in a thickness direction. At least one of the plurality of wiring patterns has an area of not less than 30% of an area of the first surface of the substrate. The plurality of filled portions includes non-overlapping portions that extend from the plurality of wiring patterns as viewed from the first surface side of the substrate, areas of the plurality of filled portions overlapped with the plurality of wiring patterns are not less than 50% of respective areas of the corresponding wiring patterns as viewed from the second surface side of the substrate.

Abstract: A heating element mounting substrate includes a substrate including a first surface and a second surface, a plurality of wiring patterns formed on the first surface of the substrate, and a plurality of filled portions including a conductive material filled in a plurality of through-holes, the plurality of through-holes penetrating through the substrate in a thickness direction. At least one of the plurality of wiring patterns has an area of not less than 30% of an area of the first surface of the substrate. Areas of the plurality of filled portions overlapped with the plurality of wiring patterns are not less than 50% of respective areas of the corresponding wiring patterns as viewed from the second surface side of the substrate.

Abstract: Lithography method for etching very dense patterns on a substrate, based on a combination of several less dense partial patterns; a sacrificial layer is formed on a substrate and is etched according to a first partial pattern; spacers are formed on edges of elements of the sacrificial layer, the spacers defining a second partial pattern; then the sacrificial layer is removed leaving only the spacers remaining A layer sensitive to an electron beam is subsequently deposited between the spacers to a thickness less than or equal to the height of the spacers, and this sensitive layer is exposed using an electron beam according to a third partial pattern such that there remains on the substrate a final pattern of regions lacking spacers and a sensitive layer, this pattern resulting from the combination of the second and third partial patterns and having higher density than each of the partial patterns.

Abstract: There is provided that a substrate comprising a glass substrate 2 constituted by a glass including a silicon oxide. The glass substrate has a through-hole 3 communicating with a front surface and a rear surface of the glass substrate, and filled with a metal material. The substrate is realized by forming an anchor part by selectively etching a silicon oxide on a sidewall surrounding an inside of said through-hole 3 before filling the metal material and by filling the inside of said through-hole 3 with the metal material after forming the anchor part.

Abstract: A coplanar waveguide transition includes a substrate, a first coplanar waveguide on a first side of the substrate, and a second coplanar waveguide on a second side of the substrate. The coplanar waveguide transition includes a first, a second, and a third via through the substrate electrically coupling the first coplanar waveguide to the second coplanar waveguide. The coplanar waveguide transition includes voids through the substrate between the first, second, and third vias and edges of the first coplanar waveguide and edges of the second coplanar waveguide.

Abstract: The present invention relates to an electrode for an energy storage and a method for manufacturing the same and provides a useful effect of improving resistance characteristics of an electrode for an energy storage by forming a trench of predetermined dimensions on a surface of a current collector, forming a conductive layer, which includes a conductive agent as much as possible, on the surface of the current collector, and forming an electrode layer including an electrode active material, a conductive agent, and a binder on the conductive layer.

Abstract: In an integrated circuit (IC) adapted for use in a stack of interconnected ICs, interrupted through-silicon-vias (TSVs) are provided in addition to uninterrupted TSVs. The interrupted TSVs provide signal paths other than common parallel paths between the ICs of the stack. This permits IC identification schemes and other functionalities to be implemented using TSVs, without requiring angular rotation of alternate ICs of the stack.

Abstract: An opening in a substrate is formed, e.g., using optical lithography, with the opening having sidewalls whose cross section is given by segments that are contoured and convex. The cross section of the opening may be given by overlapping circular regions, for example. The sidewalls adjoin at various points, where they define protrusions. A layer of polymer including a block copolymer is applied over the opening and the substrate, and allowed to self-assemble. Discrete, segregated domains form in the opening, which are removed to form holes, which can be transferred into the underlying substrate. The positions of these domains and their corresponding holes are directed to predetermined positions by the sidewalls and their associated protrusions. The distances separating these holes may be greater or less than what they would be if the block copolymer (and any additives) were to self-assemble in the absence of any sidewalls.

Abstract: A multiple layered apparatus and method for forming a z-axis interconnect is provided. The multiple layered apparatus comprises a protective layer, a dielectric layer, a conductive layer, and a support layer. A method for forming a z-axis interconnect using the multiple layer apparatus resulting in a thinner and less expensive structure for printed circuit board applications.

Abstract: This disclosure provides systems, methods and apparatus for providing electrical connections through glass substrates. In one aspect, a through-glass via including a peripheral through-glass via hole and sidewall metallization is provided. Sidewall metallization can include multiple conductive lines facilitating increased interconnect density. In another aspect, one or more methods of forming peripheral through-glass vias are provided. In some implementations, the methods include double-sided processes to form aligned via holes in a glass substrate that together form a through-glass via hole, followed by sidewall metallization and dicing through the through-glass via hole.

Abstract: Provided is a plating method of a circuit substrate comprising a conductive pattern in which a metal layer containing at least silver and copper is exposed on an outer surface. The plating method comprises: step (A) of treating the circuit substrate with a first liquid agent containing an oxidizing agent; step (B) of treating the circuit substrate after the step (A) with a second liquid agent which dissolves copper oxide, and thereby removing copper oxide from the conductive pattern's surface; step (C) of treating the circuit substrate after the step (B) with a third liquid agent whose rate of dissolving silver oxide (I) at 25° C. is 1000 times or more faster than its rate of dissolving copper (0) at 25° C., and thereby removing silver oxide from the conductive pattern's surface; and step (D) of performing electroless plating on the conductive pattern of the circuit substrate after the step (C).

Abstract: A method for manufacturing printed circuit board includes steps below. A first electrically conductive layer including a first surface and a second surface at an opposite side thereof to the first surface is provided. A number of first traces directly formed on the second surface. A first insulating layer is formed on the second surface of the first electrically conductive layer and the surface of the first traces. The electrically conductive layer is etched to form a number of second traces, the second traces superpose the first traces, the first traces and the second traces constitute a circuit pattern.

Abstract: A method of making templated circuitry employs a template system that includes a template of an insulator material on a carrier having a conductive surface. The template includes multiple levels and multiple regions, wherein a first level exposes the conductive surface of the carrier. A first metal is electrochemically deposited on the conductive surface in first regions of the first level. A circuit material is deposited to cover the first metal. The template is etched until a second level of the template exposes the conductive surface in second regions on opposite sides of the first regions. A second metal is electrochemically deposited on the conductive surface in the second regions. The template of deposited materials is transferred from the carrier to a substrate.

Abstract: A method for fabricating a pixel structure includes providing a substrate having a pixel area. A first metal layer, a gate insulator and a semiconductor layer are formed on the substrate and patterned by using a first half-tone mask or a gray-tone mask to form a transistor pattern, a lower capacitance pattern and a lower circuit pattern. Next, a dielectric layer and an electrode layer both covering the three patterns are sequentially formed and patterned to expose a part of the lower circuit pattern, a part of the lower capacitance pattern and a source/drain region of the transistor pattern. A second metal layer formed on the electrode layer and the electrode layer are patterned by using a second half-tone mask or the gray-tone mask to form an upper circuit pattern, a source/drain pattern and an upper capacitance pattern. A portion of the electrode layer constructs a pixel electrode.

Abstract: A method for manufacturing an embedded wiring board is provided. An activating insulation layer is formed. The activating insulation layer includes a plurality of catalyst particles, and covers a first wiring layer. An intaglio pattern and at least one blind via partially exposing the first wiring layer are formed on the activating insulation layer, in which some of the catalyst particles are activated and exposed in the intaglio pattern and the blind via. The activating insulation layer is dipped in a first chemical plating solution, and a solid conductive pillar is formed in the blind via through electroless plating. The activating insulation layer is dipped in a second chemical plating solution after the solid conductive pillar is formed, and a second wiring layer is formed in the intaglio pattern through the electroless plating. Components of the first chemical plating solution and the second chemical plating solution are different.

Abstract: Methods are provided for creating a metal or other electrically-conductive member extending from an air-backed cavity of a piezoelectric ultrasonic transducer (pMUT) apparatus defining such an air-backed cavity, through a substrate layer disposed adjacent to the transducer device of the pMUT device, and into electrically-conductive engagement with a first electrode of the pMUT device, such that the electrically-conductive member provides an electrically-conductive engagement between the first electrode and a conformal electrically-conductive layer deposited in the air-backed cavity of the pMUT device. Associated apparatuses are also provided.

Abstract: Methods of fabricating an integrated circuit device, such as a thin film resistor, are disclosed. An exemplary method includes providing a semiconductor substrate; forming a resistive layer over the semiconductor substrate; forming a hard mask layer over the resistive layer, wherein the hard mask layer includes a barrier layer over the resistive layer and a dielectric layer over the barrier layer; and forming an opening in the hard mask layer that exposes a portion of the resistive layer.

Abstract: The present invention discloses an etchant for etching at least two different metal layers, the etchant comprising hydrogen peroxide (H2O2) and one of carboxylic acid, carboxylate salt, and acetyl group (CH3CO—). The present invention also discloses a method of fabricating a metal wiring on a substrate, the method comprising forming a first metal layer on a substrate, forming a second metal layer on the first metal layer, and simultaneously etching the first metal layer and the second metal layer with an etchant comprising hydrogen peroxide (H2O2) and one of carboxylic acid, carboxylate salt, and acetyl group (CH3CO—).

Abstract: A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.

Abstract: Various embodiments of millimeter-wave systems on a printed circuit board, including a microstrip, a probe, and an RF integrated circuit, as well as methods for manufacturing said systems. Various embodiments have holes extending through lamina in the PCB, thereby improving radiation propagation. Various embodiments have conductive cages created by multiple through-holes extending through lamina in the PCB, thereby increasing radiation propagation. The manufacture of such systems is easier and less expensive than the manufacture of current systems.

Abstract: A metal interconnect structure, which includes a bond pad, an overlying anti-reflective coating layer, an overlying passivation layer, and an opening that exposes a top surface of the bond pad, eliminates corrosion resulting from the anti-reflective layer being exposed to moisture during reliability testing by utilizing a side wall spacer in the opening that touches the side wall of the passivation layer, the side wall of the anti-reflective coating layer, and the top surface of the bond pad.

Abstract: A method of forming printed circuit boards and packaging substrates. After blind vias are created in a dielectric layer, a first seed layer is provided in the vias and on the dielectric layer. Copper is applied to fill the vias and to form a copper layer over the vias and over the first seed layer. The first seed layer and the copper layer are removed and a second seed layer is formed on the dielectric layer and the exposed surfaces of the vias. A wire pattern is then formed using a photo-sensitive thin film applied to the second seed layer, and the wires in the wire pattern are thickened. The photo-sensitive thin film and the exposed portions of the second seed layer are removed to form a first conductive pattern of wires. The process may be repeated to form a second conductive pattern of wires on the first pattern.

Abstract: A method for manufacturing a wiring structure of a wiring board is provided. In the method, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, a barrier layer completely covering the film is formed. Next, an intaglio pattern partially exposing the insulation layer is formed on an outer surface of the barrier layer. Next, an activated layer is formed on the outer surface and in the intaglio pattern. Then, the activated layer on the outer surface is removed, and the activated layer in the intaglio pattern is remained. After the activated layer on the outer surface is removed, a conductive material is formed in the intaglio pattern by using a chemical deposition method. After forming the conductive material, the barrier layer and the film are removed.

Abstract: A process is provided for producing at least one interconnecting well to achieve a conductive pathway between at least two connection layers of a component comprising a stack of at least one first substrate and one second substrate which are electrically insulated from one another, the process including defining a surface contact region of a surface connection layer over a surface of the stack and of at least one first contact region embedded in the stack starting from a first embedded connection layer of the first substrate. A region devoid of material is positioned between the first substrate and second substrates and which comprises a stage of producing a interconnecting well which passes through the second substrate and extends between the surface contact region and the first embedded contact region and passes through the region devoid of material, and also a first layer which covers the first embedded connection layer.

Abstract: A fabrication method for a multilayer printed circuit board includes: forming a first circuit-forming pattern and a first insulation layer, into which the first circuit-forming pattern is inserted, on a first carrier; forming inner circuit patterns and inner insulation layers over the first insulation layer, and forming inner vias connecting the inner circuit patterns positioned on different insulation layers; forming a second circuit-forming pattern on a second carrier and inserting the second circuit-forming pattern into a second insulation layer on an outermost side; removing the first carrier and the second carrier; forming circuit-forming grooves by removing the first circuit-forming pattern and the second circuit-forming pattern, and forming via-forming indentations connected with the circuit-forming grooves; and forming outer circuit patterns and outer vias by filling the circuit-forming grooves and the via-forming indentations with a conductive material.

Abstract: Provided are a three-dimensional (3D) interconnection structure and a method of manufacturing the same. The 3D interconnection structure includes a wafer that has one side of an inverted V-shape whose middle portion is convex and a lower surface having a U-shaped groove for mounting a circuit, and a first electrode formed to cover a part of the inverted V-shaped one side of the wafer and a part of the U-shaped groove.

Abstract: A method of preparing a thin film on a substrate is described. The method comprises forming an ultra-thin hermetic film over a portion of a substrate using a gas cluster ion beam (GCIB), wherein the ultra-thin hermetic film has a thickness less than approximately 5 nm. The method further comprises providing a substrate in a reduced-pressure environment, and generating a GCIB in the reduced-pressure environment from a pressurized gas mixture. A beam acceleration potential and a beam dose are selected to achieve a thickness of the thin film less than about 5 nanometers (nm). The GCIB is accelerated according to the beam acceleration potential, and the accelerated GCIB is irradiated onto at least a portion of the substrate according to the beam dose. By doing so, the thin film is formed on the at least a portion of the substrate to achieve the thickness desired.

Abstract: A printed circuit board and a method of manufacturing the printed circuit board are disclosed. The printed circuit board can include a first insulation layer, a second insulation layer stacked over the first insulation layer, a circuit pattern and a via land buried in the second insulation layer, and a via made of a conductive material penetrating the first insulation layer and integrated with the via land. The circuit pattern and via land can be buried in the insulation material, and the circuit pattern, via land, and via can be formed simultaneously as an integrated structure. Thus, the electrical reliability between the wiring pattern and the via can be increased, the heat-releasing effect of the via can be improved, and the procedure for forming the circuit patterns, via lands, and vias can be simplified, allowing greater productivity in manufacturing the substrate.

Abstract: In order to provide a method for manufacturing a wiring board free from contact fault, a method of the present invention, which manufactures a wiring board (1) including an Al alloy pad (3) on a base layer (2), a gate insulating film (4) and an interlayer insulating film (5) above the Al alloy pad (3), and a contact hole whose opening part reaches a part of the Al alloy pad (3), includes the steps of: forming a contact hole (7) in the gate insulating film (4) and the interlayer insulating film (5) by dry etching so as to expose, in the contact hole (7), at least part of an end part (20) of the Al alloy pad (3) and a part (10) of the base layer (2) which part (10) is adjacent to at least the part of the end part (20); and removing, after forming the contact hole (7), an electrically nonconductive layer (9) caused on a surface of the Al alloy pad (3) by the dry etching.

Abstract: Methods of forming conductive elements on and in a substrate include forming a layer of conductive material over a surface of a substrate prior to forming a plurality of vias through the substrate from an opposing surface of the substrate to the layer of conductive material. In some embodiments, a temporary carrier may be secured to the layer of conductive material on a side thereof opposite the substrate prior to forming the vias. Structures, including workpieces formed using such methods, are also disclosed.

Abstract: An electrospray ion source for a mass spectrometer includes an electrode comprising at least a first plurality of protrusions protruding from a base, each protrusion of the at least a first plurality of protrusions having a respective tip; a conduit for delivering an analyte-bearing liquid to the electrode; and a voltage source, wherein, in operation of the electrospray ion source, the analyte-bearing liquid is caused to move, in the presence of a gas or air, from the base to each protrusion tip along a respective protrusion exterior so as to form a respective stream of charged particles emitted towards an ion inlet aperture of the mass spectrometer under application of voltage applied to the electrode from the voltage source.

Abstract: A method of manufacturing a printed circuit board includes forming a through hole 2 in an insulating layer 1 having upper and lower faces so as to penetrate between the upper and lower surfaces; allowing a first plated conductor 4 to be deposited at least in the through hole 2 and on the upper and lower surfaces around the through hole; removing the first plated conductor overlying and underlying a periphery of the through hole by etching the first plated conductor 4, while leaving at least the first plated conductor 4 in a mid-portion in a vertical direction within the through hole 2; and forming by semi-additive method a second plated conductor 6 that fills an outer portion than the first plated conductor 4 in the through hole 2, and forms a wiring conductor on the upper and lower surfaces.

Abstract: Disclosed is a method of manufacturing a printed circuit board. The method of manufacturing a printed circuit board having a via for interlayer connection can include forming a circuit pattern on one side of a carrier, pressing one side of the carrier into one side of the insulator, removing the carrier, forming a hole penetrating through the insulator by processing one end of the circuit pattern, and forming a conductive material inside the hole to have the conductive material correspond to the via.

Abstract: A wiring board is provided which can prevent a metal electrode from corroding due to a defect in a transparent conductive electrode covering an end face of an organic insulating film. An active-matrix substrate includes: a glass substrate; a metal wire provided on the glass substrate; a gate insulating film covering the metal wire; an interlayer insulating film covering the gate insulating film; and a transparent electrode formed on the interlayer insulating film. The scanning wire provided with a terminal area where the transparent electrode is laminated directly on the scanning wire. The transparent electrode extends over the terminal area in such a way as to cover an end face of the interlayer insulating film that faces the terminal area and an end face of the gate insulating film that faces the terminal area.

Abstract: A piezoelectric actuator includes a thin film sheet, a first electrode, and a second electrode. The thin film sheet is to physically deform in response to an electric field induced within the thin film sheet. The first electrode is embedded within the thin film sheet. The second electrode is embedded within the thin film sheet, and is interdigitated in relation to the first electrode. The electric field is induced within the thin film sheet via application of a voltage across the first and the second electrodes.

Abstract: In a nano filter structure for breathing and a manufacturing method of the nano filter structure, a semiconductor process technology is used for manufacturing a nano filter structure comprising a top gate, a bottom gate, a plurality of sidewall gates and a plurality of supports. The sidewall gates include a plurality of filterable gratings, and the filterable gratings are controlled precisely to a nanoscale by a semiconductor process technology. Therefore, the nano filterable gratings can be manufactured easily and quickly, and the multilayer design of the filterable gratings enhances the aperture ratio of a filter material, such that users can inhale or exhale easily through the filter material.