Abstract: For filling via holes that extend onto interconnects to be contacted in a semiconductor layer structure, the interconnects are connected to a conductive layer through auxiliary via holes. The via holes are filled with metal by electro-deposition, whereby the interconnects are wired as a cooperating electrode in an electrolyte via an auxiliary contact to the conductive layer. Subsequently, the conductive layer is removed.

Abstract: An area array interconnect device (such as of the TAB type) has a plurality of input/output (I/O) leads for connection to an electronic device such as an IC. The interconnect device also has arrays of lead lines in areas remote from the I/O leads, e.g., central or internal areas, which are connected by vias to ground and/or power pads on corresponding areas of the electronic device.

Abstract: An integrated circuit microwave interconnect is formed upon a surface by disposing a dielectric layer over the surface and patterning the dielectric layer to form a dielectric region. The dielectric region is then surrounded by a surrounding metal layer. In one embodiment the surface may be a non-metal upon which a metal layer is disposed prior to disposing the dielectric layer. In this embodiment an additional metal layer is disposed adjoining the first metal surface on both sides of the dielectric region after patterning the layer to form the dielectric region. Thus, the two metal layers thereby form the surrounding metal layer around the dielectric region. The microwave interconnect may be formed upon the surface of the substrate, above the surface of the substrate in a floating configuration, or in a trench within the substrate.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: In a metal-clad laminate the requirements concerning the mechanical strength are functionally separated from the circuit connection requirement, so as to be able to bring the circuit connection, particularly for signals, "closer" to the electrotechnical characteristics of the chips. For this purpose and without taking account of the mechanical strength of the substrate, the layout miniaturization is optimized. In place of a circuit board (MCM), a laminate which can be built up to a circuit board is produced. The inventive laminate comprises an extremely thin foil with a plurality of extremely small holes simultaneously etched in an etching process. The hole diameter can be reduced by almost an order of magnitude (up to 20 .mu.m), which permits a sub-100 .mu.m technology. Such a laminate is not used as a mechanical support and is only provided for signal guidance. The effect of the miniaturization can be seen in the diameter for the plated-through holes.

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.

Abstract: A predetermined electrical circuit pattern or discrete features composed of discrete, electrically conducting metal pathways and non-conducting spaces therebetween is formed on a dielectric substrate by(1) depositing a continuous layer of an electrically conducting metal on a surface of the substrate,(2) contacting the metal layer with a mask head defining a system of ridges and valleys therein, the ridges corresponding to the pathways of the target electrical circuitry pattern or discrete features and the valleys corresponding to the spaces of the target pattern, the ridges in the mask head contacting the metal layer in sealing arrangement with the portions of the metal layer coming into contact with the ridges, and(3) contacting the metal layer with an etchant to remove the portions of the metal layer in the spaces and thereby form the target electrical circuitry or discrete features pattern.

Abstract: According to the present invention, a method is provided for forming contact vias in an integrated circuit. Initially, a first protective layer is formed on an insulating layer, and an opening is created through the insulating layer where a contact is to be made. A conductive layer is deposited over the protective layer and partially fills the opening, forming a conductive plug in the opening. A second protective layer is then formed over the conductive plug. Portions of the conductive layer which were formed over the first protective layer are removed. During removal of those portions of the conductive layer, the second protective layer protects the conductive plug from damage. The first and second protective layers are then removed, leaving the conductive plug in the opening in the insulating layer. A conductive contact can now be made by depositing a second conductive layer over the conductive plug.