Abstract: A method for forming a through-via in a laminated substrate by laser drilling the through-via in a laminated substrate from a top exposed surface of the substrate to a bottom exposed surface of the substrate using a plurality of laser pulses that are trepanned in a first predetermined pattern. Each pulse trepanned in the first predetermined pattern has a first energy density per pulse. Then, the through-via is laser drilled using a plurality of laser pulses that are trepanned in a second predetermined pattern. Each pulse trepanned in the second predetermined pattern has a second energy density per pulse that is greater than the first energy density per pulse. The second predetermined pattern is within the first predetermined pattern.

Abstract: A method of making a laminated substrate by forming a registration mark on a core layer of the substrate. Then, forming a first layer on the core layer using the registration mark as a fiducial registration point. The first layer is laser drilled through to expose the registration mark on the core layer. A second layer is then formed on the first layer using the registration mark as a fiducial point.

Abstract: A method of performing a lower temperature bonding technique to bond together two mating pieces of glass includes applying a sodium silicate aqueous solution between the two pieces.

Abstract: A metal-clad laminate product including a carrier film, a release agent layer, a semi-transparent metal layer and a photo dielectric layer deposited on the conductive metal layer and a method for using the metal-clad laminate product to form an interlayer via by exposing at least a portion of an circuit board intermediate prepared from the metal-clad laminate product to light through the semi-transparent metal layer for a period of time sufficient to form an exposed or an unexposed photo dielectric portion and thereafter removing the exposed or unexposed portion of the photo dielectric layer and a corresponding portion of the semi-transparent metal layer overlying the exposed or unexposed portion of the photo dielectric layer to form an interlayer via.

Abstract: A method of forming circuit lines on a substrate by applying a roughened conductive metal layer using a copper foil carrier. The copper foil is etched away, leaving the roughened conductive metal embedded in the surface of the substrate. The conductive metal may be treated to remove an oxide layer. A photoresist may also be applied over the treated conductive metal layer to define a fine line circuit pattern. The photoresist defining the fine line circuit pattern is then removed to expose trenches in accordance with the desired circuit pattern. Copper is applied into the trenches over the exposed conductive metal, and the remaining photoresist, and conductive metal underlying the remaining photoresist, is removed to finish the fine line circuit pattern.

Abstract: The present invention is directed to methods of creating a cavity to contain an interconnect leading to a location within a substrate. The substrate has a first dielectric layer of a first etch rate over the location, and a semiconductor device containing the interconnect. One of the methods includes the steps of: forming a second dielectric layer on the first dielectric layer wherein the second dielectric layer has a second etch rate that is slower than the first etch rate, forming a photoresist layer on the second dielectric layer and etching into the first and second dielectric layers to form the cavity leading to the location. The second dielectric layer acts as a profile guiding layer to form a plug and runner simultaneously in a single etching step while controlling relative size of the plug and runner.

Abstract: A via for an electronic assembly. The assembly includes a substrate which has a via hole. The via hole is filled with a conductive material that extends across a diameter of the hole. The via hole can be filled by reflowing a solder ball that is attached to an outer surface of the substrate. The substrate may be part of a multi-layered integrated circuit package, wherein the vias couples internal routing layers with external contacts of the package. The filled vias can withstand extended thermal life cycles of the package.

Abstract: A three-dimensional multi-layer electronic device and method for manufacturing same, wherein the device comprises a three-dimensional substrate including a conductive trace on at least one surface of the substrate, a thin layer of dielectric material substantially covering a desired portion of the conductive trace(s) on the substrate, the dielectric layer including vias at selected locations, and applying a coating of conductive material on the dielectric layer and in the vias, and defining a conductive trace in the material to thereby form a multi-layer, interconnected three-dimensional electronic device. Additional layers of dielectric material and conductive traces may be similarly applied to create the desired number of circuit layers. Molded-in structural features, and/or vias may be defined in the appropriate layers to accommodate the attachment and/or interconnection of other electronic devices to the device.

Abstract: A method for fabricating a bump forming plate member by which bumps can be formed on an electronic component. A mask is formed on a surface of a crystalline plate, and the crystalline plate is subjected to anisotropic etching to form a plurality of grooves. The crystalline plate is also subjected to isotropic etching to deepen the grooves. The method can further includes additional anisotropic and isotropic etchings. Also, a method for fabricating a metallic bump forming plate member is disclosed. This method uses the above described crystalline plate having the grooves, and includes fabrication of a replica using the crystalline plate as an original, and fabrication of a metallic bump forming plate member using the replica as an original.

Abstract: A semiconductor package includes a laminate of substrates having a cavity 16, through-holes 25 and circuit patterns, wherein the through-holes 45 and some of the circuit patterns 18 are coated with a plated nickel/gold coating 50.

Abstract: Conductive vias in integrated circuit ceramic greensheets are formed with essentially flat exposed surfaces by applying an adherent in situ mask material to the greensheet prior to punching via openings therethrough. The in situ mask material then serves to permit the application of a second overprint conductive paste after the original conductive paste has filled the via opening and formed a depression upon hardening. The second overprint paste fills the depression and leaves an essentially flat top surface. When the in-situ mask material is removed, a slight protuberance of conductive paste remains in a plane vacated by the in-situ mask material (with or without the second conductive paste application). In one form of the invention, this protuberance is compressed back so that it is essentially level with the surrounding ceramic greensheet by the application of pressure thereto, either by a platen or by an adjoining greensheet lamina.

Abstract: A method of fabricating a dual damascene structure is provided comprising forming a photoresist layer on a dielectric layer. A mask including a region that light completely passes over, a region that light partially passes over and a dense region is used for exposure. A development step is carried out to remove the photoresist layer under the region that light completely passes over, to partially remove the photoresist layer under the region that light partially passes over and to leave the photoresist layer under the dense region. The photoresist layer remaining from the forgoing step and the dielectric layer are partially removed to form a via and a trench in the dielectric layer. The via and the trench are filled with metal to form a dual damascene structure.

Abstract: Processes for forming conductive vias between circuit elements formed on either side of a flexible substrate are disclosed. In one embodiment, the inventive process starts with a flexible film polyimide substrate on each side of which is arranged a layer of copper. Both of the copper surfaces are coated with photoresist. Blind vias are then drilled through the top copper layer and substrate using a laser. The photoresist is then exposed (patterned). A plating operation is used to fill the vias with a conductive material. The resist is then developed and the line and pad structures on the surface of the copper layer are plated. The photoresist is then stripped. In a variation of this embodiment, the photoresist is imaged prior to drilling of the vias using a laser. In an alternative embodiment of the inventive process, a through hole is drilled instead of a blind via.

Abstract: The photolithographic etching of contact holes in trenches in an insulator layer over a silicon body is improved by adjusting properly the depth of the trench and the thickness of the photoresist used in the photolithography.

Abstract: Copper interconnects with enhanced electromigration are formed by filling a via/contact hole and/or trench in a dielectric layer with undoped Cu. A Cu layer containing a dopant element, such as Pd, Zr or Sn is deposited on the undoped Cu contact/via and/or line. Annealing is then conducted to diffuse the dopant element into the copper contact/via and/or line to improve its electromigration resistance. CMP is then performed.

Abstract: A single step electroplating process for interconnect via fill and metal line formation on a semiconductor substrate is disclosed. In this process, a barrier layer is formed onto a surface of a substrate that has at least one via and then a conductive layer is formed onto the barrier layer. Next, a photoresist layer is applied and patterned on top of the conductive layer. The via plugs and metal lines are then deposited on the substrate simultaneously using an electroplating process. After the electroplating process is completed, the photoresist and the conductive layer between the deposited metal lines are removed. The process provides a simple, economical and highly controllable means of forming metal interconnect systems while avoiding the difficulties associated with depositing and patterning metal by traditional semiconductor fabrication techniques.

Abstract: This invention describes a method of forming alignment marks which will be preserved after contact holes in a dielectric have been filled with barrier metal and contact metal and the wafer has been planarized. The alignment marks are formed by filling alignment lines, formed in the dielectric when the contact holes are formed, with barrier metal and contact metal. The alignment lines and contact holes are filled with metal at the same time. After the wafer has been planarized, using a method such as chemical mechanical polishing, a small thickness of the dielectric is etched back using vertical dry anisotropic etching which will not remove either the contact metal or barrier metal. This leaves barrier metal and contact metal extending above the plane of the dielectric forming alignment marks. These alignment marks are preserved after subsequent processing steps, such as deposition of a layer of electrode metal.

Abstract: A method of fabricating a hybrid printed circuit board on a dielectric substrate is disclosed. The method comprises the step of masking a first pattern on a first side of the dielectric substrate, and masking a second side of the dielectric layer. Subsequently, the first side of the dielectric layer is etched to form a first conductive pattern. Thereafter, a second pattern is masked on the second side of the dielectric substrate, while masking the first side of the dielectric layer. With the second pattern masked on the second side of the dielectric layer and the and the first side masked, an etching step if performed on the second side of the dielectric layer to form a second conductive pattern.

Abstract: A method for preventing the occurrence of poisoned trenches and vias in a dual damascene process that includes performing a densification process, such as an plasma treatment, on the surface of the exposed dielectric layer around the openings before the openings are filled with conductive material. The densified surface of the dielectric layer is able to efficiently prevent the occurrence of poisoned trenches and vias caused by the outgassing phenomena.

Abstract: A method for minimizing the dimension of a contact forms a thick dielectric layer on a provided substrate first, and then forms a contact on the first dielectric layer and expose the substrate by performing a slope etching process. The contact with the target contact size is obtained by partially removing the thick dielectric layer. Since the target contact size is obtained by a self-aligned method, the upper diameter of the contact is not limited by a conventional fabrication process. Furthermore, after a contact is formed, it is optional to fill the contact with filler. Even after a desired contact is formed in the case that filler is used, the remains of the filler can be either kept or removed depending on the conductivity of the filler.

Abstract: A wiring layer 36A is formed by sputtering, reflowing and patterning of an Al alloy layer on insulating layers 32 and 34 covering the surface of a semiconductor substrate 30. A silicon oxide layer 38 is formed by coating a hydrogen silsesquioxane resin film flatly over the layer 36A and by successive heat treatment. Then a silicon oxide layer 40 is formed on the layer 38 by plasma-enhanced chemical vapor deposition. After formation of the desired connecting hole in an interlayer insulating layer made of a lamination of the layers 38 and 40, a wiring layer 46 connected with the layer 36A via the connecting hole is formed by sputtering, reflowing and patterning of an Al alloy layer. Results of the measurements of the resistance of the via chains having 20000 vias indicated that resistace rise has not been observed. A multi-layered wiring which is highly resistant to stress migration is provided.

Abstract: Protection structures for suppressing plasma damage. Plasma damage is shown to occur primarily during a metal clear portion of a metal etch as opposed to also occurring during the overetch portion of the etch. The protection structures (202) provide a temporary connection between the metal layer (210) being etched and the substrate or a protection device during the clear portion of the etch. This temporary connection (202) is removed as the metal (210) is cleared.

Abstract: There is provided a method of fabricating a semiconductor, including the steps, in sequence, of (a) forming a first interlayer insulating film over a semiconductor substrate, (b) forming an electrically conductive contact hole in the first interlayer insulating film, (c) forming a second interlayer insulating film over the first interlayer insulating film, (d) forming a photosensitive organic film over the second interlayer insulating film, (e) forming a via-hole passing through the photosensitive organic film and the second interlayer insulating film, the via-hole being in vertical alignment with the contact hole, (f) forming a film so that the film covers the photosensitive organic film therewith and fills the via-hole therewith, (g) exposing the film to plasma so that a portion of the film lying over the photosensitive organic film is removed, (h) removing both the photosensitive organic film and the film remaining in the via-hole, and (i) forming a wire above the via-hole.

Abstract: A structure includes a support layer formed of a conductive material, such as a sheet of copper. The support layer has a number of conductive islands isolated from other portions of the support layer by isolation gaps. The support layer is sandwiched between two compound layers each of which is formed of a dielectric layer having a number of via holes and conductive elements located in the via holes. The conductive elements are formed at predetermined locations such that a conductive element in each compound layer contacts a conductive island in the support layer. The structure also includes two conductive layers formed on the two respective compound layers such that a trace in a first conductive layer is coupled to a trace in a second conductive layer through two conductive elements in the respective two compound layers and an island in the support layer. Such a structure can be formed by a number of processes.

Abstract: A method for fabricating a chip carrier, such as a printed circuit board, which includes at least one through hole or via hole, is disclosed. In accordance with this method, an electrically conductive layer is formed on at least one of the major surfaces of the corresponding chip carrier substrate, as well as for the surface of the through hole or via hole. Significantly, the electrically conductive layer on the at least one major surface is relatively thin, which permits the formation of a relatively high density of circuit lines in this layer. On the other hand, the electrically conductive layer on the surface of the through hole or via hole is relatively thick, which prevents the formation of defects in this layer.

Abstract: A method of manufacturing a multilayer circuit substrate includes a process of forming via holes in an insulating film, a process of applying an electrically conducting paste obtained by having ultra-fine metal particles disperse in a solvent onto an insulating film, and a process of forming vias composed of a sintered product of ultra-fine metal particles in the via holes by removing the solvent and also sintering the ultra-fine metal particles. The sintered products of the ultra-fine metal particles on the insulating layer is removed (or patterned) by peeling off the protective film stuck to the insulating layer.

Abstract: A region is formed in a semiconductor substrate and extends beyond the substrate surface. First and second interconnects each having a predetermined thickness and a surface approximately parallel to the substrate surface are formed on the region. The first and second interconnects define a trench therebetween. A third interconnect is formed on the substrate. The thicknesses of the first and second interconnects are reduced a first amount to improve the aspect ratio of the trench, to improve the cross-sectional profile of the trench, or both. The thickness of the third strip is reduced a second amount. The second amount may be smaller than the first amount.

Abstract: There is provided a technique which prevents semiconductor devices under fabrication from being destroyed by pulse-like high potentials applied by plasma without adding any special fabrication step. A first line extending to a gate electrode of a thin film transistor is formed. A first insulation film is formed on the first line. A second line connected to a source region of the thin film transistor is formed on the insulation film. A second insulation film is formed on the second line. Then, a conductive pattern is formed on the second insulation film. A discharge pattern is formed the first and/or second line, and the first and/or second line is cut simultaneously with the formation of the conductive pattern.

Abstract: A resin composition comprising (a) an epoxy resin having a number average molecular weight of 1200 or less, (b) a carboxylic acid-containing acrylic or acrylonitrile-butadiene rubber, (c) a curing agent for the epoxy resin, and (d) a curing accelerator is easily chemically etched and suitable as an insulating adhesive for producing multilayer printed circuit boards.

Abstract: A method of forming an interconnect structure using a low dielectric constant material as an intralayer dielectric is described. In one embodiment, the present inventive method comprises the following steps. A conductive structure that is surrounded by a low dielectric constant material on its side surfaces is formed. A first inorganic insulator is formed over at least a portion of the low dielectric constant material. A second inorganic insulator is formed over the first inorganic insulator. A photoresist layer is deposited and then patterned to form an unlanded via in the second inorganic insulator. The second inorganic insulator and a portion of the first inorganic insulator are etched in order to form the unlanded via.

Abstract: A multilayered interconnection substrate prevents contact failure from occurring and a process for fabricating the same wherein a multilayered interconnection substrate comprises a first interconnection layer formed on a substrate, at least two layers of insulation films differing in composition from each other are formed on the first interconnection layer. The insulation layers have at least one contact hole formed in such a manner to expose the selected portion of the first interconnection layer. A resin wall buries stepped portions formed on an inter-peripheral portion of the contact hole and a second interconnection layer formed inside the contact hole along the resin wall which is electrically connected to the first interconnection layer exposed at the bottom portion of the contact hole.

Abstract: A plasma display panel is disclosed including: a transparent insulating substrate; a plurality of transparent electrodes in a strip arrangement with each electrode having a groove that runs along the median of its surface and has a predetermined width and depth at its center, and side walls on both sides of the groove, the side walls serving as barrier ribs; a fluorescent layer formed in each groove; and a plurality of electrodes in strip arrangement having a predetermined distance between one another and perpendicular to the transparent electrodes, the electrodes being supported by supporting means formed on a predetermined portion of barrier rib located on the edge portion of the substrate.

Abstract: A device includes a ceramic substrate. A ceramic via is defined within the ceramic substrate at an actual location which differs from a designed desired location for the ceramic via. A minimal capture pad electrically communicates the actual location with the designed desired location. The minimal capture pad contains a ceramic via contact portion, a thin film stud contact portion, and a connecting portion; and each of the three is configured to be as small as permitted to limit the capacitances produced by the capture pad.

Abstract: A method for forming a blind-via in a laminated substrate by laser drilling a blind-via from a top surface of the substrate toward a bottom surface of the substrate using a first laser and a first trepanning motion of a laser focal spot of the first laser. Then, the via is laser drilled from the top surface toward the bottom surface using a second laser and a second trepanning motion of a laser focal spot of the second laser.

Abstract: The specification describes techniques for applying under bump metallization (UBM) for solder bump interconnections on interconnection substrates. The UBM of the invention comprises a Cu, Cu/Cr, Cr multilayer structure. Problems in etching the Cu/Cr layer are overcome using a high pH etchant containing a copper complexing ingredient to prevent passivation of the copper constituent by the chromium etchant solution. With the availability of this etchant the UBM multilayer can be formed using subtractive techniques.

Abstract: The present invention discloses a noel method for anchoring a via/contact or the forming of a capacitor having increasing capacitance in a semiconductor device by utilizing alternating layers of BPTEOS oxide and TEOS oxide and a deep UV photoresist such that toroidal-shaped cavities can be formed at the interfaces between the BPTEOS oxide layers and the TEOS oxide layers during the formation of the via/contact opening or the capacitor opening by a plasma etching process. The number of cavities formed, i.e., the number of anchors formed on the via/contact or capacitor, can be suitably adjusted by the number of BPTEOS oxide layer deposited on the semiconductor structure. Each BPTEOS oxide layer produces two anchors on the via/contact or the capacitor. The deep UV photoresist layer should contain a photo-acid-generator such that hydrogen ions are emitted when the photoresist layer is subjected to UV radiation and heating which accelerates the hydrogen ion generation process.

Abstract: A method includes applying a first seed layer extending over a horizontal surface and via sidewalls of a dielectric material and exposed underlying contact metallization; removing at least some of the first seed layer from the contact metallization and the horizontal surface while leaving a sufficient amount of the first seed layer on the sidewalls as a catalyst for subsequent application of a third seed layer; sputtering a second seed layer over the contact metallization and the horizontal surface; using an electroless solution to react with the first seed layer and apply the third seed layer over the sidewalls; and electroplating an electroplated layer over the second and third seed layers.

Abstract: A process for forming a double-sided or multi-layered circuit structure entailing the use of a fill material that forms a conductive connection between the layers of the circuit structure and photodefinable resins that form permanent dielectric layers and plateable surfaces of the circuit structure. The method includes forming a through-hole in a substrate, and then filling the through-hole with the fill material containing a metal that is catalytic to electroless copper. The fill material forms an electrical connection having oppositely-disposed connection surfaces that are coextensive with opposite surfaces of the substrate. A first photodefinable dielectric layer is then formed on each surface of the substrate, including the connection surfaces, and openings are photoimaged and developed in the dielectric layers to expose a portion of each connection surface.

Abstract: A method for removing a resist layer, particularly in via holes, includes plasma to remove organic compounds, rinsing the device in deionized water, and sputtering with argon to remove inorganic compounds. The order of rinsing and sputtering can be reversed. These methods avoid the use of acids and industrial solvents.

Abstract: Processes for forming pedestal holes in a substrate assembly are described. In particular, processes using a high density plasma to etch doped or undoped silicon oxide are described. For example, a fluorocarbon chemistry is employed for selective deposition of a spacer layer to form a vertical to less than vertical spacer within a contact hole. The contact hole is extended using the spacer and a subsequent etch to complete formation of a via. Alternatively, both spacer deposition and contact hole formation may be achieved in a single etch step.

Abstract: A multilayer printed circuit board small in interlayer thickness, capable of fine wiring, minimized in IVH and BVH diameters, high in strength and also excellent in wire bonding workability can be produced by a process comprising the steps of coating a thermosetting resin varnish compounded with electrically insulating whiskers on a roughened side of a copper foil, semi-curing the resin by heating to form a thermosetting resin layer, integrally laminating it on an interlayer board in which plated through-holes and conductor circudits have been formed, and roughening the cured thermosetting resin layer on the via hole wall surfaces with a roughening agent.

Abstract: A constraint graph is generated by representing plural nets by using vertices and correlation in the horizontal and vertical directions among the nets by using edges. Then, clustering is conducted so that each of the vertices of the constraint graph is assigned to any one of plural layers in view of a channel height and so as to minimize the number of stacked vias. Next, routing topology is obtained on the basis of obtained clusters of the respective layers and the constraint graph, and routing patterns satisfying a design rule are obtained on the basis of the routing topology. In the clustering, the number of the stacked vias is minimized while retaining the minimum channel height in view of the final routing patterns. Accordingly, the routing patterns satisfying a desired design rule can realize a high density, resulting in a compact semiconductor integrated circuit.

Abstract: A flip chip is soldered to an array of flexible pillars of compliant dielectric material on a circuit board. Each pillar has an electrically conductive core electrically coupled to the circuit board. The pillars absorb movement due to differences in the coefficient of thermal expansion of the chip and board, and hence reduce the possibility of fatigue failure of the solder joint. The pillars are manufactured by forming a layer of compliant dielectric material on the circuit board, forming blind holes in the layer, filling the holes with electrically conductive material overlapping the edges of the holes, and then laser ablating to remove the compliant dielectric material except where protected by the electrically conductive material.

Abstract: A method of forming a via in a laminated substrate by placing a first mask between an output optics of a laser and an exposed surface of a laminated substrate. The first mask has a first aperture corresponding to a location of a via in the substrate. A second mask is placed between the first mask and the output optics of the laser. The second mask has a second aperture disposed within a main beam of a laser beam output from the laser and blocks side lobes of the laser beam from reaching the exposed surface of the substrate.

Abstract: A metalization structure having a first conductor layer on the surface of an underlying layer and, further, a second conductor layer connected conductively with the first conductor layer in which a polyimide insulative film of low thermal expansion coefficient is present between at least an end of a pattern of the second conductor layer and the first conductor layer, for stably obtaining a metalization structure of high reliability and free from the worry of peeling of the conductor portion from a substrate or occurrence of cracking to the underlying layer.

Abstract: An insulating resin composition for the build-up of multilayer circuits by the procedure of copper foil lamination and a method for the production of a multilayer printed circuit board by the use of the insulating resin composition are disclosed. The insulating resin composition comprises at least one species of epoxy resin having a softening point of not more than 110.degree. C., a monomer or an oligomer possessing an unsaturated double bond, an epoxy resin curing agent, and a photopolymerization initiator. The insulating resin composition is applied to a printed circuit board throughout the entire area thereof so as to cover conductor patterns formed thereon and then irradiated with UV light. Subsequently a copper foil is superposed on the applied layer of the insulating resin composition on the printed circuit board by means of a heated pressure roller to effect lamination thereof.

Abstract: A method of manufacturing a double-sided circuit tape carrier comprising an insulating film like a polyimide tape, circuit wiring patterns on both sides thereof, and via holes through which at least a part of the circuit wiring patterns on both sides are electrically connected with each other. A copper thin film is patterned by photoetching. Via holes are formed through the insulating film by irradiating a laser beam by using the patterned copper thin film as a mask. Then, a conductive layer of a graphite conductive thin film and a copper plating layer is formed. The copper thin film is patterned by photoetching forming a chip hole and an outer lead hole through the insulating film by irradiating a laser beam. Finally, one of the copper thin films is patterned by photoetching to form circuit wiring pattern.

Abstract: The present invention provides a method for forming a bonding pad having a low contact resistance. The method includes steps of: a) forming a bonding pad structure on a substrate having a metal layer by forming a passivation layer over said metal layer and etching the passivation layer with a fluorine-containing gas by which a fluorine-containing layer is formed on a surface of said bonding pad structure; and b) removing the fluorine-containing layer for reducing a contact resistance of said bonding pad structure.

Abstract: There is provided a technique which prevents semiconductor devices under fabrication from being destroyed by pulse-like high potentials applied by plasma without adding any special fabrication step. A first line extending to a gate electrode of a thin film transistor is formed. A first insulation film is formed on the first line. A second line connected to a source region of the thin film transistor is formed on the insulation film. A second insulation film is formed on the second line. Then, a conductive pattern is formed on the second insulation film. A discharge pattern is formed the first and/or second line, and the first and/or second line is cut simultaneously with the formation of the conductive pattern.

Abstract: A process for forming a semiconductor device (68) in which an insulating layer (52) is nitrided and then covered by a thin adhesion layer (58) before depositing a composite copper layer (62). This process does not require a separate diffusion barrier as a portion of the insulating layer (52) has been converted to form a diffusion barrier film (56). Additionally, the adhesion layer (58) is formed such that it can react with the interconnect material resulting in strong adhesion between the composite copper layer (62) and the diffusion barrier film (56) as well as allow a more continuous interconnect and via structure that is more resistant to electromigration.