Abstract: A method and system for deep trench silicon etch is presented. The method comprises introducing a reactive process gas and a Noble gas to a plasma processing system, wherein the reactive process gas comprises two or more of HBr, a fluorine-containing gas, and O2, and the Noble gas comprises at least one of He, Ne, Ar, Xe, Kr, and Rn. Additionally, radio frequency (RF) power is applied to the substrate holder, upon which the substrate rests, at two different frequencies. The first RF frequency is greater than 10 MHz, and the second frequency is less than 10 MHz.

Abstract: Each via hole of a printed wiring board is filled with a metal conductor. A distal end of each metal conductor is covered with a diffusing metal layer. The distal end of the metal conductor is pressed against a conductor circuit of another substrate, and the printed wiring boards are bonded together by thermocompression bonding. The metal of the distal end of each metal conductor is diffused into the metal of the conductor circuit so that an alloy layer is formed in an interface. As a result, reliability in the interlayer electrical connection can be improved.

Abstract: The present disclosure pertains to our discovery of a particularly efficient method for etching a multi-part cavity in a substrate. The method provides for first etching a shaped opening, depositing a protective layer over at least a portion of the inner surface of the shaped opening, and then etching a shaped cavity directly beneath and in continuous communication with the shaped opening. The protective layer protects the etch profile of the shaped opening during etching of the shaped cavity, so that the shaped opening and the shaped cavity can be etched to have different shapes, if desired. In particular embodiments of the method of the invention, lateral etch barrier layers and/or implanted etch stops are also used to direct the etching process. The method of the invention can be applied to any application where it is necessary or desirable to provide a shaped opening and an underlying shaped cavity having varying shapes.

Abstract: A method of wiring formation includes forming a feeder film partially on a substrate, forming on the substrate a plating base film via a physical film making method so that the plate base film partially overlaps the feeder film, forming a plated wiring on the plating base film using an electrolytic plating, and selectively removing at least an area of the feeder film which is exposed from the plated wiring, using a wet etching process.

Abstract: A method for removing voids in a ceramic substrate includes steps of preparing a ceramic substrate and defining holes of different dimensions in the ceramic substrate, sputtering a titanium/copper film onto opposite sides of the ceramic substrate, chemical copper plating, forming a dry film onto the ceramic substrate, forming an image, plating copper leads, plating nickel and gold, removing the dry film, and etching titanium/copper.

Abstract: A method and solution to activate and metallize the surface of a fluorocarbon material, suitable for circuit boards is disclosed. The surface of fluorocarbon materials is both hydrophobic and oleophobic, and highly inert and repellent to oils, dyes, adhesive and coatings. The method of the present invention makes such fluorocarbon materials wettable with metallizing solutions and chemicals, and also bondable with adhesives and coatings. The method comprises contacting said fluorocarbon surface with a mixture comprising a cyclic amide, a quaternary ammonium compound, a cationic or nonionic surfactant, a glycolether and an organic acid.

Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

Abstract: An aqueous solution containing sulfuric acid and hydrogen peroxide is used for a soft etchant in a soft etching step in a smear removing process performed prior to a catalyst applying process for chemical copper plating after formation of via holes through an insulating layer of a multi-layer substrate by irradiation of laser. The concentration of sulfuric acid is 2.4 times or less than the concentration of hydrogen peroxide. Preferably, the concentration of sulfuric acid is in a range of 9 to 90 g/l, and the concentration of sulfuric acid is lower than the concentration of hydrogen peroxide. More preferably, the concentration of sulfuric acid is in a range of 9 to 18 g/l, and the concentration of hydrogen peroxide is in a range of 33 to 38.5 g/l. As a result, smear can be certainly removed without excessively etching a conductive layer in the smear removing process.

Abstract: A process facilitates manufacturing a multiple layer wiring board having therein a thin-film capacitor The process includes: forming a metallic film layer having a barrier metal layer and a metal layer to be sequentially anode oxidized on an insulating layer first conductor pattern; covering a lower electrode forming region of the thin film capacitor in the first conductor pattern with a first resist film; etching to remove an uncovered portion of the metallic film layer; removing the first resist film and covering the first conductor pattern, except for part of the metallic film layer, with a second resist film; forming an anodic oxidation film on the exposed metallic film layer; removing the second resist film and attaching an adherence layer and a metal seed layer, sequentially, on the anodic oxidation film end on the first conductor pattern; and forming an upper electrode second conductor pattern on the anodic oxidation film.

Abstract: An inspection contact sheet for electronic device inspection comprises a three-layer base sheet formed by laminating protective films to both the surfaces of an insulating rubber layer, conductive rubber parts having rubber elasticity and penetrating the base sheet perpendicularly to the surfaces of the base sheet. One of the surfaces of the base sheet is provided with contact pads to be brought into contact with the terminals of the electronic device, and the other surface of the base sheet is provided with contact pads to be brought into direct contact with the terminals of an electronic circuit inspecting circuit member or wiring lines. The terminal pads or the wiring lines have an area greater than the sectional area of the conductive rubber parts.

Abstract: A method for making multi-layer electronic circuit boards 64 having “blind” type apertures 28, 30 which may be selectively and electrically grounded and further having selectively formed air bridges and/or crossover circuits 45, 46.

Abstract: A method of forming a conductive plug in a contact hole comprising: providing a wafer having a conductive layer comprising silicon adjacent a dielectric layer comprising silicon oxide, and a contact hole disposed in the dielectric layer, the contact hole having surfaces that include sidewalls formed in the dielectric layer and a bottom defined by the conductive layer, a contaminant material being disposed over at least a portion of the conductive layer defining the bottom of the contact hole, the dielectric layer having a surface in which the contact hole terminates in an opening opposing the bottom; depositing a layer of a barrier material on the work object, the layer having a substantially uniform thickness from the surface at the opening of the contact hole to the bottom of the contact hole; and depositing a layer of a protective material barrier around at least opening of the contact hole; etching the material at the bottom of the contact hole to expose the contaminant material while retaining protective

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: A method for planarizing a circuit board, has a step of fixing a circuit board having wiring layers on both sides to a board having a flat surface through an adhesive layer, wherein said circuit board is pressed from above by a flat member on fixing thereof.

Abstract: A method of making a thermally enhanced BGA substrate in which a metal (copper) core, has dielectric layers applied to each side thereof and conductive through-core build-up vias are provided. Rigidifying non-conductive dielectric sheets are laminated to the oppositely facing surfaces and then conductive layers are applied to at least one of the rigidifying non-conductive sheets and via connections are made through the dielectric layer(s) to the core conductive layer.

Abstract: A method and solution to activate and metallize the surface of a fluorocarbon material, suitable for circuit boards is disclosed. The surface of fluorocarbon materials is both hydrophobic and oleophobic, and highly inert and repellent to oils, dyes, adhesive and coatings. The method of the present invention makes such fluorocarbon materials wettable with metallizing solutions and chemicals, and also bondable with adhesives and coatings. The method comprises contacting said fluorocarbon surface with a mixture comprising a cyclic amide, a quaternary ammonium compound, a cationic or nonionic surfactant, a glycolether and an organic acid.

Abstract: A process for masking an electronic component substrate involving application of a temporary mask material to the substrate to form a removably adhered temporary mask over the surface. Exemplary mask materials include polymer films and aqueous hardenable liquid coatings. An electronic component substrate having a temporary mask for masking the substrate surface from interconnect fill material.

Abstract: An anisotropic conductive film 1 comprising an insulating film 2 and plural conductive paths (3, 4), wherein the plural conductive paths are insulated from each other and penetrate the insulating film 2 in the thickness direction of the film, with both ends of the paths being exposed on both surfaces of the insulating film, and wherein a conductive path 3 capable of contact with an electrode 12 of a semiconductor element 11 and a circuit 14 of a circuit board 13 has at least one end protruding more than an end on the same side of a conductive path incapable of contact with the electrode and the circuit. The ACF of the present invention can prevent a conductive path not involved in electrical connection from being in contact with a part other than an electrode of a semiconductor element and/or a part other than a circuit of a circuit board.

Abstract: A method is described for producing a conducting connection through insulating layers by way of a contact hole and conducting materials with which the contact hole is filled. The method permits the production of a contact hole resembling the shape of a wineglass, into which conducting filling material and barrier layers can be inserted without the known problems such as void formation, overetching trenches, and dielectric close-off. It is possible in this way, for example, to produce an electric connection between the diffusion zone of a selection transistor and the lower electrode of a storage capacitor of large-scale integrated DRAM and FeRAM components with the aid of only a few mask steps.

Abstract: A method of making a high-density copper-clad multi-layered printed wiring board having a reliable through hole including providing a stacked assembly including three copper foil layers and at least two resin layers; providing an auxiliary material on a top surface of the stacked assembly and providing a backup sheet on a bottom surface of the stacked assembly to form an assembly; subjecting the top surface of the assembly to pulsed oscillation from a carbon dioxide laser to form at least one through-hole to produce a pulsed assembly; reducing the thickness of the front and reverse copper foil layers and simultaneously with reducing, removing copper foil burrs, to produce a cleaned assembly; and plating the cleaned assembly with copper to produce the high-density copper-clad multi-layered printed wiring board.

Abstract: A method of fabricating a semiconductor package is disclosed in which a first Ni—Au plating is formed on a bonding pad for connection with a semiconductor chip, without a mechanical process or a masking operation. The method applies a copper plating on a through bore and the bonding pad, where the copper plated layer formed on the bonding pad is selectively removed, and then a second Ni—Au plating is formed on the bonding pad and a ball pad.

Abstract: A paste for filling a throughhole, comprises: an epoxy resin; a curing agent; and a metal filler, wherein the metal filler is a powder comprising a base metal, and the curing agent is an imidazole compound represented by the following formula (1): wherein R1 represents a hydrogen atom, an alkyl group having 1 to 10 carbon atoms, a hydroxyalkyl group having 1 to 10 carbon atoms or an alkyloxy group having 1 to 10 carbon atoms.

Abstract: In a method of manufacturing a multilayer circuit board, cable patterns in a plurality of cable layers can be precisely formed, and the cable layer are formed with higher density, with higher reliability. The multilayer circuit board comprises: a plurality of cable layers, each of which includes electric conductive sections; a plurality of first insulating layers, each of which encloses the electric conductive sections in each cable layer and fills spaces between the electric conductive sections; and post vias electrically connecting the electric conductive sections in one cable layer to those in another cable layer. Height of the electric conductive sections in each cable layer are equal to that of the first insulating layer enclosing those electric conductive sections.

Abstract: Process for the production of at least one solderable surface in selected solder regions and of at least one functional surface in function regions differing from the solder regions on circuit carriers provided as well as of corresponding circuit carriers.

Abstract: A method of manufacturing a microelectronics device is provided, wherein the microelectronics device is formed on a substrate having a frontside and a backside. The method comprises forming a circuit element on the frontside of the substrate from a plurality of layers deposited on the frontside of the substrate, wherein the plurality of layers includes an intermediate electrical contact layer, and forming an interconnect structure after forming the electrical contact layer. The interconnect structure includes a contact pad formed on the backside of the substrate, and a through-substrate interconnect in electrical communication with the contact pad, wherein the through-substrate interconnect extends from the backside of the substrate to the electrical contact layer.

Abstract: A semiconductor device includes a first metallization level, a first diffusion barrier layer, a first etch stop layer, a dielectric layer and an opening extending through the dielectric layer, the first etch stop layer, and the first diffusion barrier layer. The first diffusion barrier layer is disposed over the first metallization level. The first etch stop layer is disposed over the first diffusion barrier layer, and the dielectric layer is disposed over the first etch stop layer. The opening can also have rounded corners. A sidewall diffusion barrier layer can be disposed on sidewalls of the opening, and the sidewall diffusion barrier layer is formed from the same material as the first diffusion barrier layer. The first etch stop layer can be formed from a material different than the first barrier layer, and the material of the first barrier layer can be selected from the group consisting of tantalum, titanium, tantalum nitride, titanium nitride, and tungsten nitride.

Abstract: The present invention provides a process for forming a printed circuit film in a waterproof keyboard. A circuit layer and an insulation layer are provided. The circuit layer has a plurality of contacts and circuits electrically connected to the contacts. The contacts are located respectively corresponding to keys of a keyboard. The circuits are located respectively corresponding to the contacts. Then, the circuit layer is folded and then the insulation layer is interleaved between the folded circuit layer. Thereafter, the insulation layer is laminated with the circuit layer.

Abstract: The invention discloses a method of forming via-holes in multilayer circuit boards. The process includes forming covering substances in predetermined spots in a multilayer circuit board and thereafter applying an insulating layer upon the circuit board. The predetermined spots are then uncovered and the covering substances are removed to form via-holes.

Abstract: At least one layer of a dielectric material 3 is deposited on a copper track 1 covered with an encapsulation layer 2. A cavity 6 is etched in the layer of dielectric material at the location of the future vertical connection. At least one protective layer is deposited in said cavity to preclude diffusion of copper 7. The protective layer 7 at the bottom of the cavity 6 is subjected to an anisotropic etching treatment and also the encapsulation layer 2 is subjected to etching, whereafter the cavity is filled with copper. The copper particles pulverized during etching the encapsulation layer do not contaminate the dielectric material 3.

Abstract: Start with a semiconductor substrate with contacts exposed through an insulating layer. Form a base over the contacts, with the base composed of at least one metal layer. Then form a conductive metal layer over the base. Form a mask over the top surface of the conductive metal layer with C4 solder bump openings therethrough with the shape of C4 solder bump images down to the surface of the conductive metal layer above the contacts. Etch away the exposed portions of the conductive metal layer below the C4 solder bump openings to form through holes in the conductive metal layer exposing C4 solder bump plating sites on the top surface of the base below the C4 solder bump openings with the conductive metal layer remaining intact on the periphery of the through holes at the C4 solder bump plating sites. As an option, form a barrier layer over the plating sites next.

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26 which have improved solder-wetting characteristics by causing a first insulating layer to separate from a portion of a first conductive layer of the multi-layer electronic circuit board 10 which allows for communication by and between some or all of the various component containing surfaces, and portions of the formed multi-layer electrical circuit board 10, which selectively allows components contained within and/or upon these portions and surfaces to be interconnected.

Abstract: A method and structure for forming a sidewall image transfer conductor having a contact pad includes forming an insulator to include a recess, depositing a conductor around the insulator, and etching the conductor to form the sidewall image transfer conductor, wherein the conductor remains in the recess and forms the contact pad and the recess is perpendicular to the sidewall image transfer conductor.

Abstract: A process for fabricating coils using a Damascene process uses a curved substrate having a surface extending along and about an axis made of a first material. A groove is formed in the curved surface along and around said axis, and the groove is filled with a second material that is different from the first material to form a coil of second material in said first material. Excess second material is then removed from the surface of the first material, leaving the coil of second material in the groove.

Abstract: Thin films possessing low dielectric constants (e.g., dielectric constants below 3.0) are formed on integrated circuits or other substrates. Caged-siloxane precursors are linked in such a way as to form dielectric layers, which exhibit low dielectric constants by virtue of their silicon dioxide-like molecular structure and porous nature. Supercritical fluids may be used as the reaction medium and developer both to the dissolve and deliver the caged-siloxane precursors and to remove reagents and byproducts from the reaction chamber and resultant porous film created.

Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

Abstract: A method for the fabrication of electrical contacts using metal forming, masking, etching, and soldering techniques is presented. The method produces a plurality of specialized electrical contacts, capable of use in an interposer, or other device, including non-permanent or permanent electrical connections providing contact wipe, soft spring rates, durability, and significant amounts of travel.

Abstract: A method of making a multilayer substrate comprising: (a) providing an interlayer circuit board having conductor circuits thereon; (b) forming a dielectric layer on the interlayer circuit board; (c) mechanical drilling (or laser drilling) through the dielectric layer to the conductor circuits at predetermined positions thereof so as to form blind-vias; (d) electrolessly plating a conductive layer on the surface of the dielectric layer and the blind-vias; (e) forming an etch resist on the conductive layer, followed by formation of outer conductor circuits on the conductive layer by selectively etching; and (f) removing the etching resist. Since the blind-vias of the present invention are formed by drilling instead of photosensitive polymer technology, the processing steps are minimized thereby significantly improving the production efficiency. Furthermore, since the mechanical drilling (or laser drilling) has better accuracy, the blind-vias can be formed with better accuracy.

Abstract: A printed circuit board is produced by patterning a resist layer according to a circuit mask that defines desired circuit paths. The resist pattern layer is formed by removing the resist from the board in the desired circuit paths and a conductive material is plated onto the board in the resist voids defined by the circuit mask so that the height of the conductive material relative to the substrate equals or exceeds the height of the resist layer relative to the substrate. A low-reactive solution is applied over the conductive material and removes a surface portion of the conductive material. As the solution removes the conductive layer, it forms a film barrier and the solution composition changes, both of which substantially inhibits any further removal of the conductive material. Next, the film barrier is removed from the board allowing another film barrier to form stimulating the removal of further conductive material.

Abstract: The subject of the present invention is to keep the wiring resistance low and reduce the variation of the wiring resistance in one identical lot in semiconductor devices of a multi level interconnect structure in which at least the lower wiring layer is an aluminum wiring layer. Contact holes (31, 51) are formed in dielectric interlayers (3, 5) of upper and lower wiring layers (1, 2, 4) by dry etching. In the method of forming the contact holes of the invention, the dry etching was applied in two steps divisionally. The first step of etching is applied with supplying CF4, CHF3, Ar and N2 into an etching chamber. The second step of etching is conducted with supplying CF4, CHF3 and Ar into the etching gas chamber.

Abstract: A method for improving the electrical conductivity and appearance of copper films produced by reduction of copper ions using hypophosphite, comprising exposure of the as-deposited copper film to a solution of dimethylamino borane (DMAB) or equivalents thereof.

Abstract: A connection component is made by providing an assembly comprising a base layer of a dielectric material, a metal layer overlying the base layer, and a top layer of a plasma-etchable material overlying the metal layer; forming openings in the top layer to produce a top layer mask; and forming first conductive elements from the metal layer by removing metal from regions of the metal layer aligned with the openings in the top layer mask. This method may be used to form a connection component having vias or bond windows formed therein for connection with other elements of a microelectronic device and conductive elements may be formed on either or both sides of the base layer.

Abstract: A method for the fabrication of electrical contacts using metal forming, masking etching, and soldering techniques is presented. The method produces a plurality of specialized electrical contacts, capable of use in an interposer, or other device, including non-permanent or permanent electrical connections providing contact wipe, soft spring rates, durability, and significant amounts of travel.

Abstract: An electrical connecting member is provided with a holding member made of an electric insulating material and a plurality of conductive members held by the holding member in a state of being insulated with each other. One end of each of the conductive members is exposed on one surface of the holding member and the other end of each of the conductive members is exposed on the other surface of the holding member. The conductive members have portions exposed from the holding member, the length of which is longer than the thickness of the holding member. These exposed portions are easily deformed by the pressure force exerted at the time of connecting electric circuit components to reduce the coupling load even when there is irregularity in the heights thereof or unevenness in the junctions of the objects connection, hence enabling high density connections between the electric circuit components. The exposed portions can also be formed to have empty holes, i.e.

Abstract: A conductive structure in a silicon wafer for preventing plasma damage. The wafer includes a plurality of dies and a plurality of scribe lines between the dies. The semiconductor substrate of this wafer further includes a plurality of patterned conductive layers. The conductive structure comprises of a plurality of ground wires and a plurality of contacts. The ground wires are distributed inside the scribe lines and are positioned at least in the uppermost conductive layer. The contacts are used for connecting the ground wires and the semiconductor substrate electrically. When other conductive layers other than the uppermost conductive layer also contain ground wire connections, the ground wires in different conductive layers are electrically connected by plugs.

Abstract: A method for integrating a thin film resistor (60) into an interconnect process flow. Metal interconnect lines (40) are formed over a semiconductor body (10). An interlevel dielectric (50) is then formed over the metal interconnect lines (40). Conductively filled vias (62) are then formed through the interlevel dielectric (50) to the metal interconnect lines (40). A thin film resistor (60) is then formed connecting between at least two of the conductively filled vias (62) using a single mask step. Connection to the resistor (60) is from below using a via process sequence already required for connecting between interconnect layers (40, 64). Thus, only one additional mask step is required to incorporate the resistor (60).

Abstract: In a chip package, when a Ni/Au layer is formed by electroless plating, there is no problem with density increasing of interconnections and the like, since leads for plating and tie bars are not formed. However, the adhesive strength of solder balls to ball pads is low, so that the adhesion tends to be unstable. In the present invention, no leads for plating are formed, while the adhesive strength of solder balls to ball pads is improved by electroplating the ball pads with a Ni/Au layer. In addition, an increase in the density of interconnections and an improvement of the electrical properties is also obtained. The Ni/Au layer is formed by electroplating on the base metal layer surface which is not covered with a DFR (Dry Film Resist) by applying an electric current to the base metal layer.

Abstract: Substantially transparent electrodes are formed on a substrate by a process including forming on the substrate, in order, a bottom high index layer, a metallic conductive layer, and a top high index layer with a conductivity of at least about 400 &OHgr;/square; and chemically etching the bottom high index layer, the top high index layer and the conductive layer to form discrete electrodes in the metallic conductive layer.

Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.

Abstract: A process for producing a self-aligned contact comprises the steps of forming leads on a substrate, forming an etching stop layer on the leads by depositing, then forming a sacrificed oxide layer; after the structure of the leads is defined, a spacer is formed on both sides of the structure; a sacrificed oxide layer is formed, allowing the spacer to protrude in the form of horn. Next, a dielectric layer having a flat upper surface is deposited on the substrate and the structure of leads, a contact hole being formed between the leads so as to connect the substrate, a conductive material being filled in the contact hole to form a plug.

Abstract: In the method of fabricating an inductor, at least first and second conductive segments are formed in a semiconductor layer spaced apart in a first direction. A first dielectric layer is formed over a portion of the semiconductor layer along the first direction such that the first dielectric layer crosses the first and second conductive segments. A conductive core is formed on the first dielectric layer, and a second dielectric layer is formed over the semiconductor layer. First and second contact holes are formed in the second dielectric layer such that the first contact hole exposes a portion of the first conductive segment on a first side of the first dielectric layer and the second contact hole exposes a portion of the second conductive segment on a second side of the first dielectric layer.