Abstract: For a condensed matter system containing a guest interstitial species such as hydrogen or its isotopes dissolved in the condensed matter host lattice, the invention provides tuning of the molecular orbital degeneracy of the host lattice to enhance the anharmonicity of the dissolved guest sublattice to achieve a large anharmonic displacement amplitude and a correspondingly small distance of closest approach of the guest nuclei. The tuned electron molecular orbital topology of the host lattice creates an energy state giving rise to degenerate sublattice orbitals related to the second nearest neighbors of the guest bonding orbitals. Thus, it is the nuclei of the guest sublattice that are set in anharmonic motion as a result of the orbital topology. This promotion of second nearest neighbor bonding between sublattice nuclei leads to enhanced interaction between nuclei of the sublattice.

Abstract: A method for electrically interconnecting a first electrical conductor to a second electrical conductor through a via formed in an insulating layer disposed between the conductors. A refractory metal layer is formed over: an upper surface of the insulating layer; sidewalls of the insulating layer formed by the via; and, portions of the first electrical conductor exposed by the via. Gold is deposited on a portion of the refractory metal layer formed on the exposed portion of the first electrical conductor. The deposited gold has a planar surface and is preferably spaced from portions of the conductive layer disposed on the sidewalls of the insulating layer to provide an plating site. Additional gold is electroplated onto the electroplating site to fill the via to a level co-planar with the upper level of the insulating layer. A photoresist layer is formed over the co-planar surfaces of the insulating layer and the filled via.

Abstract: A desired circuit wiring pattern is formed by forming by plating means a conductive layer having excellent resistance at least to an etching solution on a metal layer which is removed in the post-process by etching means using a resist layer. A surface protective layer having a hole for exposing part of the circuit wiring pattern is formed on both sides of the circuit wiring pattern at a predetermined position as an external connection terminal portion. The circuit wiring pattern can be formed in multiple layers by coating the conductive layer with a circuit wiring layer of another conductive material and a bump is formed to fill the hole as required.

Abstract: A method of manufacturing a multiple layer circuit board with stacked vias of fine dimension and pitch. A base laminate with conductive pattern is coated with a dielectric which is photolithographically processed to create holes exposing selected regions of the underlying conductive pattern. The holes through the dielectric are plated to form via connections between the surface and the conductive pattern on the base laminate. The recess created by the via is filled with a conductive and plateable polymer which upon curing forms a conductive plug. A second dielectric layer is deposited on the board structure and in succession photolithographically processed to expose the underlying plated via and plug. The hole in the second dielectric is plated and filled with conductive polymer so as to create a second via vertically aligned with and electrically connected to the underlying first via.

Abstract: Detector of the filament type for determining a static or dynamic characteristic of an ambient medium, constituted by a resistive component intended to be heated by the Joule effect in the medium, and an interface process region suitable for reacting with the medium by a physico-chemical with an effect, depending on the characteristic to be determined, on the electrical characteristic of the interface region, in which there is a supporting member through which there is at least one aperture and at least one filament including the resistive component, composed of one or more thin films and a central portion located in the aperture and end portions via which the central portion is connected to the supporting member.

Abstract: An electrical connecting device including a first circuit board providing thereon with input/output terminals, each of the terminals having a tip surface coated with gallium and a second circuit board providing thereon with contact terminals, each of the terminals having a tip surface coated with indium or tin. A low-melting point alloy layer is formed by a mutual action between gallium and indium or tin, when the input/output terminals of the first circuit board are in contact with the respective terminals of the second circuit board and the terminals are electrically connected to each other. The second metal layer includes a plurality of wire-like metal supports extending substantially perpendicular to the surface of the terminal and a low-melting point metal retained by the wire-like metal supports.

Abstract: The present invention provides an anti-reflective Ta.sub.3 N.sub.5 coating which can be used in a dual damascene structure and for I line or G line lithographies. In addition, the Ta.sub.3 N.sub.5 coating may also be used as an etch stop and a barrier layer. A dual damascene structure is formed by depositing a first dielectric layer (16). A dielectric tantalum nitride layer (18) is deposited on top of the first dielectric layer. A second dielectric layer (20) is deposited on the tantalum nitride layer. A dual damascene opening (34) is etched into the dielectric layers by patterning a first opening portion (26) and a second opening portion (32) using photolithography operations. Dielectric tantalum nitride layer (18) serves as an ARC layer during these operations to reduce the amount of reflectance from conductive region (14) to reduce distortion of the photoresist pattern. The use of a dielectric tantalum nitride layer as an ARC is particularly suitable for I line and G line lithography.

Abstract: A method of manufacturing a magnetic head junction board wherein a laminated plate having a springy metal layer and a conductive layer is prepared. A circuit wiring pattern is formed on the conductive layer by photoetching and the springy metal layer is formed into a predetermined shape by etching. The circuit wiring pattern is provided with a surface protecting layer which leaves holes exposed at the ends of the circuit wiring pattern. Then, the holes are filled with conductive metal to form bump-shaped terminals such that the ends on one side jut out of the surface protecting layer. Lastly, the springy metal layer is bent into a predetermined shape so that the bump-shaped terminals face against each other. Alternative process are also disclosed.

Abstract: Electrodepositing a metallurgy such as gold on to printed circuit board features. The methods include electrolessly depositing a copper layer over the surface of the printed circuit board. This is followed by applying a layer of photoresist atop the electroless copper, and exposing and developing the photoresist to uncover areas to be etched, leaving behind the specific features to be plated. By this expedient the remaining copper forms a commoning layer. The remaining photoresist is stripped to uncover the copper commoning layer, and a second layer of photoresist is applied atop the partially etched copper layer. This layer of photoresist is exposed and developed to uncover the features to be plated. These features are then plated with the metallurgy of choice. The photoresist is then stripped off and the electroless copper layer can remain if needed for further processing or be microetched off without harming copper traces that may exist below the electroless copper layer.

Abstract: A conductive paste compound for via hole filling includes a conductive filler at 80 to 92 weight percent with an average particle size of from 0.5 to 20 .mu.m and specific surface of from 0.1 to 1.5 m.sup.2 / g, a liquid epoxy resin at 4.5 to 20 weight percent containing 2 or more epoxy groups with room temperature viscosity of 15 Pa.sec or less, and a hardener at 0.5 to 5 weight percent, wherein the viscosity is 2,000 Pa.sec or less and the volatile amount is 2.0 weight percent or less. A filling paste and a printed circuit board with use thereof are provided which can conduct an inner-via-hole connection between electrode layers without using a through-hole plating technique. The conductive paste comprises a metallic particle such as copper, an epoxy resin, a hardener, and if necessary, a dispersant. The paste having low viscosity and low volatility under high shear is used to fill holes disposed in a laminated substrate.

Abstract: A halogenated polymeric material is exposed to a reducing agent and/or an electrolyte and applied voltage to render exposed portions capable of being metallized and of being etched. The exposed portions can also be doped to thereby induce electrical conductivity therein. Also, new structures containing a free standing halogenated polymeric-containing layer and electrical conductive pattern thereon are provided.

Abstract: Multilayer printed circuit boards, foil printed circuit boards and metal-clad laminates for foil circuit boards and a process for the manufacture thereof, with interfacial connections structured in insulator layers, with resist openings of surface structured in resist coatings, with current paths structured in conductor layers and with contact points and in which for reducing the number of photochemical structurings or patternings required the interfacial connections and resist openings are mechanically structured, in that interfacial connection openings preworked in insulator layers are etched according to interfacial connection structures of mask foils, that in the interfacial connection openings are deposited electrically conductive deposition substances for the formation of contact layers in said openings.

Abstract: A self contained unit for forming Cu metallurgy interconnection structures on SC substrates. The unit has an enclosed chamber with a plurality of apparatus for performing wet processes, including electroless metal plating and planarization. The unit provides a way of reducing the number of times the wafer is transferred between the wet process steps that require less environmental cleanliness and dry very clean processes steps.

Abstract: An interconnecting post for mounting a microelectronic device such as an integral circuit chip is fabricated with generally uniform cross-section, by forming a first layer of positive photoresist on a substrate, soft-baking that first layer and exposing it for a short time with a wide-apertured mask or simply a UV blank flood exposure. Without developing the first layer, a second layer of positive resist is then applied over the first layer, soft-baked, and then exposed with a narrow-apertured mask. During the soft-baking of the second layer, some of its activator in the photoresist compound diffuses into the exposed portion of the first layer and modifies its solubility in such a way that, when the layers are subsequently developed, the developer partially undercuts the unexposed portion of the first layer to form in the photoresist an opening of generally uniform cross-section. This opening can then be filled by plating to produce a strong, integral interconnect post.

Abstract: A method for producing a panel of a multi-layer electronic circuit package and resulting article of manufacture is provided comprising the steps of coating a circuitized core material that has been cut into panels with a dielectric material and copper cover sheets; forming circuits from the cover sheets by etching; applying an adhesive polymer across the dielectric material covering the entire area of the panel; applying a cover sheet; drilling the panel to form through-holes and vias; seeding and plating the through-holes and vias with joining metal; applying photo-resist to the panels exposed with an image of the area of the panel to be joined and developed; and etching the cover sheet and the photo-resist away in the area of the panel to be joined to expose the adhesive polymer.

Abstract: A multilayer laminated body has a determinate system of hollow passages and is formed by an assembly of flat layers of polymeric materials having major dimensions in orthogonal X and Y directions and a thickness dimension in a Z direction perpendicular to the X and Y directions. Selected ones of the layers have openings extending through in the Z direction, and other layers have canals formed in an X-Y plane. The openings and canals form parts of hollow passages so that assembly of multiple layers joins openings and canals forms complete and continuous passages through the assembled layers. Layers joined in pre-laminate assemblies are assembled together in precise relative positions for desired alignment of the canals and openings. The passages can be filled with optically conductive material or electrically conductive material and electrodes can be appropriately positioned for acting on fluids passing through the body.

Abstract: A method of applying a conductive carbon coating to a non-conductive layer, conductive carbon compositions, and a printed wiring board having through holes or other surfaces treated with such carbon compositions are disclosed. A board or other substrate including at least first and second electrically conductive metal layers separated by a non-conductive layer is provided. The board has a recess extending through at least one of the metal layers into the non-conductive layer. The recess has a non-conductive surface which is desired to be made electrically conductive. The carbon in the dispersion has a mean particle size no greater than about 50 microns. The method is carried out by applying the carbon dispersion to a non-conductive surface of the recess to form a substantially continuous, electrically conductive carbon coating. Optionally, the coating is then fixed, leaving the carbon deposit as a substantially continuous, electrically conductive layer. Chemical and physical fixing steps are disclosed.

Abstract: A process for forming a multilayer printed wiring board comprising integrally laminating a plurality of insulating circuit boards having circuits formed on insulating substrates and interlaminar insulating layers sandwiched between adjacent insulating circuit boards, and forming via holes for making electrical connection between two or more layers of circuits. Where the difference between the glass transition point of an interlaminar insulating layer and that of the adjoining insulating substrate is not greater than 60.degree. C., proof against exfoliation due to heat history of the board and high reliability of insulation and through-hole connection is achieved. The interlaminar insulating layers desirably are B-staged and have a B-stage resin flow of less than 1%.

Abstract: An inventive method for manufacturing an array of thin film actuated mirrors for use in an optical projection system includes the steps of: (1) providing an active matrix; (2) depositing a thin film sacrificial layer; (3) ion-implanting the thin film sacrificial layer; (4) creating an array of empty cavities; (5) depositing an elastic layer; (6) forming an array of conduits; (7) depositing a second thin film, a thin film electrodisplacive and a first thin film layers, successively, thereby forming a multiple layered structure; (8) patterning the multiple layered structure into an array of semifinished actuated mirrors; (9) forming a thin film protection layer covering each of the semifinished actuated mirrors; (10) removing the thin film sacrificial layer by using an etchant; (11) rinsing away the etchant by using a rinse; (12) removing the rinse; and (13) removing the thin film protection layer, thereby forming the array of thin film actuated mirrors.

Abstract: A process for fabricating thin multi-layer circuit boards which allow the electrical conduction of remodeling pads to be easily cut do not use etching for gold, avoid the lift-off method for forming a thin chromium film on the wiring pattern layer, allow a defective wiring pattern layer to be removed, and which uses uniform heating of the substrate, from the back side thereof, at the time of pre-baking. A barrier metal (60) is excluded from a portion where the electrical conduction of a remodeling pad (62b) is to be cut (FIGS. 1 to 16). Alternatively, gold-plating resist is formed in order to avoid the etching for gold (FIGS. 17 to 19). Alternatively, a thin chromium film is formed in advance by etching on the wiring pattern layer (FIGS. 27 to 33). Alternatively, a metallic barrier film (122) is formed on each of the wiring pattern layers so that the wiring pattern layer can be removed without affecting other wiring pattern layers (FIGS. 36 to 42).

Abstract: A multi-degree-of-freedom manipulator includes a flexible tube having a plurality of flex portions provided therealong, a plurality of actuators made of shape memory alloy and respectively provided near the flex portions to correspond to the flex portions, for flexing the flex portions, two common energy transmission paths, extending along the flexible tube, for transmitting an energy to the actuators, and selective energy supply members, provided between the common energy transmission paths and the actuators in series, for controlling the energy supplied from the common energy transmission path to the actuators, thereby respectively independently driving the actuators to bend the flexible tube.

Abstract: This invention provides a method of cleaning integrated circuit wafers which effectively removes precipitates formed as a result of the tungsten etchback process. When tungsten is used to fill via holes in an inter-metal dielectric layer an adhesion layer of titanium nitride, TiN, is required to provide good adhesion. As a result of the tungsten etchback, wherein fluorine based etchants are used, precipitates of TiF.sub.3 can form which are extremely difficult to remove. Methods, such as in-situ bake after the tungsten etchback, are used to prevent the formation of the precipitates but do not remove them after they are formed. This invention teaches a method using a strong oxidizing agent, such as H.sub.2 O.sub.2, to cause an oxidation-reduction reaction which converts the precipitates to a water soluble form. The water soluble form of the precipitates are then removed using a water rinse and spin dry process.

Abstract: A microwave arrangement, such as a splitter and combiner, is formed by sandwiching a conductive ground plane between two dielectric microstrip boards whose outer faces carry RF traces and extending the ground plane with a conductive plurality of distributed via holes that contact the ground plane and pass through the boards to their outer faces. Connections are made between the traces on the surfaces with additional conductive via holes that pass through the ground plane where the ground plane forms openings for passage of the via holes.

Abstract: Through-holes are formed in a printed circuit board substrate by chemical etching a metal foil clad circuit board having open positions in the metal foil where a hole is to be formed using N-methyl-2-pyrrolidone, a mixture of methylene chloride and HF, or a mixture of methylene chloride, HF and xylene.

Abstract: In the method according to the invention for the production of multilayer foil printed circuit board from preliminary products (A), with current paths (B) structured in electrical conductive layers (1,3) and with electrically conductive metal platings (C,D) from conductive layer (1) to conductive layer (3) through an insulating layer (2), or for producing semifinished products for such foil circuit boards, in first method steps a structuring means (7,7',13) is applied in controlled, local manner to the preliminary product (A) and resist layers (8,9) are coated with the preliminary product (A), the structuring means (7,7',13) being applied either to the resist layers (8,9) and the resist layer (8,9) is locally removed, or the resist layers (8,9) are applied to the structuring means (7,7',13) and in a further method step the applied structuring means (7,7',13) are removed, so that openings (10,10') are formed in the resist layers (8,9) and extend down to the insulating layer (2) and in a further method step thr

Abstract: A multilayered electronic component created by a wet process, wherein a ceramic base is imprinted with an electrode and an interlayer via is formed on top of it by introducing a via pattern printed in ink that is incompatible with a layer of wet ceramic slurry coating placed on top of the electrode and the via pattern. The incompatibility leads to a physical-chemical reaction that removes ceramic material away from the top of the via pattern by diffusing ceramic materials contained in a colloidal suspension forming a via-through hole. After the wet ceramic slurry is dried, it surrounds the via-through hole and the imprinted via pattern. Then a new electrode layer is imprinted on top of the dried ceramic coating. The new electrode layer completes an electrically conductive path formed from the bottom-most electrode layer, to the via pattern, and then terminating at the new electrode layer on top.

Abstract: A process for the production of printed circuit boards and film circuit boards includes providing a starting product with a layer of insulating material between layers of metal. Openings are formed at desired locations through the metal and, at selected ones of those openings, openings are formed through the insulating material by plasma etching or chemical etching. The result of this is back-etching leaving projecting webs of metal extending partly across the openings. The projecting edges are removed by subjecting all of the metal surfaces to etching or electrodeplating which also thins the metal layers. The resulting structure is then plated, adding reinforcing thickness to the thinned metal layers and coating the openings through the insulating material with metal, providing interracial connections between the metal layers. The resulting intermediate can then be formed into a circuit board by forming circuit patterns in the metal layers.

Abstract: A structure of openings is produced in two or more layers of silylated, polyimide photoresist. Openings in subsequent layers, which overlap previous openings, are of larger size. Then the structure is transferred to an organic substrate using oxygen plasma etching with up to 3% CF.sub.4. The smallest opening transferred to the substrate extends through the substrate.

Abstract: The present invention relates to the preparation of a multichip module comprising one or more thin film probes. The thin film probes are useful in in situ probe testing of IC chips. An assembly comprising the multichip module and a circuit board having IC chips in a number corresponding to the number of thin film probes is also claimed.

Abstract: A chip carrier according to the present invention includes: a carrier body including an upper face, a lower face, and an internal conductor; and a plurality of terminal electrodes formed on the upper face of the carrier body, the plurality of terminal electrodes electrically connecting an LSI chip to the internal conductor. A plurality of concave portions for electrically connecting a plurality of electrodes on a circuit substrate to the internal conductor are provided on the lower face of the carrier body, the concave portions being electrically connected to the internal conductor.

Abstract: A multi-layer electronic circuit package including at least one electrically conductive plane, a first organic polymeric dielectric material having a first optical absorbency to an ablating wavelength of laser light, and a second organic polymeric dielectric material having a second optical absorbency to the ablating wavelength of laser light. The first and second optical absorbencies being different from each other. A first layer of one of the organic polymeric materials overlays at least one surface of the at least one electrically conductive plane and a second layer of a different organic polymeric material with a different optical absorbency to the material in the first layer overlays the first layer.

Abstract: A permanent solder mask is applied to the surface of a printed circuit board using a copper foil carrier. The solder mask preferably is one or two layers of a thermosetting resin e.g. epoxy resin. Selected circuit features are exposed by etching away portions of the copper foil and removing the underlying thermosetting resin. Then, the remaining copper foil is removed, leaving the solder mask on the surface of the printed circuit board.

Abstract: Multilayer circuit devices include a plurality of metallized patterns thereon, said patterns being separated by a polymeric dielectric film. The various metallized patterns are interconnected by means of microvias through the polymeric film or films. Each of the metallizations is a composite including in succession from the substrate or from the polymeric film, a layer of titanium (Ti), a layer of titanium and palladium alloy (Ti/Pd), a layer of copper (Cu), and a layer of titanium and palladium alloy (Ti/Pd). The Ti-Ti/Pd-Cu-Ti/Pd composite is hereinafter referred to as TCT. The adhesion between the polymeric film and the top Ti/Pd layer is better than that between the polymer and gold (Au) and comparable to that between the polymer and an adhesion promoted Au layer. Use of the TCT metallization also results in additional cost reduction due to the elimination of Ni and Au layers on top of the Cu layer.

Abstract: The present invention relates to a process for the manufacture of printed circuit boards. The method contemplates a novel processing sequence for this manufacturing process which method is particularly versatile in reducing the number of steps and variety of chemicals currently necessary to produce the circuit boards.

Abstract: Disclosed is a printed wiring board 1 with a through hole 5 in which a hollow portion 7 wider than both an upper opening 5A and a lower opening 5A is formed, and a solder resist film 9 is formed at the hollow portion 7 so as to firmly adhere to an inner wall of the through hole 5. Thereby, it can prevent the solder resist film 9 from being dropped out from the through hole 5 and electrical check of circuit patterns on the printed wiring board 1 can be efficiently conducted while directly setting a checker pin 13 of a checker into the through hole 5.

Abstract: In a multilayer wiring board comprising a substrate on which two or more layers of wiring or insulation film are formed of different materials, for example, the wiring layer is processed so that the processed side faces of the board contour a stepped shape in the cross-sectional view of the board, whereby coverage of a film formed thereon can be improved. Specifically, first, insulation film 2 is formed on a substrate 1 and then, resistor film 3 and resistor electrode film 4 are continuously formed thereon to form a film of multiple structure. Mask 9 is formed thereon. Then, the layers is etched successively in the order of from the top layer and thereafter only the resistor electrode film 4 is further etched with an etching solution which selectively etches only the resistor electrode film 4 to form a stepwise patterned side face. Finally, the mask is removed and wiring electrode film 5 is formed.

Abstract: A circuit component assembly and a method for forming the assembly as an annular body in a laminate, preferably between a trough-hole or via and a surrounding conductive layer in a PCB are disclosed, the circuit component assembly including one or more resistors/conductors, inductors and dielectrics/capacitors or combinations thereof, outer and inner peripheries of the circuit component preferably having substantially constant radii permitting simple determination of operative electrical characteristics for the circuit component from (a) the inner and outer radii, (b) an effective thickness for the circuit component and (c) its electrical characteristics determined by the material formed in the annular recess, the circuit component body preferably being formed from a liquid precursor forming conductive interconnections for the circuit component assembly at its outer and inner perimeters.

Abstract: A photosensitive insulation bonding layer is formed on a conducting layer. The photosensitive insulation bonding layer is subjected to exposure treatment to produce an exposed area and an unexposed area. Another conducting layer is formed on the outer surface of the photosensitive insulation bonding layer which has undergone the exposure treatment, then both conducting layers are photoetched to produce desired wiring patterns. In the next step, the unexposed area is removed from the photosensitive insulation bonding layer by development so as to form an access opening for connecting a circuit component to the wiring patterns. Then, the exposed area of the photosensitive insulation bonding layer is turned into an insulating layer by curing.

Abstract: A method of fabricating a printed wiring board (1) and a printed wiring board module (17) by providing a first board (1) having a pair of major opposing surfaces, a via (3) having walls extending between the surfaces and a layer of copper (5) disposed on at least one surface and extending along the walls of the via. The copper disposed in the via is protected against a subsequent etching of the copper on the surface by filling the remaining portion of the via with an epoxy (7) and then reducing the thickness of the layer of copper on the surface. The layer of copper and the epoxy are then planarized. A core layer and a second board are then provided and the first and second boards are secured to opposing sides of the core layer. A second via having walls and extending through the first and second boards and the core layer is then formed and a layer of copper is disposed on the walls of the second via and the surface.

Abstract: A process for producing front and rear contacts on a solar cell provides for producing a channel structure on the passivation layer of a silicon wafer, producing a rear contact by printing and firing a silver paste that has an aluminum dopant, treating the wafer with a palladium solution containing fluoride to produce a nucleation layer on the surface of the channel structure, and reinforcing the nucleation layer by depositing a further metal.

Abstract: A printed circuit board and a method for making same is disclosed whereby a very high wiring density is provided in those regions of the printed circuit board in which external components (e.g., semiconductor chips) are to be attached directly. An automated registration routine permits very precise registration and positioning in said regions.

Abstract: A head for an ink jet recording apparatus including: an electro-thermal transducer for generating thermal energy for use to discharge ink; and a circuit portion electrically connected to the electro-thermal transducer, wherein the circuit portion has a first conductive layer, an insulating layer disposed on the first conductive layer, and a second conductive layer disposed on the insulating layer, and an opening portion of the insulating layer is filled with a conductor formed by a selective deposition method so that the first conductive layer and the second conductive layer are connected to each other.

Abstract: The present invention provides a process for producing a high-density printed wiring board with plated throughholes, at high productivity and reliability by a direct drawing method.

Abstract: In a method of fabricating a multilayer laminate for a printed wiring board, a plurality of blind via sites are etched from a first side of a first sheet, the first sheet including a flexible dielectric material, the flexible material being clad on the first and a second side with first and second layers of conductive material, respectively, through the first conductive material and the flexible material to the second conductive material. Conductive material posts are electroplated in the blind via sites, using the second layer of conductive material as an electrode. A system for fabricating a multilayer laminate for a printed wiring board and a multilayer laminate for a printed wiring board formed thereby is also disclosed.

Abstract: Electrical interconnect structures comprised of high temperature superconducting signal layers on a substrate bonded to one another or optionally to a base substructure containing power and ground planes and processes for their preparation are disclosed.

Abstract: The multi-chip module comprises a co-fired substrate, and, on at least ont face of the substrate, a set of superimposed ceramic insulating layers, fired at a temperature substantially smaller than the firing temperature of the substrate. Conducting interconnection lines are formed in thick layers deposited between said ceramic insulating layers. Electronic components are mounted at the surface of the set of ceramic layers.

Abstract: Methods of constructing a wire interconnect structure on a substrate are described. The methods broadly comprise the steps of depositing a spacer layer on a surface of the substrate, depositing a mask layer on the spacer layer, and removing a first portion of the mask layer overlying a desired area on the substrate surface to expose the spacer layer underlying the first portion of the mask layer. The methods further comprise the step of etching the structure such that a first portion of the spacer layer overlaying the desired area is removed and such that a portion of the desired area is exposed, and the step of depositing a first conductive material on the exposed portion of the desired area such that a conductive post is formed on the substrate surface and mounted to the desired area. Some of the disclosed methods comprise additional steps for forming an interconnect structure on the opposite surface of the substrate and providing an electrical interconnect means between the two interconnect structures.

Abstract: Disclosed is a process for plasma etching a mask patterned dielectric film to form vias on a semiconductor wafer, so that the resulting etched structure is devoid of residues on the walls of the structure. A via is an opening through a dielectric material through which a point of contact of underlying metal with a metal film deposited over the dielectric is made. The underlying metal, when exposed to plasma, has a tendency to sputter onto the vertical wall portions of the contact via structures. The metal-containing sputtered material forms a residue that essentially cannot be removed in the subsequent photoresist stripping process typically used in semiconductor manufacturing. The plasma etch process in accordance with the invention enables removal of the sputtered metal by utilizing with the basic dielectric etch gases a gas that reacts with the metal to form volatile compounds which are readily evacuable.

Abstract: An electronic part is produced by forming two metallic wiring films of different materials on a main substrate, where a first metallic wiring film is formed on the main substrate, a protective film is formed in desired regions on the main substrate and the first metallic wiring film, and a second metallic wiring film is formed on the first metallic wiring film. The thus produced electronic part has an insulating protective film between the first and second metallic wiring films. By the presence of the protective film the surface of the first metallic wiring film is protected from etching, corrosion or deterioration by an agent for patterning the second metallic wiring film.

Abstract: A process for an improved solder terminal is disclosed. The improved solder terminal is made of a bottom metallic adhesion layer, a CrCu intermediate layer on top of the adhesion layer, a solder bonding layer above the CrCu layer and a solder top layer. The adhesion layer is either TiW or TiN. A process for fabricating an improved terminal metal consists of depositing an adhesive metallic layer, a layer of CrCu over the adhesive layer and a layer of solder bonding material, over which a solder layer is formed in selective regions and the underlying layers are etched using solder regions as a mask.