Abstract: A structure and method for creating a contact between a conductive layer and a pad for dissipating electrostatic charges comprising the steps of, forming a pad and a composite insulating layer between and over conductive plates on a substrate, wherein the insulating layer isolates and protects the conductive plates and pad from damage, the insulating layer comprising a dielectric region underlying a conductive layer. A passivation layer is formed over at least a portion of the conductive layer and a photoresist is patterned over at least a portion of the passivation. An opening is etched through the passivation and the insulating layers, wherein the photoresist and the conductive layer serve as masks. Finally, a conductive material is deposited in the opening to form an electrical contact between the pad and the conductive layer.

Abstract: A method of forming minimally spaced MRAM structures is disclosed. A photolithography technique is employed to define masking patterns, on the sidewalls of which spacers are subsequently formed to reduce the distance between any of the two adjacent masking patterns. A filler material is next used to fill in the space around the masking patterns and to form filler plugs. The masking patterns and the spacers are removed using the filler plugs as a hard mask. Digit and word lines of MRAM structures are subsequently formed.

Abstract: A method for fabricating a flexible printed circuit board with access on both sides includes the steps of applying a metallic conductor track sheet to a base sheet and patterning the metallic conductor track sheet in order to produce conductor tracks. A conductor track covering with first contact-making cutouts is applied over the conductor tracks. Second contact-making cutouts are produced in the base sheet material by locally removing the base sheet through the use of laser irradiation. As an alternative, the first contact-making cutouts as well as the second contact-making cutouts can be produced by removing material with a laser.

Abstract: A laser direct write method creates true three dimensional structures within photocerams using an focused pulsed ultraviolet laser with a wavelength in a weakly absorbing region of the photoceram material. A critical dose of focused laser UV light selectively exposes embedded volumes of the material for subsequent selective etching. The photoceram material exposure is nonlinear with the laser fluence and the critical dose depends on the square of the per shot fluence and the number of pulses. The laser light is focused to a focal depth for selective volumetric exposure of the material within a focal volume within the remaining collateral volumes that is critically dosed for selecting etching and batch fabrication of highly defined embedded structures.

Abstract: One or more through holes are formed by a process in a printed circuit board substrate formed of a resinous dielectric sheet and a conductive layer covering one surface of the dielectric sheet. The process involves the forming by laser one or more cavities on other surface of the dielectric sheet such that the cavities penetrate only the dielectric sheet, without penetrating the conductive layer. Both surfaces of the dielectric sheet are coated with a liquid photoresist layer such that the cavities are filled with the photoresist. A plurality of small areas are formed by photolithography on the surface which is covered with the conductive layer. The small areas are corresponding in location and shape to the cavities which may be of any shape. The small areas are stripped of the conductive, layer by etching before the cavities are stripped of the photoresist. The through holes are thus formed in the small areas defined by the cavities.

Abstract: A multilayer wiring board assembly, a multilayer wiring board assembly component and a method of manufacture thereof are described in which it is possible to easily laminate together flexible FPCs having highly packing densities by via-on-via and chip-on-via. The multilayer wiring board assembly is laminated by laminating together a plurality of multilayer wiring board assembly components, each of which is made by preparing a copper plated resin film 10 made of a flexible resin film 1 which is provided with a copper foil 2 bonded to one surface thereof and an adhesive layer 3 bonded to the other surface, opening a through hole 7 in the copper plated resin film 10 through the resin film 1 and the adhesive layer 3, filling the through hole by screen printing from the copper foil 2 with a conductive paste to form a conductive paste filler 8 having a projection 8b as projected from the adhesive layer 3.

Abstract: A method of making upper conductive lines in dual damascene process having lower copper conductive lines is disclosed. The processes begin from a substrate having lower copper conductive lines and a via formed in the nitride layer. An oxide layer as IMD is then formed on the nitride layer. Next, the oxide layer is patterned to form trenches. Thereafter, a barrier layer is deposited on the resulting exposed surface. An anisotropic etching process is then carried out to form barrier spacers on the sidewall of the trenches. Subsequently, an inert gas bombardment is done to remove a copper oxide layer so as to clean a surface of the via. Next, a conductive layer refilled in the trenches followed by a CMP process are successively performed to form a plurality of upper conductive lines.

Abstract: Fabrication of improved low-k dielectric structures is disclosed. Low-k dielectric structures are fabricated while overcoming the otherwise existing problems associated with the use of low-k dielectric materials. In one embodiment, the physical properties of a low-k dielectric material is modified by exposing the low-k dielectric material to electron beams. The exposed portion of the low-k dielectric material becomes easier to etch and clean and exhibits greater mechanical strength and a reduction in absorption of moisture. In another embodiment, a number of incremental exposure and etch steps are performed to fabricate a desired structure. In yet another embodiment, the steps of exposure of a low-k dielectric material are combined with the etch steps. The exposure and the etching of the low-k dielectric material are performed concurrently in the same system. In still another embodiment, a single exposure and a single etch step are utilized to fabricate a desired structure.

Abstract: A method for forming a recognition mark on the back surface of a substrate for a KGD that can be easily produced while manufacturing cost is low and permits repeated use of a substrate is provided. In the method, wiring patterns are formed on a surface of one side of an insulating substrate. The method includes step of forming a conductive pattern as a recognition mark on one surface where the wiring patterns are formed, and step of forming a through hole from a surface where the wiring pattern is not formed toward the conductive pattern. In the substrate, bumps connected with the KGD are formed on the surface on which the wiring patterns are not formed. Also, the conductive pattern may have a shape as the recognition mark or the through hole may have the shape as the recognition mark.

Abstract: A method of manufacturing a semiconductor device, which comprises the steps of providing a substrate having a groove on the surface thereof, forming a burying film on the substrate to thereby fill the groove with the burying film, performing a first polishing step to polish the burying film by means of a CMP method, the polishing being suspended before the substrate is exposed, and performing a second polishing step to polish the burying film by means of a CMP method until part of the burying film which is disposed outside the groove is removed. The time to finish polishing of the second polishing step is determined based on a film thickness of the burying film which is left remained after finishing the first polishing step. The first polishing step may be performed under a condition which differs from that of the second polishing step.

Abstract: A thin film circuit substrate is manufactured by forming a lower thin film electrode on a substrate, forming an organic insulating film with via holes on the lower thin film electrode, and irradiating the substrate with an inert gas ion to remove an oxidized surface film on the lower thin film electrode, and to generate functional groups, such that a modified surface layer with a surface modification coefficient of about 0.1 to about 0.5 is formed on the surface of the organic insulating film, and such that the oxidized surface film on the lower thin film electrode is removed at the same time. Accordingly, a thin film circuit substrate having excellent adhesion strength between the organic insulating film and the upper thin film electrode as well as excellent reliability of electroconductivity between the upper and the lower thin film electrodes is efficiently manufactured.

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Abstract: A method of making a multilayer substrate comprising: (a) providing an interlayer circuit board having conductor circuits thereon; (b) forming a dielectric layer on the interlayer circuit board; (c) mechanical drilling (or laser drilling) through the dielectric layer to the conductor circuits at predetermined positions thereof so as to form blind-vias; (d) electrolessly plating a conductive layer on the surface of the dielectric layer and the blind-vias; (e) forming an etch resist on the conductive layer, followed by formation of outer conductor circuits on the conductive layer by selectively etching; and (f) removing the etching resist. Since the blind-vias of the present invention are formed by drilling instead of photosensitive polymer technology, the processing steps are minimized thereby significantly improving the production efficiency. Furthermore, since the mechanical drilling (or laser drilling) has better accuracy, the blind-vias can be formed with better accuracy.

Abstract: In a microfluidic system using electrokinetic forces, the present invention uses electrical current or electrical parameters, other than voltage, to control the movement of fluids through the channels of the system. Time-multiplexed power supplies also provide further control over fluid movement by varying the voltage on an electrode connected to a fluid reservoir of the microfluidic system, by varying the duty cycle during which the voltage is applied to the electrode, or by a combination of both. A time-multiplexed power supply can also be connected to more than one electrode for a savings in cost.

Abstract: Disclosed is a manufacturable silicon-based modular integrated circuit structure having performance characteristics comparable to high frequency GaAs-based integrated circuit structures, comprising materials and made in process steps which are compatible with existing low cost silicon-based integrated circuit processing.

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Abstract: The present invention relates to flow field plates and the manufacture thereof, for use in fuel cells. The method of manufacture comprises particulate etching of a plate material using a particulate etchant (eg. sand blasting), a particulate etchant accelerator and a particulate etchant-resistant patterned mask, such that a fluid flow pattern determined by the pattern design on said mask is formed on the plate material.

Abstract: A printed circuit board includes a rectangular, insulating substrate and a conductive land formed on the substrate. The land is arranged near a selected one of the longitudinal edges of the substrate. An L-shaped terminal is mounted on the substrate, so that its longer horizontal portion overlaps the land, while its shorter bent portion is engaged with a positioning groove formed in the selected longitudinal edge of the substrate. The land is caused to protrude from the overlapping horizontal portion of the terminal toward the opposite longitudinal edge of the substrate.

Abstract: It is an object of a method of manufacturing a thin-film magnetic head of the invention to improve the insulating property between an electrode connected to a magnetoresistive element and a shield layer without increasing the thickness of an insulating layer between the magnetoresistive element and the shield layer. In the method, a pair of conductive layers to be the electrode (lead) connected to the MR element are formed on an insulating layer. Magnetic layers are formed to surround the conductive layers while an insulating film is placed between the magnetic layers and the conductive layers. Next, an insulating layer of alumina, for example, is formed over the entire surfaces of the magnetic layers. This insulating layer is polished to the surfaces of the conductive layers and flattened.

Abstract: A multilayer printed circuit board and a corresponding fabrication method are disclosed, which circuit board achieves a relatively high degree of wiring density and a relatively high degree of wiring design freedom. These advantages are obtained in the inventive printed circuit board by electrically connecting power conductors or ground conductors using through holes. On the other hand, signal conductors in any two adjacent signal wiring layers are electrically connected using via holes extending only through an intervening electrically insulating layer. Preferably, the electrically insulating layer is a layer of photosensitive resin and the via holes are formed using conventional photolithographic techniques.

Abstract: A microelectromechanical (MEMS) apparatus has a base and a flap with a portion coupled to the base may be fabricated by an inventive process. The process generally involves etching one or more trenches in a backside of a base, e.g., by anisotropic etch. The trench may be etched such that an orientation of a sidewall is defined by a crystal orientation of the base material. A layer of insulating material is formed on one or more sidewalls of one or more of the trenches. A conductive layer is formed on the layer of insulating material on one or more sidewalls of one or more of the trenches. The conductive layer may completely fill up the trench between the insulating materials on the sidewalls to provide the isolated electrode. Base material is removed from a portion of the base bordered by the one or more trenches to form a cavity in the base. The trench etch may stop on an etch-stop layer so that the cavity does not form all the way through the base.

Abstract: A method for forming a multi-level metal interconnection, comprising the step of forming a first metal interconnection over an underlying layer; forming an insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole to contact with the first metal interconnection; etching the insulating layer by a portion of the selected thickness; forming a pair of metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through one of the metal spacers.

Abstract: In the method for manufacturing a semiconductor device according to the present invention, after forming a BPSG film 110 on a silicon substrate 100, a preparatory hole 120 that reaches a specific depth and has a larger diameter than a contact hole 118 is formed at a position where the contact hole 118 (see FIG. 4) is to be formed at the BPSG film 110. Thus, polysilicon side walls 114 (see FIG. 4) formed at side portions of a polysilicon film 112 (see FIG. 4) are also formed at the side walls of the preparatory hole 120. As a result, the contact hole 118 (see FIG. 4) free of shape defects can be formed by using an etching mask 116 (see FIG. 4) constituted of the polysilicon film 112 and the polysilicon side walls 114. This structure prevents defects related to the shape of the hole and reduces electrical defects such as shorting.

Abstract: A method of forming a circuit includes forming a metallic circuit pattern on a base substrate. The circuit pattern has traces which are connected together by temporary bussing. A resist pattern for defining at least one terminal pad is formed over the circuit pattern. A layer of metal is formed on at least one area of the circuit pattern exposed by the resist pattern to a thickness suitable for serving as the at least one terminal pad for the circuit. A portion of the base substrate at the location of the temporary bussing is removed thereby causing the removal of the temporary bussing.

Abstract: A method for forming a top interconnection level and bonding pads for an integrated circuit chip is described. The interconnection level is formed by a damascene type process. Bonding pads are placed above the plane of the wiring channels of the interconnection level. This eliminates the problem of dishing of the relatively large bonding pads which occurs, during chemical mechanical polishing, when the bonding pads are on the same level as the interconnection metallurgy. The interconnection wiring includes a smaller pad base segment upon which the larger bonding pad is then formed. The bonding pad base segments are small enough that dishing during CMP is not a problem. Placing the bonding pads on pad bases provides for a more robust pad. The top level and bonding pad fabrication procedures are applicable with various conductive materials including aluminum, tungsten, and copper.

Abstract: A method and apparatus are disclosed for electrically monitoring processing variations of a material deposited using a collimated process. In one embodiment, the method and apparatus are directed to monitoring variations in step coverage of a conductive material deposited using a collimated sputtering process. A substrate having a plurality of trenches is used to mimic features desired to be monitored, such as contact holes. The resistance of metal deposited into the trenches is monitored to determine the effectiveness of the collimated sputtering process.

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions with desirable processing and dimensional characteristics. The invention is particularly useful for producing integral capacitors, with the desired processing and dimensional characteristics achieved with the invention yielding predictable electrical characteristics for the capacitors. The method generally entails providing a substrate with a first conductive layer, forming a dielectric layer on the first conductive layer, and then forming a second conductive layer on the dielectric layer. A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed.

Abstract: A process for fabricating an accelerometer, which includes providing a substrate with a layer of electrically conductive material on the substrate, micromachining the substrate to form a central electrical heater, a pair of temperature sensitive elements, and a cavity beneath the heater and the temperature sensing elements. Each temperature sensing element is spaced apart from said heater a distance in the range of 75 to 400 microns. The temperature sensing elements are located on opposite sides of the heater, thereby forming an accelerometer.

Abstract: A method of depositing and etching dielectric layers having low dielectric constants and etch rates that vary by at least 3:1 for formation of horizontal interconnects. The amount of carbon or hydrogen in the dielectric layer is varied by changes in deposition conditions to provide low k dielectric layers that can replace etch stop layers or conventional dielectric layers in damascene applications. A dual damascene structure having two or more dielectric layers with dielectric constants lower than about 4 can be deposited in a single reactor and then etched to form vertical and horizontal interconnects by varying the concentration of a carbon:oxygen gas such as carbon monoxide. The etch gases for forming vertical interconnects preferably comprises CO and a fluorocarbon, and CO is preferably excluded from etch gases for forming horizontal interconnects.

Abstract: A method 10 for making a multi-layer electronic circuit board 98 having at least one electrically conductive protuberance 15 which forms a “via” and which traverses through the various layers of the electric circuit board 98, and further having at least one interconnection portion 102 which supports a wide variety of components and interconnection assemblies.

Abstract: A printed wiring board manufacturing method is provided which is so consitituted that when a carbon dioxide leaser is used to form holes such as via holes in a copper clad laminate, copper foils and resin layers may be processed at the same time, without having to perform an etching treatment on the cooper foil. Namely, a carbon dioxide laser is used to form recess portions such as via holes in a copper clad laminate, followed by plating to form interlayer electrical connections, forming etching resist layers, and exposing and developing the etching resist layers, thereby effecting a circuit etching treatment. In particular, the copper clad laminate is a laminate formed by using waved copper foils to form external copper foils.

Abstract: A method for making a capacitor of a semiconductor memory device capable of providing increased capacitance without degraded resolution, as well as without the removal of any interlayer insulation layers upon formation of a lower electrode for the capacitor, wherein after formation of an access transistor on a semiconductor substrate, a first interlayer insulation layer for planarization of a surface of the semiconductor substrate and a second interlayer insulation layer for formation of the capacitor lower electrode are formed. After formation of an opening for exposing a part of an impurity diffusion region of the access transistor by etching a part of the first and second interlayer insulating layers, a spacer is formed within the opening. Further, after deposition of a conductive layer for the capacitor lower electrode onto a surface of the substrate, a planarization process is carried out until a part of the upper surface of the spacer is exposed.

Abstract: An electronic element is mounted on a resin wiring substrate and a cover member is bonded to the wiring substrate so as to cover the electronic element and constitute an encapsulation region. The encapsulation region houses the electronic element and has a cavity inside. A side electrode is formed of an electronically conductive through groove provided in a cover-member-bonding surface on the wiring substrate. A plating layer inside the electrically conductive through groove includes at least two metal layers including an Au plating layer and a Cu plating layer. The plating layer has conductors connected to circumferential peripheries of the electrically conductive through groove on upper and lower surfaces of the wiring substrate. Only the Cu plating layer is formed on the conductor on the upper surface of the wiring substrate to improve the reliability of bonding.

Abstract: Disclosed are a printed wiring board having micro-via holes highly reliable for conduction and a method of making the micro-via hole by providing a coating or sheet of an organic substance containing 3 to 97% by volume of at least one selected from a metal compound powder, a carbon powder or a metal powder having a melting point of at least 900° C.

Abstract: A method for fabricating stacked vias for microelectronic components. The method has a first step of providing a first patterned interconnect layer on a substrate. A first insulating layer is then applied on the first interconnect layer. A first via is formed in the first insulating layer and is in contact with the first interconnect layer. A second patterned interconnect layer is applied on the first insulating layer, leaving free a region around the first via. A second insulating layer is then deposited on the second interconnect layer and on the region left free around the first via. A second via is formed in the second insulating layer in such a way that it meets the first via directly.

Abstract: A multilayer rigid flex printed circuit board wherein the board laminate comprises a basestock composite containing a flexible core, formed by laminating a first conductive layer to a flexible insulator layer, a second insulator layer affixed to the basestock, said second insulator layer having a cutout region proximate to the flexible core of the basestock composite to expose a portion of said first conducting layer on said flexible core, a second conductive layer attached to said second insulator layer said second conductive layer having a cutout region proximate to the flexible core of the basestock composite, and a photo-imageable soldermask applied to the exposed portion said first conducting layer, and to the second conductive layer, wherein said photoimageable soldermask allows for photo definition of openings on the conductive layers to which it is applied.

Abstract: The present invention is for a method wherein a printed circuit board can be fabricated in an electroless process with a minimum number of manufacturing steps using mild etchant conditions on an intermediary seed layer to produce low-defect, fine conductive line printed circuit boards.

Abstract: An integrated in situ oxide etch process particularly useful for a counterbore dual-damascene structure over copper having in one inter-layer dielectric level a lower nitride stop layer, a lower oxide dielectric, a lower nitride stop layer, an upper oxide dielectric layer, and an anti-reflective coating (ARC). The process is divided into a counterbore etch and a trench etch with photolithography for each, and each step is preferably performed in a high-density plasma reactor having an inductively coupled plasma source primarily generating the plasma and a capacitively coupled pedestal supporting the wafer and producing the bias power. The counterbore etch preferably includes at least four substeps of opening the ARC, etching through the upper oxide and nitride layers, selectively etching the lower oxide layer but stopping on the lower nitride layer, and a post-etch treatment for removing residue.

Abstract: A multilayer circuit board having strengthened air bridge crossover structures, and additive and subtractive methods for producing the same, wherein the circuit includes specially designed metallic fortifying layers to mechanically and/or electrically fortify the circuit. A preferred embodiment includes air bridge structures having generally T-shaped cross-sections, which provide strengthened, mechanically robust air bridges which are especially resistant to damage from flexure and displacement due to physical impact, bending, thermal excursions, and the like.

Abstract: A method of polishing selected ceramics and metals is provided wherein the selected ceramic or metal material is rubbed against a solid surface in the presence of a nonabrasive liquid medium which only attacks the selected ceramic or metal material under friction. Examples of materials for the tribochemical polishing process includes ceramics such as silicon, silicon nitride, silicon carbide, silicon oxide, titanium carbide and aluminum nitride and metals such as tungsten. Both ceramic and metal surfaces can be polished, as in a damascene structure of an integrated circuit.

Abstract: A method for forming copper interconnects, without inducing copper diffusion, by eliminating the copper chemical-mechanical polishing process. A semiconductor structure is provided having a first metal layer thereover. A first inter-metal dielectric layer is formed over the first metal layer and planarized. A first resist layer is formed over the first inter-metal dielectric layer, and the first resist layer and the first inter-metal dielectric layer are patterned to form via openings with the first metal layer forming the bottoms of the via openings. A barrier/seed layer, comprising a barrier layer and an overlying seed layer, is formed on the sidewalls and bottoms of the via openings. A self-align layer, composed of a high-resistivity, inorganic material, is formed over the barrier/seed layer. The self-align layer is patterned to reform the via openings and to form trench openings, exposing the barrier/seed layer on the bottoms and sidewalls of the via openings and on the bottoms of the trench openings.

Abstract: The invention relates to subtractive and additive processes for creating a circuitized cavity in a printed circuit board. Additionally, the invention includes a circuitized cavity and a printed circuit board with a circuitized cavity. The circuitized cavity provides for a variety of advantages over wire bonds.

Abstract: A method of forming an internal channel within an article, such as a cooling channel in an air-cooled blade, vane, shroud, combustor or duct of a gas turbine engine. The method generally entails forming a substrate to have a groove recessed in its surface. A solid member is then placed in the groove, with the solid member being sized and configured to only partially fill the groove so that a void remains in the groove. The void is then filled with a particulate material so that the groove is completely filled. A layer is then deposited on the surface of the substrate and over the solid member and the particulate material in the groove, after which at least the solid member is removed from the groove to form the channel in the substrate beneath the layer.

Abstract: A method of creating a multilayer ceramic component of the present invention is used to spontaneously create vias between adjacent conductor layers in a multilayer inductive component. After a first conductive layer is printed, a via dot is printed on the first conductive layer. Next, a controlled thickness of ceramic slurry is cast over the previous ceramic layer, first conductive pattern, and the via dot. The physical/chemical forces between the via dot and the ceramic slurry expel the slurry in the proximity of the top surface of the via dot. When the ceramic slurry dries, the ceramic cast leaves vias filled with conductors from the preprinted via dots. This process is repeated until a desired number of conductive layers are formed.

Abstract: A process is provided for removing etch residues from one or more openings formed in one or more layers of a low dielectric constant insulation material over a copper metal interconnect layer of an integrated circuit structure which includes cleaning exposed portions of the surface of the copper interconnect layer at the bottom of the one or more openings, the process comprising providing an anisotropic hydrogen plasma to cause a chemical reaction between ions in the plasma and the etch residues in the bottom of the one or more opening, including copper oxide on the exposed copper surface, to thereby clean the exposed portions of the copper surface, and to remove the etch residues without sputtering the copper at the bottom of the opening.

Abstract: A silicon article including a silicon base and columns extending from the silicon base. The columns define a gap between the columns which is devoid of material so that the article can act as a filter or heat sink. Also disclosed is a method of making the silicon article.

Abstract: An information handling system is provided which comprises: a metal enclosure; at least one circuit assembly positioned within said metal enclosure, said circuit assembly including a circuitized substrate having at least one dielectric interior layer including a first surface and at least one hole therein; means for providing electrical power to said circuitized substrate within said metal enclosure; a filler material, wherein said filler material substantially fills said at least one hole within said at least one dielectric interior layer; a first wiring layer positioned on said first surface of said at least one dielectric interior layer, wherein said first wiring layer substantially covers said at least one hole having said filler material therein, said first wiring layer assisting in retaining said filler material within said at least one hole in said at least one dielectric interior layer; a first dielectric photoresist layer positioned on said first wiring layer and on said first surface of said at lea

Abstract: A process for making a printed circuit board is provided. The process employs a noble metal as an etch mask for subtractive circuitization and as a seed layer for secondary finishing. In a preferred embodiment of the invention, a dielectric is covered by a conductive layer of metal such as copper, a patterned photoresist is applied, additional copper is deposited on areas not covered by the photoresist, and a palladium etch mask/seed layer is deposited on the copper. The palladium layer remains sufficiently active for deposition of nickel or gold on the circuitry for purposes such as wire bonding.

Abstract: A method of fabricating an organic EL display panel accomplishes pixelation without using a shadow mask, and without exposing active EL elements to solvents from photoresist, or developing and stripping solutions. A first electrode layer and an insulating layer are formed on a transparent substrate. Portions of the insulating layer are removed at predetermined regions using at least one laser beam. An organic function layer and a second electrode layer are then formed on the predetermined regions. The first electrode layer, the organic layer and the second electrode layer form a sub-pixel. Additional sub-pixels are formed using the same method.

Abstract: The present invention relates to new methods for manufacturing electronic packaging devices, particularly printed circuit boards. Methods of the invention include use of reduced pH sweller and etch treatments that can produce printed circuit boards and other devices that are substantially more robust and reliable than produced by prior methods.