Etching Of Semiconductor Material To Produce An Article Having A Nonelectrical Function Patents (Class 216/2)
  • Patent number: 7182875
    Abstract: Microstructures and methods of fabricating microstructures are disclosed. One exemplary microstructure, among others, includes a substrate, an overcoat layer disposed upon the substrate, an air-region within at least a portion of the overcoat layer, and a framing material layer engaging at least a portion of the air-region on the inside of the framing material layer and engaging the overcoat layer on the outside of the framing material layer.
    Type: Grant
    Filed: October 28, 2003
    Date of Patent: February 27, 2007
    Assignee: Georgia Tech Research Corporation
    Inventors: Paul Jayachandran Joseph, Paul A. Kohl, Sue Ann Bidstrup Allen
  • Patent number: 7182876
    Abstract: In the present invention, disclosed are a cantilever microstructure and a fabrication thereof comprising a base plate; a cantilever beam extended from one surface of the base plate to outside so that a part thereof can be suspended, and formed of a silicon nitride material, and a probing tip formed at a front end of one surface of the cantilever beam, whereby the thickness of the cantilever beam becomes uniform and the mechanical and electrical characteristic thereof are improved.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: February 27, 2007
    Assignee: LG Electronics Inc.
    Inventor: Hyo-Jin Nam
  • Patent number: 7179674
    Abstract: An acceleration sensor includes a semiconductor substrate, a first layer formed on the substrate, a first aperture within the first layer, and a beam coupled at a first end to the substrate and suspended above the first layer for a portion of the length thereof. The beam includes a first boss coupled to a lower surface thereof and suspended within the first aperture, and a second boss coupled to an upper surface of the second end of the beam. A second layer is positioned on the first layer over the beam and includes a second aperture within which the second boss is suspended by the beam. Contact surfaces are positioned within the apertures such that acceleration of the substrate exceeding a selected threshold in either direction along a selected axis will cause the beam to flex counter to the direction of acceleration and make contact through one of the bosses with one of the contact surfaces.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: February 20, 2007
    Assignee: STMicroelectronics, Inc.
    Inventor: Joseph Colby McAlexander, III
  • Patent number: 7179392
    Abstract: A process for manufacturing a resonator including the steps of: forming on an insulating substrate a first portion of a conductive material and a second portion of another material on the first portion; forming an insulating layer having its upper surface flush with the upper part of the second portion; forming by a succession of depositions and etchings a beam of a conductive material above the second portion, the beam ends being on the insulating layer on either side of the second portion, the upper surface of the second portion being exposed on either side of the beam, a third portion of a piezoelectric material on the beam and a fourth portion of a conductive material on the third portion above the beam portion located above the second portion; and removing the second portion.
    Type: Grant
    Filed: March 5, 2004
    Date of Patent: February 20, 2007
    Assignees: STMicroelectronics S.A., Commissariat a l'Energie Atomique
    Inventors: Philippe Robert, Grégory Caruyer, Pascal Ancey, Guillaume Bouche
  • Patent number: 7175772
    Abstract: An actuator assembly and method for making and using an actuator assembly. In one embodiment, the assembly includes an actuator body having an actuator channel with a first region and a second region. An actuator is disposed in the actuator channel and is movable when in a flowable state between a first position and a second position. A heater is positioned proximate to the actuator channel to heat the actuator from a solid state to a flowable state. A source of gas or other propellant is positioned proximate to the actuator channel to drive the actuator from the first position to the second position. The actuator has a higher surface tension when engaged with the second region of the channel than when engaged with the first region. Accordingly, the actuator can halt upon reaching the second region of the channel due to the increased surface tension between the actuator and the second region of the channel.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: February 13, 2007
    Assignee: Micron Technology, Inc.
    Inventor: Jerome M. Eldridge
  • Patent number: 7175776
    Abstract: A method of fabricating a micro-electromechanical device includes the step of forming electrical connections to drive circuitry on a wafer substrate. A first sacrificial structure is formed on the wafer substrate. The first sacrificial structure corresponds at least to a mechanical arm to be formed on the sacrificial structure, spaced from the wafer substrate. At least the mechanical arm is formed on the sacrificial structure. A second sacrificial structure is formed on the wafer substrate such that the second sacrificial structure corresponds at least to a heater element to be connected to the electrical connections, isolated from and overlying the mechanical arm. The heater element is formed on the second sacrificial structure.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: February 13, 2007
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7172707
    Abstract: Methods are disclosed for fabricating spring structures that minimize helical twisting by reducing or eliminating stress anisotropy in the thin films from which the springs are formed through manipulation of the fabrication process parameters and/or spring material compositions. In one embodiment, isotropic internal stress is achieved by manipulating the fabrication parameters (i.e., temperature, pressure, and electrical bias) during spring material film formation to generate the tensile or compressive stress at the saturation point of the spring material. Methods are also disclosed for tuning the saturation point through the use of high temperature or the incorporation of softening metals. In other embodiments, isotropic internal stress is generated through randomized deposition (e.g., pressure homogenization) or directed deposition techniques (e.g., biased sputtering, pulse sputtering, or long throw sputtering). Cluster tools are used to separate the deposition of release and spring materials.
    Type: Grant
    Filed: January 5, 2005
    Date of Patent: February 6, 2007
    Assignee: Xerox Corporation
    Inventors: David K. Fork, Scott Solberg, Karl A. Littau
  • Patent number: 7160475
    Abstract: The present disclosure relates to a method for generating a three-dimensional microstructure in an object. In one embodiment, a method for fabricating a microscopic three-dimensional structure is provided. A work piece is provided that includes a target area at which the three-dimensional structure is to be fabricated. The target area has a plurality of virtual dwell points. A shaped beam is provided to project onto the work piece. The intersection of the shaped beam with the work piece defines a beam incidence region that has a desired shape. The beam incidence region is sufficiently large to encompass multiple ones of the virtual dwell points. The shaped beam is moved across the work piece such that different ones of the virtual dwell points come into it and leave it as the beam moves across the work piece thereby providing different doses to different ones of the virtual dwell points as the different dwell points remain in the beam incidence region for different lengths of time during the beam scan.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: January 9, 2007
    Assignee: FEI Company
    Inventor: Lawrence Scipioni
  • Patent number: 7160476
    Abstract: The electronic device (100) comprises an electrical element (30), for instance a MEMS capacitor or a BAW filter in a cavity (37) that is protected from the environment by a cover (38). The cover (38) is a patterned layer which is mechanically embedded in isolating material (7) present beside the cavity (37) and may further include contact pads (41). The device (100) may be suitably manufactured from an accurately folded foil including a patterned layer and a sacrifice layer. After applying the foil to the cavity (37) the isolating material (7) is provided and the sacrifice layer is removed. The patterned layer, or part thereof, stays behind and forms the cover (38).
    Type: Grant
    Filed: April 10, 2003
    Date of Patent: January 9, 2007
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Johannus Wilhelmus Weekamp
  • Patent number: 7160478
    Abstract: A method for producing an electronic component is provided. The method includes providing at least one die on a wafer, the at least one die having at least one sensor-technologically active and/or emitting device on at least a first side; producing at least one patterned support having at least one structure which is functional for the at least one sensor-technologically active and/or emitting device; joining the wafer with the at least one patterned support so that the first side faces the at least one patterned support; and separating the at least one die from the wafer.
    Type: Grant
    Filed: August 26, 2002
    Date of Patent: January 9, 2007
    Assignee: Schott AG
    Inventors: Jürgen Leib, Florian Bieck
  • Patent number: 7153440
    Abstract: A microelectromechanical structure is formed by depositing sacrificial and structural material over a substrate to form a structural layer on a component electrically attached with the substrate. The galvanic potential of the structural layer is greater than the galvanic potential of the component. At least a portion of the structural material is covered with a protective material that has a galvanic potential less than or equal to the galvanic potential of the component. The sacrificial material is removed with a release solution. At least one of the protective material and release solution is surfactanated, the surfactant functionalizing a surface of the component.
    Type: Grant
    Filed: September 12, 2002
    Date of Patent: December 26, 2006
    Assignee: PTS Corporation
    Inventors: Bevan Staple, Jillian Buriak
  • Patent number: 7153442
    Abstract: A method of manufacturing an ink jet print head is provided. The method forms, on a silicon monocrystailine substrate, a first etching pattern for forming pressure generating chambers and a second etching pattern located opposite to the first etching pattern with respect to ink supply ports. The second etching pattern is narrower than the first etching pattern and is located within opposite lines defining the first etching pattern. The method also anisotropically etches the silicon monocrystailline from the surface thereof, on which the first and second etching patterns are formed, to the other surface thereof and anisotropically etches areas of the silicon monocrystalline substrate. Also, each of the areas is located between the first and second etching patterns, to a depth suitable for the ink supply ports.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: December 26, 2006
    Assignee: Seiko Epson Corporation
    Inventors: Yutaka Furuhata, Yoshinao Miyata
  • Patent number: 7135120
    Abstract: The UV, deep UV and/or far UV (ultraviolet) filter transmission spectrum of an MPSi spectral filter is optimized by introducing at least one layer of substantially transparent dielectric material on the pore walls. Such a layer will modify strongly the spectral dependences of the leaky waveguide loss coefficients through constructive and/or destructive interference of the leaky waveguide mode inside the layer. Increased blocking of unwanted wavelengths is obtained by applying a metal layer to one or both of the principal surfaces of the filter normal to the pore directions. The resulting filters are stable, do not degrade over time and exposure to UV irradiation, and offer superior transmittance for use as bandpass filters. Such filters are useful for a wide variety of applications including but not limited to spectroscopy and biomedical analysis systems.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: November 14, 2006
    Assignee: Lake Shore Cryotronics, Inc.
    Inventors: Vladimir Kochergin, Philip Swinehart
  • Patent number: 7132056
    Abstract: A method of fabricating a fluid ejection device includes the step of forming a plurality of micro-electromechanical fluid ejection devices on a substrate that incorporates drive circuitry such that each device includes a micro-electromechanical actuator that is in electrical contact with the drive circuitry and a fluid ejection member that is positioned on the actuator. A plurality of nozzle chamber walls are formed on the substrate to define nozzle chambers such that each fluid ejection member is operatively positioned with respect to a respective nozzle chamber to eject fluid from the nozzle chamber on receipt of an electrical signal from the drive circuitry by the micro-electromechanical actuator to displace the fluid ejection member. A layer of sacrificial material is deposited on the substrate to cover the nozzle chamber walls.
    Type: Grant
    Filed: December 8, 2003
    Date of Patent: November 7, 2006
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7128845
    Abstract: A printhead for an ink jet printer with an array 14 of ink ejection nozzles 22 formed from MEMS techniques. To protect the delicate nozzle structures, a nozzle guard 80 covers the exterior surface of the array 14. A corresponding array of apertures 84 is formed in the guard 80. To attach the guard 80 to the silicon substrate 16 carrying the nozzles 22, alignment formations 148 configured for engagement with complementary formations on a nozzle guard 86. For precise registration between the nozzles 22 and the respective apertures 86 in the guard 80, the alignment formations 148 may be formed using the same etching and deposition techniques used to form the nozzles 22. To protect the fragile nozzle structures 22 from inadvertent contact with the struts 86 during assembly, the nozzles 22 are reinforced by sacrificial material 152 which subsequently removed by an oxygen plasma etch 154.
    Type: Grant
    Filed: January 24, 2002
    Date of Patent: October 31, 2006
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7129176
    Abstract: An optical device includes a semiconductor substrate and an optical part having a plurality of columnar members disposed on the substrate. Each columnar member is disposed in a standing manner and adhered each other so that the optical part is provided. The optical part is integrated with the substrate. This optical part has high design freedom.
    Type: Grant
    Filed: January 20, 2004
    Date of Patent: October 31, 2006
    Assignee: Denso Corporation
    Inventors: Junji Oohara, Kazuhiko Kano, Yoshitaka Noda, Yukihiro Takeuchi, Toshiyuki Morishita
  • Patent number: 7128842
    Abstract: A layer of polyimide or polysilicon is used as a mask in vapor hydrogen fluoride etching. Both non-photosensitive and photosensitive type polyimide may be used. A non-photosensitive polyimide mask requires the use of photoresist for patterning with a lithographic mask. Alternatively, photosensitive type polyimide may be patterned directly with the use of a lithographic mask. The resulting polyimide mask enables the etching of very small features with great uniformity. Such etching may be used to expose micropoint emitters of field emission devices.
    Type: Grant
    Filed: November 27, 2000
    Date of Patent: October 31, 2006
    Inventors: Tianhong Zhang, John K. Lee
  • Patent number: 7128843
    Abstract: A process for fabricating monolithic membrane structures having air gaps is disclosed, comprising the steps of: providing a wafer; depositing and patterning a protective layer on the wafer; providing a trench in the wafer; depositing and patterning a metal in the trench; depositing and patterning a sacrificial layer on the metal; depositing and patterning a membrane pad on the sacrificial layer; providing a polymeric film on the protective layer and sacrificial layer, wherein part of the polymeric film has a tensile stress; and releasing part of the polymeric film from the protective layer and sacrificial layer, wherein the tensile stress of a portion of the polymeric film releases the portion of the polymeric film from the wafer and generates the air gap.
    Type: Grant
    Filed: February 24, 2004
    Date of Patent: October 31, 2006
    Assignee: HRL Laboratories, LLC
    Inventor: Sarabjit Mehta
  • Patent number: 7130103
    Abstract: Provided is an optical modulator capable of forming an optical gap easily and accurately without having to perform underetching to the sacrifice layer. An optical modulator includes a first substrate provided with a first concave portion in which the bottom part becomes a moving part, and a movable reflection film being formed on the moving part; and a second substrate provided with a second concave portion having a diameter that is smaller than the diameter of the first concave portion at a position facing the first concave portion, and a fixed reflection film being formed on the bottom part of the second concave portion; wherein the depth of the first concave portion prescribes the movable range of the movable reflection film, and an optical gap is prescribed based on the spacing between movable reflection film and the fixed reflection film.
    Type: Grant
    Filed: February 16, 2005
    Date of Patent: October 31, 2006
    Assignee: Seiko Epson Corporation
    Inventor: Akihiro Murata
  • Patent number: 7108584
    Abstract: The method and apparatus manufacture a liquid drop ejecting head. The method and apparatus blast particles on a substrate having on an upper layer a patterned mask layer made of an organic material and on a lower layer a driver circuit for ejecting a liquid drop to thereby perform an etching process on parts of the substrate exposed from the mask layer. The etching process is performed in an ionic atmosphere ionized with a polarity opposite to a charged polarity generated in the substrate when the substrate is subjected to etching.
    Type: Grant
    Filed: September 26, 2002
    Date of Patent: September 19, 2006
    Assignee: Fuji Photo Film Co., Ltd.
    Inventor: Ryoichi Yamamoto
  • Patent number: 7108819
    Abstract: A tool for embossing high aspect ratio microstructures is provided, wherein the microstructures provide decreased surface reflection and increased transmission through an optical component even at high incident angles. The tool is fabricated by a process that comprises anisotropic etching of columnar pits in a silicon substrate using inductively coupled plasma, followed by isotropic reactive ion etching of the columnar pits to create relatively pointed obelisks. The silicon substrate is then preferably rinsed to remove remaining photoresist prior to vapor depositing a conductive layer thereon. Finally, a metal is electroformed over the conductive layer to form the embossing tool. The embossing tool is then pressed against an optical coating, for example a polymer sheet, to create microstructures having aspect ratios from 1 to 5.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: September 19, 2006
    Assignee: The Boeing Company
    Inventors: Alan B Harker, Jeffrey F DeNatale, Dennis R Strauss
  • Patent number: 7107668
    Abstract: A photosensitive material is coated on an insulating material (13) stacked on a substrate (1) (FIG. 16A), and exposed and developed using a mask having a light-shielding film capable of controlling a light transmittance from 100% to 0% annularly and continuously to form a spiral photosensitive material (FIG. 16B). After conducting treatment at a high temperature, the insulating material under the photosensitive material is spirally formed by etching (FIG. 16C). A metal (12) is stacked on the substrate (FIG. 16D), and a photosensitive material is coated (FIG. 16E). The photosensitive material is exposed and developed using a mask having an annular light-shielding film with a light transmittance of 0% to leave the photosensitive material covering only the metal on the base of the spiral structure (FIG. 16F). After treatment at a high temperature is conducted and the metal exposed is etched (FIG. 16G), the photosensitive material is removed (FIG. 16H).
    Type: Grant
    Filed: April 2, 2004
    Date of Patent: September 19, 2006
    Inventor: Takashi Nishi
  • Patent number: 7105097
    Abstract: A method of forming an opening through a substrate includes etching into the substrate from a first side so as to form a first portion of the opening, etching into the substrate from a second side opposite the first side so as to form a second portion of the opening, continuing etching into the substrate from at least one of the first side and the second side toward the other of the first side and the second side so as to communicate the first portion and the second portion of the opening, and etching into the substrate from an interface between the first portion and the second portion of the opening, including etching toward the second side of the substrate and forming a third portion of the opening.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: September 12, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Jeffery S. Hess
  • Patent number: 7101502
    Abstract: Methods for forming openings having predetermined shapes in a substrate and apparatuses with these openings. The methods may be used to form assemblies which include the substrate with its openings and elements which are disposed in the openings. In one example of a method, each of the elements include an electrical component and are assembled into one of the openings by a fluidic self assembly process. In an particular example of a method to create such an opening, the substrate is etched through a first patterned mask and is later etched through a second patterned mask. Typically, the second patterned mask is aligned relative to the opening created by etching through the first patterned mask and has an area of exposure which is smaller than an area of exposure through the first patterned mask.
    Type: Grant
    Filed: May 23, 2002
    Date of Patent: September 5, 2006
    Assignee: Alien Technology Corporation
    Inventors: John Stephen Smith, Mark A. Hadley, Gordon S. W. Craig, Frank Lowe
  • Patent number: 7101724
    Abstract: The present invention relates to MEM switches. More specifically, the present invention relates to a system and method for making MEM switches having a common ground plane. One method for making MEM switches includes: patterning a common ground plane layer on a substrate; forming a dielectric layer on the common ground plane layer; depositing a DC electrode region through the dielectric layer to contact the common ground plane layer; and depositing a conducting layer on the DC electrode region so that regions of the conducting layer contact the DC electrode region, so that the common ground plane layer provides a common ground for the regions of the conducting layer.
    Type: Grant
    Filed: November 20, 2004
    Date of Patent: September 5, 2006
    Assignee: Wireless MEMs, Inc.
    Inventor: Chia-Shing Chou
  • Patent number: 7097779
    Abstract: A processing system and method for chemically treating a TERA layer on a substrate. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate. In one embodiment, the system for processing a TERA layer includes a plasma-enhanced chemical vapor deposition (PECVD) system for depositing the TERA layer on the substrate, an etching system for creating features in the TERA layer, and a processing subsystem for reducing the size of the features in the TERA layer.
    Type: Grant
    Filed: July 6, 2004
    Date of Patent: August 29, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Aelan Mosden, Asao Yamashita
  • Patent number: 7098143
    Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.
    Type: Grant
    Filed: April 22, 2004
    Date of Patent: August 29, 2006
    Assignee: Texas Instruments Incorporated
    Inventor: Darwin Rusli
  • Patent number: 7098137
    Abstract: A method of making a micro corner cube array includes the steps of: providing a substrate, at least a surface portion of which consists of cubic single crystals and which has a surface that is substantially parallel to {111} planes of the crystals; and dry-etching the surface of the substrate anisotropically with an etching gas that is reactive with the substrate, thereby forming a plurality of unit elements of the micro corner cube array on the surface of the substrate. Each of the unit elements is made up of a number of crystal planes that have been etched at a lower etch rate than the {111} planes of the crystals.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: August 29, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ichiro Ihara, Kiyoshi Minoura, Yutaka Sawayama
  • Patent number: 7097776
    Abstract: A low cost method for fabricating microneedles is provided. According to one embodiment, the fabrication method includes the steps of: providing a substrate; forming a metal-containing seed layer on the top surface of the substrate; forming a nonconductive pattern on a portion of the seed layer; plating a first metal on the seed layer and over the edge of the nonconductive pattern to create a micromold with an opening that exposes a portion of the nonconductive pattern, the opening having a tapered sidewall surface; plating a second metal onto the micromold to form a microneedle in the opening; separating the micromold with the microneedle formed therein from the seed layer and the nonconductive pattern; and selectively etching the micromold so as to release the microneedle.
    Type: Grant
    Filed: October 22, 2004
    Date of Patent: August 29, 2006
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventor: Ramesh Govinda Raju
  • Patent number: 7097775
    Abstract: A microfluidic delivery system substrate is coated with ultra-nanocrystalline diamond (UNCD) or with a thin ceramic film, such as alumina or zirconia, that is applied by ion-beam assisted deposition; assuring that the device is impermeably sealed, to prevent the substrate from being dissolved by hostile environments and to protect the molecules from premature release or undesired reaction with hostile environments. The UNCD coating may be selectively patterned by doping to create electrically conductive areas that can be used as an electrically activated release mechanism for drug delivery. The UNCD coating provides a conformal coating, of approximately uniform thickness, around sharp corners and on high aspect-ratio parts, assuring impermeability and strength despite the need to coat difficult shapes. The microfluidic delivery system is suitable for use as an iontophoresis device, for transport of molecule, having a substrate, a reservoir in the substrate for containing the molecules.
    Type: Grant
    Filed: March 11, 2002
    Date of Patent: August 29, 2006
    Assignee: Second Sight Medical Products, Inc.
    Inventors: Robert J. Greenberg, Brian V. Mech
  • Patent number: 7090781
    Abstract: An extremely small, self-moved, impact driven microactuator is disclosed that has a movable mass member electrostatically driven and which eliminates the need for it to be assembled individually. The microactuator includes a fixing member (1) securely connected to a pedestal part (14), an elastic support beam member (2) having one end securely connected to the fixing member, a movable mass member (3) fastened to the other end of the elastic support beam member, a driving electrode and a stopper member (4, 5) each securely connected to the pedestal part and spacedly juxtaposed with the movable mass member, and a power supply circuit (9) for applying a voltage between the movable mass and driving electrode members.
    Type: Grant
    Filed: June 25, 2004
    Date of Patent: August 15, 2006
    Assignee: Japan Science and Technology Agency
    Inventors: Hiroyuki Fujita, Dai Kobayashi, Makoto Mita, Shouichi Tensaka
  • Patent number: 7083737
    Abstract: A micro-actuator having a stage capable of a see-saw motion and a method for its manufacture are disclosed. In the micro-actuator according to the present invention, a plurality of parallel driving comb-type electrodes are formed on the bottom of the stage, and a plurality of parallel fixed comb-type electrodes are formed on a base plate. At both sides of the stage is a torsion bar that enables the see-saw motion. The torsion bar is supported by a frame comprised of a first frame layer and a second frame layer. The torsion bar and the first frame layer form one body. The first and second frame layers are bonded by a metal eutectic bonding layer between metal layers.
    Type: Grant
    Filed: March 4, 2004
    Date of Patent: August 1, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-ho Lee, Young-chul Ko, Do-hyun Kong
  • Patent number: 7084051
    Abstract: A purpose of the invention is to provide a manufacturing method for a semiconductor substrate in which a high quality strained silicon channel can easily be formed without sacrificing the processing efficiency of a wafer and to provide a manufacturing method for a semiconductor device wherein the driving performance of a PMOS transistor, in addition to that of an NMOS transistor, can be improved. The invention provides a manufacturing method for a semiconductor substrate with the steps of: forming a SiGe film on the top surface of a substrate having a silicon monocrystal layer in the (111) or (110) plane direction as the surface layer; introducing buried crystal defects into the above described substrate by carrying out ion implantation and annealing treatment; and forming a semiconductor film on the above described SiGe film.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: August 1, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Takashi Ueda
  • Patent number: 7081623
    Abstract: An apparatus for an ion trap includes a semiconductor or dielectric wafer with front and back surfaces, a sequence of alternating conductive and dielectric layers formed over said front surface, and a bottom conductive layer. The sequence includes top and middle conductive layers, wherein the middle conductive layer is closer to the wafer than the top conductive layer. The middle conductive layer includes a substantially right cylindrical cavity that crosses a width of the middle conductive layer. The top and bottom conductive layers cap respective first and second ends of the cavity. The top conductive layer includes a hole that forms a first access port to the cavity. The wafer includes via through the width of the wafer. The via provides another access to the cavity via the back surface of the wafer. The wafer is substantially thicker than the sequence of layers.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: July 25, 2006
    Assignee: Lucent Technologies Inc.
    Inventors: Chien-Shing Pai, Stanley Pau
  • Patent number: 7078293
    Abstract: A method for fabricating an optical interference display cell is described. A first electrode and a sacrificial layer are sequentially formed on a transparent substrate and at least two openings are formed in the first electrode and the sacrificial layer to define a position of the optical interference display cell. An insulated heat-resistant inorganic supporter is formed in each of the openings. A second electrode is formed on the sacrificial layer and the supporters. Finally, a remote plasma etching process is used for removing the sacrificial layer.
    Type: Grant
    Filed: March 11, 2004
    Date of Patent: July 18, 2006
    Assignee: Prime View International Co., Ltd.
    Inventors: Wen-Jian Lin, Hsiung-Kuang Tsai
  • Patent number: 7075701
    Abstract: Described are MEMS mirror arrays monolithically integrated with CMOS control electronics. The MEMS arrays include polysilicon or polysilicon-germanium components that are mechanically superior to metals used in other MEMS applications, but that require process temperatures not compatible with conventional CMOS technologies. CMOS circuits used with the polysilicon or polysilicon-germanium MEMS structures use interconnect materials that can withstand the high temperatures used during MEMS fabrication. These interconnect materials include doped polysilicon, polycides, and tungsten metal.
    Type: Grant
    Filed: November 23, 2005
    Date of Patent: July 11, 2006
    Assignee: Active Optical Networks, Inc.
    Inventors: Vlad Novotny, Bharat Sastri, Chitranjan N. Reddy
  • Patent number: 7074637
    Abstract: There are many inventions described and illustrated herein. In one aspect, there is described a thin film or wafer encapsulated MEMS, and technique of fabricating or manufacturing a thin film or wafer encapsulated MEMS employing anti-stiction techniques. In one embodiment, after encapsulation of the MEMS, an anti-stiction channel is formed in the encapsulation layer or substrate, thereby providing “access” to the chamber containing some or all of the active members or electrodes of the mechanical structures. Thereafter, an anti-stiction fluid (for example, gas or gas-vapor) is introduced into the chamber via the anti-stiction channel. The anti-stiction fluid may deposit on one, some or all of the active members of the mechanical structures thereby providing an anti-stiction layer (for example, a monolayer coating or self-assembled monolayer) and/or out-gassing molecules on such members or electrodes.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: July 11, 2006
    Assignee: Robert Bosch GmbH
    Inventors: Markus Lutz, Aaron Partridge
  • Patent number: 7070699
    Abstract: A bistable microelectromechanical system (MEMS) based system comprises a micromachined beam having a first stable state, in which the beam is substantially stress-free and has a specified non-linear shape, and a second stable state. The curved shape may comprises a simple curve or a compound curve. In embodiments, the boundary conditions for the beam are fixed boundary conditions, bearing boundary conditions, spring boundary conditions, or a combination thereof. The system may further comprise an actuator arranged to move the beam between the first and second stable states and a movable element that is moved between a first position and a second position in accordance with the movement of the beam between the first and second stable states. The actuator may comprise one of a thermal actuator, an electrostatic actuator, a piezoelectric actuator and a magnetic actuator. The actuator may further comprise a thermal impact actuator or a zippering electrostatic actuator.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: July 4, 2006
    Assignee: Xerox Corporation
    Inventors: Joel A. Kubby, Fuqian Yang, Jun Ma, Kristine A. German, Peter M. Gulvin
  • Patent number: 7071031
    Abstract: A vertically integrated structure includes a micro-electromechanical system (MEMS) and a chip for delivering signals to the MEMS. The structure includes a metal stud connecting a surface of the chip and the MEMS; the MEMS has an anchor portion having a conducting pad on an underside thereof contacting the metal stud. The MEMS is spaced from the chip by a distance corresponding to a height of the metal stud, and the MEMS includes a doped region in contact with the conducting pad. In particular, the MEMS may include a cantilever structure, with the end portion including a tip extending in the vertical direction. A support structure (e.g. of polyimide) may surround the metal stud and contact both the underside of the MEMS and the surface of the chip. A temporary carrier plate is used to facilitate handling of the MEMS and alignment to the chip.
    Type: Grant
    Filed: May 28, 2003
    Date of Patent: July 4, 2006
    Assignee: International Business Machines Corporation
    Inventors: H. Bernhard Pogge, Michel Despont, Ute Drechsler, Peter Vettiger, Roy Yu
  • Patent number: 7063798
    Abstract: A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10) is obtained starting from a small surface port of the trench (4) by anisotropic etching of the trench. The microchannel (10) is then completely buried in the substrate (2) by growing a microcrystalline structure to enclose the small surface port.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: June 20, 2006
    Assignee: STMicroelectronics S.r.l.
    Inventors: Alessio M. D'arrigo Guiseppe, Rosario C. Spinella, Guiseppe Arena, Simona Lorenti
  • Patent number: 7063796
    Abstract: A method of manufacturing a micromechanical component has a substrate (1), a movable sensor structure (6) in a micromechanical functional layer (5) located over the substrate; a first sealing layer (8) on the first micromechanical functional layer (5) which is at least partly structured; a second micromechanical functional layer (10) on the first sealing layer (8), which has at least one sealing function and is anchored at least partly in the first micromechanical functional layer (5); and a second sealing layer (8) on the second micromechanical functional layer (10). The sensor structure (6) is provided with trenches (7) whose width is not larger than a maximum trench width (66), which is sealable by the first sealing layer (8) in the form of plugs (9) which do not extend to the trench bottoms.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: June 20, 2006
    Assignee: Robert Bosch GmbH
    Inventor: Markus Lutz
  • Patent number: 7060197
    Abstract: In a mass flow sensor having a layered structure on the upper side of a silicon substrate (1), and having at least one heating element (8) patterned out of a conductive layer in the layered structure, thermal insulation between the heating element (8) and the silicon substrate (1) is achieved by way of a silicon dioxide block (5) which is produced beneath the heating element (8) either in the layered structure on the silicon substrate (1) or in the upper side of the silicon substrate (1). As a result, the sensor can be manufactured by surface micromechanics, i.e. without wafer back-side processes.
    Type: Grant
    Filed: June 8, 2002
    Date of Patent: June 13, 2006
    Assignee: Robert Bosch GmbH
    Inventors: Matthias Fuertsch, Frank Fischer, Lars Metzger, Frieder Sundermeier
  • Patent number: 7052616
    Abstract: There is disclosed a method providing micro-scale devices, nano-scale devices, or devices having both nano-scale and micro-scale features. The method of the invention comprises fluidic assembly and various novel devices produced thereby. A variety of nanofluidic and molecular electronic type devices and structures having applications such as filtering and genetic sequencing are provided by the invention.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: May 30, 2006
    Assignee: The Penn State Research Foundation
    Inventors: Stephen J. Fonash, Daniel J. Hayes, Wook Jun Nam, Joseph Cuiffi
  • Patent number: 7054052
    Abstract: A method of combining components to form an integrated device, wherein at least one first component is provided on a first surface of a sacrificial substrate, and at least one second component is provided on a first surface of a non-sacrificial substrate. At least one support structure is formed on at least one of the first surfaces of the sacrificial substrate, and the non-sacrificial substrate, respectively, such that said at least one support structure is extended outwardly from at least one of the first surfaces. The sacrificial substrate carrying the first component, and the non-sacrificial substrate carrying the second component, respectively, are bonded, so that the first and second surfaces will be facing one another with a distance defined by a thickness of the support structure. At least a part of the sacrificial substrate is removed. The first component and second components are interconnected.
    Type: Grant
    Filed: September 4, 2003
    Date of Patent: May 30, 2006
    Inventors: Frank Niklaus, Göran Stemme
  • Patent number: 7052617
    Abstract: A process for producing multiple undercut profiles in a single material. A resist pattern is applied over a work piece and a wet etch is performed to produce an undercut in the material. This first wet etch is followed by a polymerizing dry etch that produces a polymer film in the undercut created by the first wet etch. The polymer film prevents further etching of the undercut portion during a second wet etch. Thus, an undercut profile can be obtained having a larger undercut in an underlying portion of the work piece, utilizing only a single resist application step. The work piece may be a multi-layer work piece having different layers formed of the same material, or it may be a single layer of material.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: May 30, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Karen Huang, Christophe Pierrat
  • Patent number: 7049164
    Abstract: The current invention provides for encapsulated release structures, intermediates thereof and methods for their fabrication. The multi-layer structure has a capping layer, that preferably comprises silicon oxide and/or silicon nitride, and which is formed over an etch resistant substrate. A patterned device layer, preferably comprising silicon nitride, is embedded in a sacrificial material, preferably comprising polysilicon, and is disposed between the etch resistant substrate and the capping layer. Access trenches or holes are formed in to capping layer and the sacrificial material are selectively etched through the access trenches, such that portions of the device layer are release from sacrificial material. The etchant preferably comprises a noble gas fluoride NGF2x (wherein Ng=Xe, Kr or Ar: and where x=1, 2 or 3). After etching that sacrificial material, the access trenches are sealed to encapsulate released portions the device layer between the etch resistant substrate and the capping layer.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: May 23, 2006
    Assignee: Silicon Light Machines Corporation
    Inventor: Mike Bruner
  • Patent number: 7045069
    Abstract: A method of fabricating microstructural components, microparts assemblies and microparts is disclosed. The method includes fabricating a unidirectional metal matrix composite made of materials selected to allow precise etching of different structural elements of the given composite without damage to each other. Cutting a composite to form slices or sections. Etching a matrix entirely out will produce wide assortment of microparts. Partial removal of matrix will form an array of microprotrusions protruding from a substrate. Etching out the microprotrusions cores will form hollow microprotrusions. The method of invention is suitable for fabricating of variety of microcomponents. For example: microneedles—a medical microdevice component having micron features, arrays of high strength micropins and micropunches, and precisely controlled unique microstructural surfaces.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: May 16, 2006
    Inventor: Gennady Ozeryansky
  • Patent number: 7045052
    Abstract: A method of manufacture for optical spectral filters with omnidirectional properties in the visible, near IR, mid IR and/or far IR (infrared) spectral ranges is based on the formation of large arrays of coherently modulated waveguides by electrochemical etching of a semiconductor wafer to form a pore array. Further processing of said porous semiconductor wafer optimizes the filtering properties of such a material. The method of filter manufacturing is large scale compatible and economically favorable. The resulting exemplary non-limiting illustrative filters are stable, do not degrade over time, do not exhibit material delamination problems and offer superior transmittance for use as bandpass, band blocking and narrow-bandpass filters. Such filters are useful for a wide variety of applications including but not limited to spectroscopy, optical communications, astronomy and sensing.
    Type: Grant
    Filed: October 16, 2003
    Date of Patent: May 16, 2006
    Assignee: Lake Shore Cryotronics, Inc.
    Inventors: Vladimir Kochergin, Philip Swinehart
  • Patent number: RE39143
    Abstract: A method for fabricating a wafer-pair having at least one recess in one wafer and the recess formed into a chamber with the attaching of the other wafer which has a port plugged with a deposited layer on its external surface. The deposition of the layer may be performed in a very low pressure environment, thus assuring the same kind of environment in the sealed chamber. The chamber may enclose at least one device such as a thermoelectric sensor, bolometer, emitter or other kind of device. The wafer-pair typically will have numerous chambers, with devices, respectively, and may be divided into a multiplicity of chips.
    Type: Grant
    Filed: December 3, 2001
    Date of Patent: June 27, 2006
    Assignee: Honeywell International Inc.
    Inventors: R. Andrew Wood, Jeffrey A. Ridley, Robert E. Higashi
  • Patent number: RE39273
    Abstract: A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. There is then formed upon the oxygen containing plasma etchable microelectronics layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while employing the patterned photoresists layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching a hard mask material from which is formed the hard mask layer.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Syun-Ming Jang, Ming-Hsin Huang