With Measuring, Testing, Or Inspecting Patents (Class 216/59)
  • Patent number: 7204934
    Abstract: A method for processing recess etch operations in substrates is provided including forming a hard mask over the substrate and etching a trench in the substrate using the hard mask, and forming a dielectric layer over the hard mask and in the trench, where the dielectric layer lines the trench. A conductive material is then applied over the dielectric layer such that a blanket of the conductive material lies over the hard mask and fills the trench, and the conductive material is etched to substantially planarize the conductive material. The etching of the conductive material triggers an endpoint just before all of the conductive material is removed from over the dielectric layer that overlies the bard mask. The conductive material is recess etched to remove the conductive material over the dielectric layer that overlies the hard mask and removes at least part of the conductive material from within the trench.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: April 17, 2007
    Assignee: Lam Research Corporation
    Inventors: Linda Braly, Vahid Vahedi, Erik Edelberg, Alan Miller
  • Patent number: 7199053
    Abstract: Disclosed is a method for detecting an end-point of a CMP process of a semiconductor device. More specifically, when all polishing processes are performed using a nitride film as a polishing barrier film, a buffer layer including nitrogen is formed on the nitride film and a polishing process is performed. Then, the concentration of NO from ammonia gas generated from the buffer layer is detected so that the nitride film may be polished to a desired target without damage of the nitride film. As a result, an end-point can be set.
    Type: Grant
    Filed: June 28, 2004
    Date of Patent: April 3, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventor: Jong Goo Jung
  • Patent number: 7192505
    Abstract: There is provided by this invention a wafer probe for measuring plasma and surface characteristics in plasma processing environment that utilizes integrated sensors on a wafer substrate. A microprocessor mounted on the substrate receives input signals from the integrated sensors to process, store, and transmit the data. A wireless communication transceiver receives the data from the microprocessor and transmits information outside of the plasma processing system to a computer that collects the data during plasma processing. The integrated sensors may be dual floating Langmuir probes, temperature measuring devices, resonant beam gas sensors, or hall magnetic sensors. There is also provided a self-contained power source that utilizes the plasma for power that is comprised of a topographically dependent charging device or a charging structure that utilizes stacked capacitors.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: March 20, 2007
    Assignee: Advanced Plasma, Inc.
    Inventors: Gregory A. Roche, Leonard J. Mahoney, Daniel C. Carter, Steven J. Roberts
  • Patent number: 7182879
    Abstract: A plasma processing method, in which a process gas is introduced into an evacuated process chamber for subjecting the target object to a plasma processing. The plasma processing method is featured in that at least a part of the process gas exhausted from the process chamber is introduced again into the process chamber. A specified value is obtained by monitoring the state of the plasma of the process gas within the process chamber, and the introducing conditions of the process gas into the process chamber are controlled to adjust a predetermined property value to a regulated value.
    Type: Grant
    Filed: March 9, 2004
    Date of Patent: February 27, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Itsuko Sakai, Tokuhisa Ohiwa
  • Patent number: 7175777
    Abstract: A single, controlled etch step can be used to form a sharp tip feature along a sidewall of an etch feature. An etch process is used that is selective to a layer of tip material relative to the substrate upon which the layer is deposited. A lag can be created in the etch, such that the etch rate is slower near the sidewall. The sharp tip feature is formed from the same layer of material used to create the etch feature. The sharp tip feature can be used to decrease the minimum critical dimension of an etch process, such as may be due to the minimum resolution of a photolithographic process. The novel tip feature also can be used for other applications, such as to create a microaperture for a photosensitive device, or to create a micromold that can be used to form objects such as microlenses.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: February 13, 2007
    Assignee: National Semiconductor Corporation
    Inventors: André Paul Labonté, Lee James Jacobson
  • Patent number: 7172839
    Abstract: The object of the present invention is to provide a method for solving the problem of surface damage due to gallium ion irradiation that poses a problem when carrying out mask repair using currently established FIB techniques, and the problem of residual gallium, and to provide a device realizing this method. The device of the present invention has an electron beam lens barrel that can carry out processing, as well as an FIB lens barrel, provided inside the same sample chamber, which means that a mask repair method of the present invention, in correction processing to remove redundant sections such as a mask opaque defect, phase shift film bump defect or a glass substrate cut remnant defect, comprises a step of coarse correction by etching using a focused ion beam and a step of finishing processing using an electron beam, to remove surface damage due to gallium irradiation, and residual gallium.
    Type: Grant
    Filed: November 24, 2003
    Date of Patent: February 6, 2007
    Assignee: SII NanoTechnology Inc.
    Inventors: Yasuhiko Sugiyama, Junichi Tashiro, Anto Yasaka
  • Patent number: 7169440
    Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an oxygen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.
    Type: Grant
    Filed: September 30, 2002
    Date of Patent: January 30, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Vaidyanathan Balasubramaniam, Masaaki Hagiwara, Eiichi Nishimura, Kouichiro Inazawa
  • Patent number: 7160475
    Abstract: The present disclosure relates to a method for generating a three-dimensional microstructure in an object. In one embodiment, a method for fabricating a microscopic three-dimensional structure is provided. A work piece is provided that includes a target area at which the three-dimensional structure is to be fabricated. The target area has a plurality of virtual dwell points. A shaped beam is provided to project onto the work piece. The intersection of the shaped beam with the work piece defines a beam incidence region that has a desired shape. The beam incidence region is sufficiently large to encompass multiple ones of the virtual dwell points. The shaped beam is moved across the work piece such that different ones of the virtual dwell points come into it and leave it as the beam moves across the work piece thereby providing different doses to different ones of the virtual dwell points as the different dwell points remain in the beam incidence region for different lengths of time during the beam scan.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: January 9, 2007
    Assignee: FEI Company
    Inventor: Lawrence Scipioni
  • Patent number: 7153444
    Abstract: Provided is a method and apparatus for controlling a bias voltage over a wide range and for de-coupling dual radio frequency (RF) currents to allow for independent control of plasma density and ion energy of a plasma for processing a substrate. An exemplary apparatus provides a plasma processing chamber which includes a bottom electrode configured to hold a substrate and first and second RF power supplies being connected to the bottom electrode. Also included is a top electrode which is electrically isolated from a top ground extension. A filter array defining a set of filter settings is included. A switch is coupled to the top electrode and the switch is configured to interconnect the top electrode to one of the filter settings. The filter settings are configured to enable or disable RF current generated from one or both of the RF power supplies from passing through the top electrode.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: December 26, 2006
    Assignee: Lam Research Corporation
    Inventor: Andreas Fischer
  • Patent number: 7147793
    Abstract: An etch profile tailoring system (100), for use with an etching process carried out on a wafer (130), has a scavenging plate (170) with a baseline etch profile, and at least one etch profile tuning structure (such as a plug) (160) replaceably disposed with respect to the scavenging plate (170) and configured to alter the baseline etch profile during the etching process so as to arrive at a desired etch profile. A method of performing maintenance on an etch profile tailoring system (100) involves the steps of performing an etching process on a wafer in accordance with a desired etch profile, determining whether or not maintenance should be performed, and (if the maintenance decision indicates that maintenance should be performed) replacing with a second plug before conducting an etching process on additional wafers.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: December 12, 2006
    Assignee: Tokyo Electron Limited
    Inventor: Steven Fink
  • Patent number: 7138067
    Abstract: In a plasma processing system, a method of tuning of a set of plasma processing steps is disclosed. The method includes striking a first plasma comprising neutrals and ions in a plasma reactor of the plasma processing system. The method also includes etching in a first etching step a set of layers on a substrate; positioning a movable uniformity ring around the substrate, wherein a bottom surface of the uniformity ring is about the same height as a top surface of the substrate; and striking a second plasma consisting essentially of neutrals in the plasma reactor of the plasma processing system. The method further includes etching in a second etching step the set of layers on the substrate; and wherein the etching in the first step and the etching in the second step are substantially uniform.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: November 21, 2006
    Assignee: Lam Research Corporation
    Inventors: Vahid Vahedi, John Daugherty, Harmeet Singh, Anthony Chen
  • Patent number: 7135123
    Abstract: The backside navigation method of the present invention includes milling a fiducial opening through the substrate of an integrated circuit. The milling process is stopped when the fiducial opening reaches the bottom of a trench isolation structure. The trench isolation structure delineated by the fiducial opening may be imaged and registered to a computer aided design layout image to achieve sub-micron navigation resolution.
    Type: Grant
    Filed: January 14, 2004
    Date of Patent: November 14, 2006
    Assignee: Credence Systems Corporation
    Inventors: Mark Alan Thompson, Erwan Le Roy, Theodore Lundquist, William B. Thompson, Catherine Kardach
  • Patent number: 7115210
    Abstract: Disclosed is a method and system for detecting abnormal plasma discharge that is useful in, for example, detecting plasma leakage in a reactive ion etching (RIE) chamber. The system includes electrical contacts connected to the chamber that provide an input signal to the chamber. This input signal can be generated by a radio frequency (RF) generator that is connected to the electrical contacts. A variable power controller connected to the RF generator gradually increases (ramps) the power of the input signal being supplied to the chamber.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: October 3, 2006
    Assignee: International Business Machines Corporation
    Inventors: Robert A. Calderoni, June Cline, Kellie L. Dutra, Ronald G. Meunier, Joseph P. Walko, Justin Wai-chow Wong
  • Patent number: 7115211
    Abstract: A method and system for determining an endpoint in a (near) real-time environment using statistical process control. By utilizing such control, an endpoint of a semiconductor process (e.g., an etch) can be monitored. Monitoring may lead to increased yields by avoiding or reducing error conditions (e.g., under- or over-etching).
    Type: Grant
    Filed: August 12, 2004
    Date of Patent: October 3, 2006
    Assignee: Tokyo Electron Limited
    Inventor: Deana R. Delp
  • Patent number: 7112288
    Abstract: Methods are provided for delineating different layers and interfaces for inspection of a semiconductor wafer, wherein a sectioned portion of a wafer is subjected to a reactive ion etch process before inspection using a scanning electron microscope.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: September 26, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Fred Y. Clark, Andrew L. Vance, David G. Farber
  • Patent number: 7105100
    Abstract: A system and method for distributing gas to a substrate in a dry etch chamber make use of different flow channels to distribute the gas to different portions of a substrate. A first flow channel can be oriented to distribute gas to an inner portion of the substrate. A second flow channel can be oriented to distribute gas to an outer portion of the substrate. With different flow channels, the system and method enable separate control of gas distribution for different portions of the substrate. In particular, the flow channels allow separate control of gas flow rate, concentration, and flow time for different areas of the substrate. In this manner, gas distribution can be selectively controlled to compensate for different etch rates across the substrate surface. Also, gas distribution can be controlled as a function of etch rate patterns exhibited by different etch gasses used in successive process steps.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: September 12, 2006
    Assignee: Applied Materials, Inc.
    Inventor: Haruhiro H. Goto
  • Patent number: 7105080
    Abstract: Method for manufacturing a workpiece by a vacuum treatment process includes providing a vacuum treatment system with first second parts in a vacuum chamber. Either a sensor or an adjusting element with first signal connection is mounted on the second part. An electronic unit in the chamber has a reference potential and a second electric signal connection. The first part is connected to a system reference potential. A workpiece goes into the chamber and the method includes operating the second part at a further electric potential different from the system reference potential by at least 12 V. The method includes connecting the first electric signal connection to the second electric signal connection and maintaining the reference connection during operation on the further electric potential by metallically connecting the reference connection to the second part.
    Type: Grant
    Filed: December 31, 2002
    Date of Patent: September 12, 2006
    Assignee: OC Oerlikon Balzers AG
    Inventor: Felix Mullis
  • Patent number: 7105098
    Abstract: New methods for fabrication of silicon microstructures have been developed. In these methods, an etching delay layer is deposited and patterned so as to provide differential control on the depth of features being etched into a substrate material. Compensation for etching-related structural artifacts can be accomplished by proper use of such an etching delay layer.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: September 12, 2006
    Assignee: Sandia Corporation
    Inventors: Randy J. Shul, Christi G. Willison, W. Kent Schubert, Ronald P. Manginell, Mary-Anne Mitchell, Paul C. Galambos
  • Patent number: 7094355
    Abstract: This invention provides a local dry etching method comprising the step of removing an oxide film formed on the surface of a semiconductor water before unevenness on the semiconductor wafer is removed by scanning the surface of the semiconductor wafer at a controlled relative speed with a nozzle for applying a flow of activated species gas to the surface of the semiconductor wafer. The removal of this oxide film is carried out by widening an etching profile and a scan pitch and making the nozzle speed constant, and then flattening is carried out in the same local dry etching apparatus. For flattening, the nozzle speed is changed for each area according to initial unevenness.
    Type: Grant
    Filed: July 22, 2003
    Date of Patent: August 22, 2006
    Assignee: Speedfam Co., Ltd.
    Inventors: Michihiko Yanagisawa, Tadayoshi Okuya
  • Patent number: 7087498
    Abstract: A method for forming a trench in a semiconductor silicon substrate. An anti-reflective coating layer and a photoresist layer are formed over the substrate and patterned in accordance with a location for the trench. During the trench etch into the silicon substrate, the etch environment is monitored to detect the material of the anti-reflective coating layer. The etch process is controlled in response to detecting the removal of this material and the known etch rate differential between the anti-reflective coating material layer and the silicon substrate.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: August 8, 2006
    Assignee: Agere Systems Inc.
    Inventors: Mario Pita, Milton Beachy, Gerald W. Gibson, Jr.
  • Patent number: 7081209
    Abstract: A printed circuit board has a circuit trace on it and a solder mask over the circuit trace. The solder mask is removed from the printed circuit board using an ultra violet laser, to expose the circuit trace without damaging the circuit trace. A failure analysis is performed on the circuit trace of the printed circuit board.
    Type: Grant
    Filed: July 9, 2003
    Date of Patent: July 25, 2006
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Yian-Liang Kuo
  • Patent number: 7077971
    Abstract: Methods for detecting the endpoint of a photoresist stripping process provide O for reaction with the photoresist for a wafer to be stripped of photoresist. NO is also supplied for reaction with O not reacted with the photoresist. After substantially all the photoresist is stripped from the wafer, the rate of a reaction of O and NO to form NO2 increases, which increases the intensity of emitted light. An operation of detecting this increase in light intensity signals the endpoint of the photoresist stripping process.
    Type: Grant
    Filed: June 4, 2002
    Date of Patent: July 18, 2006
    Assignee: Lam Research Corporation
    Inventors: Tuqiang Ni, Wenli Collison
  • Patent number: 7052622
    Abstract: A method of determining the time to release of a movable feature in a multilayer substrate of silicon-containing materials including alternate layers of polysilicon and silicon oxide wherein a mass monitoring device determines the mass of a released feature, and the substrate is etched with anhydrous hydrogen fluoride until the substrate mass is equivalent to that of the released movable feature when the etch time is noted. A suitable mass monitoring device is a quartz crystal microbalance.
    Type: Grant
    Filed: October 8, 2002
    Date of Patent: May 30, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Jeffrey D. Chinn, Robert Z. Bachrach
  • Patent number: 7033518
    Abstract: A method of etching multi-layer films, the method including: (1) etching a plurality of layers according to etching parameters, (2) determining a plurality of optical characteristics each associated with one of the plurality of layers and determined during the etching of the associated one of the plurality of layers, and (3) determining dynamic etch progressions each based on one of the plurality of optical characteristics that is associated with a particular one of the plurality of layers undergoing the etching.
    Type: Grant
    Filed: June 24, 2003
    Date of Patent: April 25, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hui Ou Yang, Miao-Ju Hsu, Chao-Cheng Chen, Hun-Jan Tao
  • Patent number: 7033514
    Abstract: This invention relates to a method and apparatus for forming a micromachined device, where a workpiece is plasma etched to define a microstructure. The plasma etching is conducted in the presence of a magnetic field, which can be generated and manipulated by an electric field. The magnetic field effects the electrons present in the plasma by directing them to “collect” on a desired plane or surface of the workpiece. The electrons attract the ions of the plasma to etch the desired region of the a workpiece to a greater extent than other regions of the workpiece, thereby enabling the formation of more precise “cuts” in the workpiece to form specific shapes of microstructures. The magnetic field can be controlled in direction and intensity and substrate bias power can also be controlled during etching to precisely and accurately etch the workpiece.
    Type: Grant
    Filed: August 27, 2001
    Date of Patent: April 25, 2006
    Assignee: Micron Technology, Inc.
    Inventor: Neal Rueger
  • Patent number: 7029536
    Abstract: A processing system and method for chemical oxide removal (COR), wherein the processing system comprises a first treatment chamber and a second treatment chamber, wherein the first and second treatment chambers are coupled to one another. The first treatment chamber comprises a chemical treatment chamber that provides a temperature controlled chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate is exposed to a gaseous chemistry, such as HF/NH3, under controlled conditions including surface temperature and gas pressure. The second treatment chamber comprises a heat treatment chamber that provides a temperature controlled chamber, thermally insulated from the chemical treatment chamber. The heat treatment chamber provides a substrate holder for controlling the temperature of the substrate to thermally process the chemically treated surfaces on the substrate.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: April 18, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Thomas Hamelin, Jay Wallace, Arthur LaFlamme, Jr.
  • Patent number: 7029594
    Abstract: A plasma processing method for providing plasma processing to an object to be processed disposed within a vacuum processing chamber in which a process gas feeding device feeds process gas into the vacuum processing chamber, a wafer electrode is placed within the vacuum processing chamber for mounting the object to be processed, a wafer bias power generator applies self-bias voltage to the wafer electrode, and a plasma generator generates plasma within the vacuum processing chamber. The plasma processing method flattens either a positive side voltage or a negative side voltage of a voltage waveform of a high frequency voltage generated to the object at an arbitrary voltage.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: April 18, 2006
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Naoki Yasui, Masahiro Sumiya, Hitoshi Tamura, Seiichi Watanabe
  • Patent number: 7029593
    Abstract: A method for controlling CD of etch process defines difference between designed dimension and etched dimension as dimensional displacement and defines target value of the dimensional displacement. A plurality of samples are prepared in each group having different exposure ratios. The plurality of samples of each group are etched until etch end point is detected and then over-etched for uniform time interval after detecting the etch end point. Using etch end point and over-etch time, correlation function of the over-etch time to the etch end point time is determined and the over-etch time to the etch end point is determined using the correlation function.
    Type: Grant
    Filed: October 14, 2003
    Date of Patent: April 18, 2006
    Assignee: Samsung Electronics Co., Ltd,
    Inventors: Myeong-Cheol Kim, Yong-Hoon Kim, Jeong-Yun Lee
  • Patent number: 7025895
    Abstract: A plasma processing apparatus and method are capable of performing etching with high precision without damaging the semiconductor wafer. The plasma processing apparatus has a plasma generation power supply for generating a plasma within a processing chamber; a high-frequency power supply for applying a high frequency wave to a sample stage installed within the processing chamber; and control means for controlling the plasma generation power supply or the high-frequency power supply based on parameter settings for an output intensity and an output mode for each process step. In this regard, when the process steps are switched, the control means compares parameters for a current process step with those for a next process step and then switches either the output intensities or the output modes before switching the output modes or the output intensities, respectively.
    Type: Grant
    Filed: August 15, 2002
    Date of Patent: April 11, 2006
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Youji Takahashi, Makoto Kashibe
  • Patent number: 7018553
    Abstract: A method of adjusting plasma processing of a substrate in a plasma reactor having an electrode assembly. The method includes the steps of positioning the substrate in the plasma reactor, creating a plasma in the plasma reactor, monitoring optical emissions emanating from a plurality of different regions of the plasma in a direction substantially parallel to the surface of the substrate during plasma processing of the substrate, and determining an integrated power spectrum for each of the different plasma regions and comparing each of the integrated power spectra to a predetermined value. One aspect of the method includes utilizing an electrode assembly having a plurality of electrode segments and adjusting RF power delivered to the one or more electrode segments based on differences in the integrated power spectra from the predetermined value.
    Type: Grant
    Filed: April 18, 2003
    Date of Patent: March 28, 2006
    Assignee: Tokyo Electron Limited
    Inventors: Lianjun Liu, Wayne L. Johnson
  • Patent number: 7020577
    Abstract: In order to determine the dielectric constant of a layer deposited on a semiconducotr wafer (2), the density of the layer is obtained. To obtain that density, the wafer (2) without the layer is weighed in a weighing chamber (4) in which a weighing pan (7) supports the wafer on a weighing balance. The weight of the wafer is determined taking into account the buoyancy exerted by the air on the wafer (2). Then the layer is deposited on the wafer (2) and the weighing operation repeated. Alternatively a reference wafer may be used. If the material of the layer is known, the weight of the layer can be used to derive its density using a thickness measurement. Alternatively, if the density is known, the thickness can be obtained.
    Type: Grant
    Filed: June 29, 2001
    Date of Patent: March 28, 2006
    Assignee: Metryx Limited
    Inventor: Robert John Wilby
  • Patent number: 7014787
    Abstract: This invention relates to a method for etching an organic insulating film used in the production of semiconductor devices. A sample to be etched on which a low dielectric constant organic insulating film is formed is etched by generating a plasma from hydrogen gas and nitrogen gas or ammonia gas, and controlling the gas flow rate and pressure so that the light emission spectral intensity ratio of hydrogen atom and cyan molecule in the plasma comes to a prescribed value. By this method, a low dielectric constant organic insulating film as an insulating film between layers can be etched without using any etch stop layer so that bottom surfaces of trenches and holes for electrical wiring become flat.
    Type: Grant
    Filed: April 1, 2004
    Date of Patent: March 21, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Michinobu Mizumura, Ryooji Fukuyama, Yutaka Ohmoto, Katsuya Watanabe
  • Patent number: 7011762
    Abstract: One aspect of the present invention relates to a wafer containing a semiconductor substrate, at least one metal layer formed over the semiconductor substrate, and at least one electrical sensor embedded at least one of on and in the wafer to facilitate real time monitoring of the metal layer as it progresses through a subtractive metallization process. Another aspect of the present relates to a system and method for monitoring a subtractive metallization process in real time in order to effectuate an immediate response in the on-going process. The system contains a wafer comprising at least one metal layer formed on a semiconductor substrate, at least one electrical sensor in contact with the wafer and operable to detect and transmit electrical activity associated with the wafer, and an electrical measurement station operable to process electrical activity detected and received from the electrical sensor for monitoring a subtractive metallization process in real-time.
    Type: Grant
    Filed: April 21, 2003
    Date of Patent: March 14, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Christopher F. Lyons, Ramkumar Subramanian, Steven C. Avanzino
  • Patent number: 7005305
    Abstract: A technique is provided that may be used to improve optical endpoint detection in a plasma etch process. A semiconductor structure is manufactured that includes at least one electrical device. The technique is adapted for forming a signal layer on or in a wafer, wherein the signal layer comprises a chemical element that causes a characteristic optical emission when coming into contact with an etch plasma. The chemical element does not have a primary influence on the electrical properties of the electrical device. The signal layer is for use in a plasma etch process to detect a plasma etch endpoint if the characteristic optical emission is detected. The signal layer may be patterned and may be incorporated into a stop layer.
    Type: Grant
    Filed: May 29, 2003
    Date of Patent: February 28, 2006
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gunter Grasshoff, Christoph Schwan, Matthias Schaller
  • Patent number: 7001530
    Abstract: A method for detecting the end point of plasma etching process by using matrix comprises a step of detecting a beginning matrix including emitting intensities and/or other plasma parameters of at least two different plasma species during beginning etching process. Then, a step of detecting an etching matrix is performed in which the etching matrix includes emitting intensities and/or other plasma parameters of the at least two different plasma species at the etching reaction. An end point matrix is then computed by using the beginning as well as etching matrices and compared to a reference end point matrix to decide whether the end point is reached.
    Type: Grant
    Filed: September 9, 2003
    Date of Patent: February 21, 2006
    Assignee: Winbond Electronics Corp.
    Inventor: Szetsen Steven Lee
  • Patent number: 7001529
    Abstract: A method for controlling a photoresist etch step in a plasma processing chamber is disclosed. The photoresist etch step being configured to etch back a photoresist layer deposited on a substrate surface to a thinner photoresist layer having predefined photoresist thickness. The method includes etching the photoresist layer using a plasma etch process and detecting interference patterns coming from the photoresist layer. The method further includes terminating the photoresist etch step when an analysis of the interference patterns indicates that the predefined photoresist thickness is achieved, whereby the predefined photoresist thickness is greater than zero.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: February 21, 2006
    Assignee: Lam Research Corporation
    Inventors: Taejoon Han, Xiaoqiang Yao
  • Patent number: 6982042
    Abstract: A method for reducing noise in a lapping guide. Selected portions of a Giant magnetoresistive device wafer are masked, thereby defining masked and unmasked regions of the wafer in which the unmasked regions include lapping guides. The wafer is bombarded with ions such that a Giant magnetoresistive effect of the unmasked regions is reduced.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: January 3, 2006
    Assignee: Hitachi Global Storage Technologies Netherlands, B.V.
    Inventors: Mark A. Church, Wipul Pemsiri Jayasekara, Howard Gordon Zolla
  • Patent number: 6979408
    Abstract: The invention provides methods and apparatuses for controlling critical dimension (CD) uniformity of a photomask by neutralizing CD variation associated with pattern density and process fluctuation.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: December 27, 2005
    Assignees: Intel Corporation, Dai Nippon Printing Co., Ltd.
    Inventors: Yoshihiro Tezuka, Toshifumi Yokoyama, Tsukasa Abe
  • Patent number: 6967109
    Abstract: A method and apparatus for measuring a potential difference for plasma processing with a plasma processing apparatus that processes a sample by introducing a gas into a vacuum chamber and generates plasma. A light-emitting portion is formed on a measurement-use sample of the sample to be processed and a current flows into the light-emitting portion according to a potential difference that has been generated across the light-emitting portion. An intensity of light emitted from the light-emitting portion according to a predetermined light intensity is measured and a potential difference on the measurement-use sample according to a predetermined light intensity is measured.
    Type: Grant
    Filed: July 1, 2004
    Date of Patent: November 22, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tatehito Usui, Tetsuo Ono, Ryoji Nishio, Kazue Takahashi, Nobuyuki Mise
  • Patent number: 6962664
    Abstract: An electrode assembly (50) and an associated plasma reactor system (10) and related methods for a variety of plasma processing applications. The electrode assembly provides control of a plasma density profile (202) within an interior region (30) of a plasma reactor chamber (20). The electrode assembly includes an upper electrode (54) having a lower surface (54L), an upper surface (54U) and an outer edge (54E). The lower surface of the upper electrode faces interior region of the plasma chamber housing the plasma (200), and thus interfaces with the plasma. The electrode assembly further includes a segmented electrode (60) arranged proximate to and preferably substantially parallel with the upper surface of the upper electrode. The segmented electrode comprises two or more separated electrode segments (62a, 62b, . . . 62n), each having an upper and lower surface. Each electrode segment is spaced apart from the upper electrode upper surface by a corresponding controlled gap (Ga, Gb, . . . Gn).
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: November 8, 2005
    Assignee: Tokyo Electron Limited
    Inventor: Andrej S. Mitrovic
  • Patent number: 6958476
    Abstract: Methods for creating a cross section of at least one feature located on a substrate are disclosed. The methods include coating the feature with a layer of contrast enhancing material, recoating the feature with a second material that is different from the contrast enhancing material, and milling the feature. The second material has substantially similar milling characteristics as the feature. The methods may further include creating an image of the feature and saving the image of the feature.
    Type: Grant
    Filed: October 10, 2003
    Date of Patent: October 25, 2005
    Assignee: ASML Netherlands B.V.
    Inventors: Todd J. Davis, Theodore Allen Paxton
  • Patent number: 6952014
    Abstract: A Focused Ion Beam (FIB) milling end-point detection system uses a constant current power supply to energize an Integrated Circuit (IC) that is to be modified. The FIB is cycled over a conductive trace that is to be accessed during the milling process. The input power, or voltage to the IC is monitored during the milling process. The end-point can be detected when the FIB reaches the conductive trace. The FIB can inject charge onto the conductive trace when the FIB reaches the level of the conductive trace. An active device coupled to the conductive trace can amplify the charge injected by the FIB. The active device can operate as a current amplifier. The change in IC current can result in an amplified change in device input voltage. The end-point can be detected by monitoring the change in input voltage from the constant current power supply.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: October 4, 2005
    Assignee: Qualcomm Inc
    Inventor: Alan Glen Street
  • Patent number: 6949203
    Abstract: An integrated in situ etch process performed in a multichamber substrate processing system having first and second etching chambers. In one embodiment the first chamber includes an interior surface that has been roughened to at least 100 Ra and the second chamber includes an interior surface that has a roughness of less than about 32 Ra. The process includes transferring a substrate having formed thereon in a downward direction a patterned photoresist mask, a dielectric layer, a barrier layer and a feature in the substrate to be contacted into the first chamber where the dielectric layer is etched in a process that encourages polymer formation over the roughened interior surface of the chamber. The substrate is then transferred from the first chamber to the second chamber under vacuum conditions and, in the second chamber, is exposed to a reactive plasma such as oxygen to strip away the photoresist mask deposited over the substrate.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: September 27, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Chang-Lin Hsieh, Diana Xiaobing Ma, Brian Sy Yuan Shieh, Gerald Zheyao Yin, Jennifer Sun, Senh Thach, Lee Luo, Claes H. Bjorkman
  • Patent number: 6942811
    Abstract: The etching of a sacrificial silicon portion in a microstructure such as a microelectromechanical structure by the use of etchant gases that are noble gas fluorides or halogen fluorides is performed with greater selectivity toward the silicon portion relative to other portions of the microstructure by slowing the etch rate. The etch rate is preferably 30 um/hr or less, and can be 3 um/hr or even less. The selectivity is also improved by the addition of non-etchant gaseous additives to the etchant gas. Preferably the non-etchant gaseous additives that have a molar-averaged formula weight that is below that of molecular nitrogen offer significant advantages over gaseous additives of higher formula weights by causing completion of the etch in a shorter period of time while still achieving the same improvement in selectivity. The etch process is also enhanced by the ability to accurately determine the end point of the removal step.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: September 13, 2005
    Assignee: Reflectivity, Inc
    Inventors: Satyadev R. Patel, Gregory P. Schaadt, Douglas B. MacDonald, Hongqin Shi
  • Patent number: 6939472
    Abstract: The present invention teaches a method and apparatus for removing sacrificial materials in fabrications of microstructures using one or more selected spontaneous vapor phase etchants. The selected etchant is fed into an etch chamber containing the microstructure during each feeding cycle of a sequence of feeding cycles until the sacrificial material of the microstructure is exhausted through the chemical reaction between the etchant and the sacrificial material. Specifically, during a first feeding cycle, a first amount of selected spontaneous vapor phase etchant is fed into the etch chamber. At a second feeding cycle, a second amount of the etchant is fed into the etch chamber. The first amount and the second amount of the selected etchant may or may not be the same. The time duration of the feeding cycles are individually adjustable.
    Type: Grant
    Filed: September 17, 2003
    Date of Patent: September 6, 2005
    Assignee: Reflectivity, Inc.
    Inventors: Gregory P. Schaadt, Hongqin Shi
  • Patent number: 6939476
    Abstract: The present invention predicts Critical Dimension (CD) before processing a wafer lot and alters the etch by adjusting recipe inputs to control the current lots bias to target critical dimensions. Also, the process incorporates the use of etch chamber selection by an automated system, disallowing processing of a lot if critical dimensions are predicted to be out of control. Line caper, the angle of sidewall on the metal line, and oxide loss, the amount of oxide removed by the over etch portion of the process, are also used to monitor current tool performance and make adjustments to recipe inputs.
    Type: Grant
    Filed: November 20, 2002
    Date of Patent: September 6, 2005
    Assignee: National Semiconductor Corporation
    Inventor: Justin Griffin
  • Patent number: 6911157
    Abstract: At least one control parameter such as power supplied to a plasma, process pressure, gas flow rate, and radio frequency bias power to a wafer is changed for an extremely short time as compared with an entire plasma processing time, to the extent that such a change does not affect the result of plasma processing on the wafer, to monitor a temporal change of a plasma state which occurs at the time of changing. A signal resulting from the monitoring method is used to control or diagnose the plasma processing, thereby making it possible to accomplish miniature etching works, high quality deposition, surface processing.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: June 28, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Manabu Edamura, Hideyuki Yamamoto, Kazuyuki Ikenaga
  • Patent number: 6905623
    Abstract: A system and method for determining precisely in-situ the endpoint of halogen-assisted charged particle beam milling of a hole or trench in the backside of the substrate of a flipchip packaged IC. The backside of the IC is mechanically thinned. Optionally, a coarse trench is then milled in the thinned backside of the IC using either laser chemical etching or halogen-assisted charged particle beam milling. A further small trench is milled using a halogen-assisted charged-particle beam (electron or ion beam). The endpoint for milling this small trench is determined precisely by monitoring the power supply leakage current of the IC induced by electron-hole pairs created by the milling process. A precise in-situ endpoint detection signal is generated by modulating the beam at a reference frequency and then amplifying that frequency component in the power supply leakage current with an amplifier, narrow-band amplifier or lock-in amplifier.
    Type: Grant
    Filed: November 6, 2002
    Date of Patent: June 14, 2005
    Assignee: Credence Systems Corporation
    Inventors: Theodore R. Lundquist, Kenneth R. Wilsher
  • Patent number: 6881352
    Abstract: A plasma processing control system and method which can suppress influences caused by disturbances. The control system includes a plasma processor for performing processing operation over a sample accommodated within a vacuum processing chamber, a sensor for monitoring process parameters during processing operation of the plasma processor, a processed-result estimation model for estimating a processed result on the basis of a monitored output of the sensor and a preset processed-result prediction equation, and an optimum recipe calculation model for calculating correction values of processing conditions on the basis of an estimated result of the processed-result estimation model in such a manner that the processed result becomes a target value. The plasma processor is controlled on the basis of a recipe generated by the optimum recipe calculation model.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: April 19, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Akira Kagoshima, Hideyuki Yamamoto, Shoji Ikuhara, Toshio Masuda, Hiroyuki Kitsunai, Junichi Tanaka, Natsuyo Morioka, Kenji Tamaki
  • Patent number: 6864041
    Abstract: A method of fabricating an electronic chip on a wafer in which a first mask at a predetermined lower resolution is developed on the wafer and then etched under a first set of conditions for a predetermined period to achieve a mask that is below the resolution limit of current lithography. The etched mask is then used as a hard mask for etching material on a lower layer.
    Type: Grant
    Filed: May 2, 2001
    Date of Patent: March 8, 2005
    Assignee: International Business Machines Corporation
    Inventors: Jeffrey J. Brown, Sadanand Vinayak Deshpande, David V. Horak, Maheswaran Surendra, Len Y. Tsou, Qingyun Yang, Chienfan Yu, Ying Zhang