Irradiating, Ion Implanting, Alloying, Diffusing, Or Chemically Reacting The Substrate Prior To Etching To Change Properties Of Substrate Toward The Etchant Patents (Class 216/62)
  • Patent number: 8615868
    Abstract: A method for manufacturing a magnetic sensor that includes depositing a plurality of mask layers, then forming a stripe height defining mask over the sensor layers. A first ion milling is performed just sufficiently to remove portions of the free layer that are not protected by the stripe height defining mask, the first ion milling being terminated at the non-magnetic barrier or spacer layer. A dielectric layer is then deposited, preferably by ion beam deposition. A second ion milling is then performed to remove portions of the pinned layer structure that are not protected by the mask, the free layer being protected during the second ion milling by the dielectric layer.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: December 31, 2013
    Assignee: HGST Netherlands B.V.
    Inventors: Yongchul Ahn, Xiaozhong Dang, Quang Le, Simon H. Liao
  • Patent number: 8617408
    Abstract: A method for manufacturing a magnetic read sensor at very narrow track widths. The method uses an amorphous carbon mask layer to pattern the sensor by ion milling, rather than a mask constructed of a material such as photoresist or DURIMIDE® which can bend over during ion milling at very narrow track widths. By using the amorphous carbon layer as the masking layer, the trackwidth can be very small, while avoiding this bending over of the mask that has been experienced with prior art methods. In addition, the track-width can be further reduced by using a reactive ion etching to further reduce the width of the amorphous carbon mask prior to patterning the sensor. The method also allows extraneous portions of the side insulation layer and hard bias layer to be removed above the sensor by a light CMP process.
    Type: Grant
    Filed: October 18, 2011
    Date of Patent: December 31, 2013
    Assignee: HGST Netherlands B.V.
    Inventors: Hamid Balamane, Patrick M. Braganca, Jordan A. Katine, Jui-Lung Li, Yang Li, Kanaiyalal C. Patel, Neil L. Robertson, Samuel W. Yuan
  • Patent number: 8617411
    Abstract: Substrate processing systems and methods for etching an atomic layer are disclosed. The methods and systems are configured to introducing a first gas into the chamber, the gas being an etchant gas suitable for etching the layer and allowing the first gas to be present in the chamber for a period of time sufficient to cause adsorption of at least some of the first gas into the layer. The first gas is substantially replaced in the chamber with an inert gas, and metastables are then generated from the inert gas to etch the layer with the metastables while substantially preventing the plasma charged species from etching the layer.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: December 31, 2013
    Assignee: Lam Research Corporation
    Inventor: Harmeet Singh
  • Patent number: 8607439
    Abstract: A method and system for providing an energy assisted magnetic recording (EAMR) head are described. The method and system include providing a slider, an EAMR transducer coupled with the slider, and a top layer on the slider. The top layer includes a mirror well therein and has a substantially flat top surface. The method and system further includes providing a laser including a light-emitting surface and providing a mirror optically coupled with the laser. The laser is coupled to the top surface of the top layer external to the mirror well. The mirror has a bottom surface and a reflective surface facing the light-emitting surface of the laser. A portion of the bottom surface of the mirror is affixed to the top surface of the top layer. A portion of the mirror resides in the mirror well.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: December 17, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Lei Wang, Dujiang Wan
  • Patent number: 8603920
    Abstract: A manufacturing method of a semiconductor device includes: irradiating a laser beam on a single crystal silicon substrate, and scanning the laser beam on the substrate so that a portion of the substrate is poly crystallized, wherein at least a part of a poly crystallized portion of the substrate is exposed on a surface of the substrate; and etching the poly crystallized portion of the substrate with an etchant. In this case, a process time is improved.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: December 10, 2013
    Assignee: DENSO CORPORATION
    Inventors: Katsuhiko Kanamori, Masashi Totokawa, Hiroshi Tanaka
  • Patent number: 8603351
    Abstract: An object to be processed is reliably cut along a line to cut. An object to be processed is irradiated with laser light while locating a converging point at the object, so as to form a modified region in the object along a line to cut. The object formed with the modified region is subjected to an etching process utilizing an etching liquid exhibiting a higher etching rate for the modified region than for an unmodified region, so as to etch the modified region. This can etch the object selectively and rapidly along the line to cut by utilizing a higher etching rate in the modified region.
    Type: Grant
    Filed: May 23, 2008
    Date of Patent: December 10, 2013
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Takeshi Sakamoto, Hideki Shimoi, Naoki Uchiyama
  • Patent number: 8597530
    Abstract: A method of forming a semiconductor device comprises forming a mask pattern over an etch target layer, forming an ion implantation region in the mask pattern through an ion implantation process, and forming an ion non-implantation region within the mask pattern, removing the ion implantation region on a top surface of the ion non-implantation region, removing the ion non-implantation region, and patterning the etch target layer by using spacers that comprise the ion implantation region as an etch mask.
    Type: Grant
    Filed: November 2, 2010
    Date of Patent: December 3, 2013
    Assignee: SK hynix Inc.
    Inventor: Min Sub Lee
  • Patent number: 8580130
    Abstract: Laser-assisted apparatus and methods for performing nanoscale material processing, including nanodeposition of materials, can be controlled very precisely to yield both simple and complex structures with sizes less than 100 nm. Optical or thermal energy in the near field of a photon (laser) pulse is used to fabricate submicron and nanometer structures on a substrate. A wide variety of laser material processing techniques can be adapted for use including, subtractive (e.g., ablation, machining or chemical etching), additive (e.g., chemical vapor deposition, selective self-assembly), and modification (e.g., phase transformation, doping) processes. Additionally, the apparatus can be integrated into imaging instruments, such as SEM and TEM, to allow for real-time imaging of the material processing.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: November 12, 2013
    Assignee: The Regents of the University of California
    Inventors: Samuel S. Mao, Costas P. Grigoropoulos, David J. Hwang, Andrew M. Minor
  • Patent number: 8567041
    Abstract: A heated resonator includes a base substrate, a piezoelectric piece having a thickness and a top side and a bottom side, a first electrode on the top side, a second electrode opposite the first electrode on the bottom side, an anchor connected between the piezoelectric piece and the base substrate, and a heater on the piezoelectric material. A thermal resistor region in the piezoelectric piece is between the heater and the anchor.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: October 29, 2013
    Assignee: HRL Laboratories, LLC
    Inventor: Christopher S. Roper
  • Patent number: 8568605
    Abstract: A method for forming nanometer-sized patterns and pores in a membrane is described. The method comprises incorporating a reactive material onto the membrane, the reactive material being a material capable of lowering an amount of energy required for forming a pore and/or pattern by irradiating the membrane material with an electron beam, thus leading to a faster pore and/or pattern formation.
    Type: Grant
    Filed: November 17, 2011
    Date of Patent: October 29, 2013
    Assignee: California Institute of Technology
    Inventors: Sameer Walavalkar, Axel Scherer, Andrew P. Homyk
  • Patent number: 8557613
    Abstract: A method for designing, fabricating, and predicting a desired structure in and/or on a host material through defining etch masks and etching the host material is provided. The desired structure can be micro- or nanoscale structures, such as suspended nanowires and corresponding supporting pillars, and can be defined one layer at a time. Arbitrary desired structures can also be defined and obtained through etching. Further, given the desired structure, a starting structure can be predicted where etching of the starting structure yields the desired structure.
    Type: Grant
    Filed: June 13, 2011
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Michael Shearn, Michael David Henry, Axel Scherer
  • Patent number: 8557612
    Abstract: A method to determine minimum etch mask dosage or thickness as a function of etch depth or maximum etch depth as a function of etch mask implantation dosage or thickness, for fabricating structures in or on a substrate through etch masking via addition or removal of a masking material and subsequent etching.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: October 15, 2013
    Assignee: California Institute of Technology
    Inventors: Michael David Henry, Michael Shearn, Axel Scherer
  • Patent number: 8557698
    Abstract: A method for producing a micromechanical and/or nanomechanical device includes partial etching of at least one sacrificial layer arranged between a first layer and a substrate, forming at least one cavity in which is arranged at least one portion of the sacrificial layer in contact with the first layer and/or the substrate. The method also includes chemical transformation of at least one wall of the first layer and/or the substrate in the cavity, delimiting at least one stop in the first layer and/or the substrate at the level of the portion of the sacrificial layer. The portion of the sacrificial layer and the chemically transformed wall of the first layer and/or the substrate is also eliminated.
    Type: Grant
    Filed: December 16, 2008
    Date of Patent: October 15, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Stéphane Caplet
  • Publication number: 20130256267
    Abstract: A substrate processing method includes a water removing step of removing water from a substrate, a silylating step of supplying a silylating agent to the substrate after the water removing step, and an etching step of supplying an etching agent to the substrate after the silylating step. The substrate may have a surface on which a nitride film and an oxide film are exposed and in this case, the etching step may be a selective etching step of selectively etching the nitride film by the etching agent. The etching agent may be supplied in a form of a vapor having an etching component.
    Type: Application
    Filed: November 28, 2012
    Publication date: October 3, 2013
    Applicant: DAINIPPON SCREEN MFG. CO., LTD.
    Inventors: Takashi OTA, Yuya AKANISHI, Akio HASHIZUME
  • Patent number: 8545710
    Abstract: An ion radiation damage prediction method includes a parameter computation step of computing the collision position and the incidence angle of an incident ion hitting a fabricated object by considering a transport path of the ion and by adopting the Monte Carlo method which takes distributions of flux quantities, incidence energies and angles of incident ions as input parameters; and a defect-distribution computation step of searching for data by referring to information found at the parameter computation step and databases created in advance, the databases storing distributions of quantities of crystalline defects having an effect on the fabricated object, ion reflection probabilities and ion penetration depths, finding the penetration depth and location of the incident ion based on the data found in the search operation, and the incidence energy and angle of the incident ion, and computing a distribution of defects in the fabricated object from the penetration depth and location.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 1, 2013
    Assignee: Sony Corporation
    Inventors: Nobuyuki Kuboi, Shoji Kobayashi
  • Publication number: 20130248489
    Abstract: A microstructure manufacturing method includes (a) generating first light including an interference fringe by crossing two laser beams, (b) forming a denatured region and a non-denatured region on an object having thermal non-linearity by applying the first light onto the object, so that the denatured region and the non-denatured region are disposed so as to correspond to a period of the interference fringe of the first light, and (c) etching the object so that the denatured region or the non-denatured region is selectively eliminated.
    Type: Application
    Filed: February 19, 2008
    Publication date: September 26, 2013
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Jun AMAKO
  • Patent number: 8540852
    Abstract: Disclosed are method and apparatus for manufacturing a magnetoresistive device which are suitable for manufacturing a high-quality magnetoresistive device by reducing damages caused during the processing of a multilayer magnetic film as a component of the magnetoresistive device, thereby preventing deterioration of magnetic characteristics due to such damages. Specifically disclosed is a method for manufacturing a magnetoresistive device, which includes processing a multilayer magnetic film by performing a reactive ion etching on a substrate which is provided with the multilayer magnetic film as a component of the magnetoresistive device. This method for manufacturing a magnetoresistive device includes irradiating the multilayer magnetic film with an ion beam after the reactive ion etching.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: September 24, 2013
    Assignee: Canon Anelva Corporation
    Inventors: Naoki Watanabe, Yoshimitsu Kodaira, David D. Djayaprawira, Hiroki Maehara
  • Patent number: 8541313
    Abstract: A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species.
    Type: Grant
    Filed: October 25, 2006
    Date of Patent: September 24, 2013
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Stéphan Borel, Jeremy Bilde
  • Patent number: 8529782
    Abstract: A microstructure manufacturing method includes (a) generating first light including an interference fringe by crossing two laser beams, (b) forming a denatured region and a non-denatured region on an object having thermal non-linearity by applying the first light onto the object, so that the denatured region and the non-denatured region are disposed so as to correspond to a period of the interference fringe of the first light, and (c) etching the object so that the denatured region or the non-denatured region is selectively eliminated.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: September 10, 2013
    Assignee: Seiko Epson Corporation
    Inventor: Jun Amako
  • Patent number: 8524100
    Abstract: The invention provides a system and process of patterning structures on a carbon based surface comprising exposing part of the surface to an ion flux, such that material properties of the exposed surface are modified to provide a hard mask effect on the surface. A further step of etching unexposed parts of the surface forms the structures on the surface. The inventors have discovered that by controlling the ion exposure, alteration of the surface structure at the top surface provides a mask pattern, without substantially removing any material from the exposed surface. The mask allows for subsequent ion etching of unexposed areas of the surface leaving the exposed areas raised relative to the unexposed areas thus manufacturing patterns onto the surface. For example, a Ga+ focussed ion beam exposes a pattern onto a diamond surface which produces such a pattern after its exposure to a plasma etch.
    Type: Grant
    Filed: July 3, 2009
    Date of Patent: September 3, 2013
    Assignee: The Provost Fellows and Scholars of the College of the Holy and Undivided Trinity of Queen Elizabeth, near Dublin
    Inventors: Graham L. W. Cross, Warren McKenzie, John B. Pethica
  • Patent number: 8505190
    Abstract: Disclosed herein is a method of manufacturing an inertial sensor. The method of manufacturing an inertial sensor 100 includes (A) applying a polymer 120 to a base substrate 110, (B) patterning the polymer 120 so as to form an opening part 125 in the polymer 120, (C) completing a cap 130 by forming a cavity 115 on the base substrate 110 exposed fro the opening part 125 through an etching process in a thickness direction, and (D) bonding the cap 130 to a device substrate 140 by using a polymer 120, whereby the polymer 120 is applied to the base substrate 110 in a constant thickness D3, such that the cap 130 may be easily bonded to the device substrate 140 by using the polymer 120.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: August 13, 2013
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hyun Kee Lee, Tae Joon Park, Sang Kee Yoon, Hyung Jae Park, Yeong Gyu Lee, Heung Woo Park
  • Patent number: 8480911
    Abstract: A read sensor for a read transducer is fabricated. The read transducer has field and device regions. A read sensor stack is deposited. A mask covering part of the stack corresponding to the read sensor is provided. The read sensor having inboard and outboard junction angles is defined from the stack in a track width direction. A critical junction (CJ) focused ion beam scan (FIBS) polishing that removes part of the read sensor based on the junction angles is performed. A hard bias structure is deposited and the transducer planarized. A remaining portion of the mask is removed. A stripe height mask covering part of the read sensor and hard bias structure in a stripe height direction is provided. The read sensor stripe height is defined. A tunneling magnetoresistance (TMR) FIBS polishing that removes part of the stack in the field region is performed. An insulating layer is provided.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: July 9, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Masahiro Osugi, Guanghong Luo, Lily Yao, Ming Jiang
  • Patent number: 8481427
    Abstract: A micromechanical method for manufacturing a cavity in a substrate, and a micromechanical component manufactured with this method. In this method, in a first step a first layer is produced on or in a substrate. At least one second layer is then applied onto the first layer. An access hole is produced in this second layer. Material of the first layer and of the substrate can be dissolved out through this hole, so that a cavity is produced in the substrate beneath at least a portion of the second layer. This second layer above the cavity can subsequently be used as a membrane. In addition, the possibility also exists of depositing further layers onto the second layer, only the totality of which layers constitutes the membrane. The material of the first layer is selected so that dissolving out the material of the first layer produces a transition edge in the first layer, which edge at is at a predefinable angle between the substrate and the second layer.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: July 9, 2013
    Assignee: Robert Bosch GmbH
    Inventors: Hans Artmann, Andrea Urban, Arnim Hoechst
  • Patent number: 8481246
    Abstract: According to one embodiment, a method of forming a pattern includes applying a block copolymer to a substrate, the block copolymer including a first block and a second block, the first block including polyacrylate or polymethacrylate having a side chain to which an alicyclic hydrocarbon group or a hydrocarbon group including a tertiary carbon is introduced, and the second block including polystyrene substituted with hydrocarbon or halogen at an ?-position, causing the block copolymer to be phase-separated, irradiating the block copolymer with an energy beam to decompose the second block, and removing the second block with a developer to form a pattern of the first block.
    Type: Grant
    Filed: March 26, 2012
    Date of Patent: July 9, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Asakawa, Shigeki Hattori, Ryota Kitagawa
  • Patent number: 8474127
    Abstract: A method for enhancing thermal stability, improving biasing and reducing damage from electrical surges in self-pinned abutted junction heads. The method includes forming a free layer, forming first hard bias layers abutting the free layer and forming second hard bias layers over the first hard bias layers discontiguous from the free layer, the second hard bias layers being anti-parallel to the first hard bias layers, the first and second hard bias layers providing a net longitudinal bias on the free layer.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: July 2, 2013
    Assignee: HGST Netherlands B.V.
    Inventors: Hardayal Singh Gill, Wen-Chien Hsiao, Jih-Shiuan Luo
  • Patent number: 8470190
    Abstract: A method for processing at least one wall of an opening formed in a silicon substrate, successively including the steps of implanting fluorine atoms into an upper portion of the wall of the opening, performing an oxidization step, and applying a specific processing to at least a portion of the non-implanted portion of the opening.
    Type: Grant
    Filed: July 16, 2008
    Date of Patent: June 25, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Edgard Jeanne, Sylvain Nizou
  • Patent number: 8468682
    Abstract: A method for providing a perpendicular magnetic recording transducer is described. The method and system include providing a metallic underlayer and providing an insulator, at least a portion of which is on the metallic underlayer. The method and system also include forming a trench in the insulator. The bottom of the trench is narrower than the top of the trench and includes a portion of the metallic underlayer. The method and system also include providing a nonmagnetic seed layer that substantially covers at least the bottom and sides of the trench. The method and system also include plating a perpendicular magnetic pole material on at least a portion of the seed layer and removing a portion of the perpendicular magnetic pole material. A remaining portion of the perpendicular magnetic pole material forms a perpendicular magnetic recording pole.
    Type: Grant
    Filed: March 6, 2012
    Date of Patent: June 25, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventor: Lei Larry Zhang
  • Patent number: 8460569
    Abstract: A method of patterning a substrate, comprises providing a set of patterned features on the substrate, exposing the set of patterned features to a dose of ions incident on the substrate over multiple angles, and selectively etching exposed portions of the patterned features.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: June 11, 2013
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Christopher R. Hatem, Patrick M. Martin, Timothy J. Miller
  • Patent number: 8453316
    Abstract: A method of forming a magnetic head comprises the steps of: selectively exposing through the use of a photomask a photoresist layer unpatterned; forming a pattern for forming a pole layer by developing the photoresist layer after the exposure; and forming the pole layer through the use of the pattern. The photomask includes first to third regions. The first region has such a perimeter that a projection image thereof is shaped along a perimeter of an ideal shape of the top surface of the pole layer. The second region touches the perimeter of the first region, and is located outside the first region. The third region is located inside the first region without touching the perimeter of the first region. The third region suppresses deviation of the pole layer from its desired shape which may be caused by the effect of light reflected while the photoresist layer is exposed.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: June 4, 2013
    Assignee: Headway Technologies, Inc.
    Inventors: Yoshitaka Sasaki, Kazuo Ishizaki, Hiroyuki Itoh
  • Patent number: 8443511
    Abstract: A scalable MEMS inductor is formed on the top surface of a semiconductor die. The MEMS inductor includes a plurality of magnetic lower laminations, a circular trace that lies over and spaced apart from the magnetic lower laminations, and a plurality of upper laminations that lie over and spaced apart from the circular trace.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: May 21, 2013
    Assignee: National Semiconductor Corporation
    Inventors: Peter Smeys, Peter Johnson
  • Patent number: 8438710
    Abstract: A structure with an integrated circuit (IC) and a silicon condenser microphone mounted thereon includes a substrate having a first area and a second area. The IC is fabricated on the first area in order to form a conducting layer and an insulation layer. Both the conducting layer and the insulation layer further extend to the second area. The insulation layer is removed under low temperature in order to expose the conducting layer on which the silicon condenser microphone is fabricated. The silicon condenser microphone includes a first film layer, a connecting layer and a second film layer under a condition that the connecting layer connects the first and the second film layers. The first film layer and the second film layer act as two electrodes of a variable capacitance.
    Type: Grant
    Filed: August 11, 2009
    Date of Patent: May 14, 2013
    Inventor: Gang Li
  • Patent number: 8424192
    Abstract: A method and system for manufacturing a pole on a recording head is disclosed. The method and system include sputtering at least one ferromagnetic layer and fabricating a hard mask on the ferromagnetic layer. The method and system also include defining the pole and depositing a write gap on the pole. A portion of the pole is encapsulated in an insulator.
    Type: Grant
    Filed: August 8, 2005
    Date of Patent: April 23, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Danning Yang, Lei Wang, Yingjian Chen, Brant Nease, Kyusik Sin
  • Patent number: 8420547
    Abstract: A plasma processing method performed in a plasma processing apparatus including a processing chamber accommodating a substrate in which a plasma is generated; a mounting table mounting the substrate, which is provided in the processing chamber and to which a plasma attraction high frequency voltage is applied; and a facing electrode provided to face the mounting table in the processing chamber, to which a negative DC voltage is applied, the method including: applying a plasma attraction high frequency voltage to the mounting table for a predetermined period of time; and stopping the application of the plasma attraction high frequency voltage to the mounting table. In the plasma processing method, the application of the plasma attraction high frequency voltage and stopping thereof are alternately repeated.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: April 16, 2013
    Assignee: Tokyo Electron Limited
    Inventor: Yoshinobu Ooya
  • Patent number: 8419952
    Abstract: According to one embodiment, a method of manufacturing a patterned medium includes forming an implantation depth-adjusting layer above a magnetic recording layer, the magnetic recording layer being made of a material that is deactivated when implanted with a chemical species, and the implantation depth-adjusting layer being made of a material that is etched when irradiated with an ion beam of the chemical species and irradiating the implantation depth-adjusting layer with the ion beam to implant the chemical species into a part of the magnetic recording layer through the implantation depth-adjusting layer while etching the implantation depth-adjusting layer by an action of the ion beam to decrease a thickness of the implantation depth-adjusting layer.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: April 16, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masatoshi Sakurai, Kaori Kimura, Hiroyuki Hyodo, Takeshi Iwasaki
  • Patent number: 8420704
    Abstract: A process for preparing a polymer composite that includes reacting (a) a multi-functional monomer and (b) a block copolymer comprising (i) a first block and (ii) a second block that includes a functional group capable of reacting with the multi-functional monomer, to form a crosslinked, nano-structured, bi-continuous composite. The composite includes a continuous matrix phase and a second continuous phase comprising the first block of the block copolymer.
    Type: Grant
    Filed: July 18, 2008
    Date of Patent: April 16, 2013
    Assignee: Regents of the University of Minnesota
    Inventors: Marc Hillmyer, Liang Chen
  • Publication number: 20130087530
    Abstract: A method to fabricate a hierarchical graduated-branched structure that grows in a three-dimensional pattern down to fractal-branching, nano-size level is detailed. The fractal patterning is accomplished on a three-dimensional (i.e., non-planar) surface, by exposing the surface to a properly focused particle beam, which causes the spontaneous growth of graduated branches all over the surface. The structure can be fabricated with a single material and the fractal-patterning is done in a one step process. No addition of material is required for the formation of each branch. The fractal graduated branching structure can then be molded in order to produce replicas.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 11, 2013
    Inventors: Ranjana Sahai, Paolo Corradi
  • Patent number: 8409452
    Abstract: A through-hole forming method includes steps of forming a first impurity region (102a) around a region where a through-hole is to be formed in the first surface of a silicon substrate (101), the first impurity region (102) being higher in impurity concentration than the silicon substrate (101), forming a second impurity region (102b) at a position adjacent to the first impurity region (102a) in the depth direction of the silicon substrate (101), the second impurity region (102b) being higher in impurity concentration than the first impurity region (102a), forming an etch stop layer (103) on the first surface, forming an etch mask layer (104) having an opening on the second surface of the silicon substrate (101) opposite to the first surface, and etching the silicon substrate (101) until at least the etch stop layer (103) is exposed via the opening.
    Type: Grant
    Filed: August 25, 2008
    Date of Patent: April 2, 2013
    Assignee: Canon Kabushiki Kaisha
    Inventors: Keiichi Sasaki, Yukihiro Hayakawa
  • Patent number: 8402635
    Abstract: A method of manufacturing a magnetic head, including a magneto resistance effect (MR) element that reads a magnetic recording medium, is disclosed. A multilayer film is formed on a shield layer. Unnecessary portions of the multilayer film are removed from both sides of the MR element in a first direction orthogonal to a lamination direction of the multilayer film and parallel to the MR element surface facing the magnetic recording medium. An insulating layer is formed on a surface exposed by removal of the unnecessary portions. An integrated soft magnetic layer covering both sides of the MR element in the first direction and an upper side of the MR element is formed, thereby configuring a second shield layer. An anisotropy application layer is formed on the second shield layer, thereby providing exchange anisotropy to the soft magnetic layer, and magnetizing the soft magnetic layer in a predetermined direction.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: March 26, 2013
    Assignee: TDK Corporation
    Inventors: Naomichi Degawa, Takumi Yanagisawa, Satoshi Miura, Yoshikazu Sawada, Takahiko Machita, Kenzo Makino, Takekazu Yamane, Shohei Kawasaki
  • Patent number: 8404594
    Abstract: A semiconductor process and apparatus includes forming first and second gate electrodes (151, 161) by forming the first gate electrode (151) over a first high-k gate dielectric (121) and forming the second gate electrode (161) over at least a second high-k gate dielectric (122) different from the first gate dielectric (121). Either or both of the high-k gate dielectric layers (121, 122) may be formed by depositing and selectively etching an initial layer of high-k dielectric material (e.g., 14). As deposited, the initial layer (14) has an exposed surface (18) and an initial predetermined crystalline structure. An exposed thin surface layer (20) of the initial layer (14) is prepared for etching by modifying the initial crystalline structure in the exposed thin surface layer. The modified crystalline structure in the exposed thin surface layer may be removed by applying a selective etch, such as HF or HCl.
    Type: Grant
    Filed: May 27, 2005
    Date of Patent: March 26, 2013
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Dina H. Triyoso, Olubunmi O. Adetutu
  • Patent number: 8381392
    Abstract: A method, including depositing a layer of material onto a base portion of a wafer, is disclosed. The layer of material has a first surface adjacent the base portion. The method also includes depositing a pattern of masking material onto a portion of a second surface of the layer. Material from the layer of material that is unprotected by the pattern of masking material is removed from the layer of material. By removing such material a portion of the layer of material is suspended from the base portion.
    Type: Grant
    Filed: May 11, 2010
    Date of Patent: February 26, 2013
    Assignee: Seagate Technology LLC
    Inventors: Jie Zou, Kaizhong Gao
  • Patent number: 8375564
    Abstract: A method provides a pole of magnetic recording transducer. A nonmagnetic stop layer having a thickness and a top surface is provided. A depression that forms a bevel is provided in the stop layer. The bevel has a depth less than the thickness and a bevel angle with respect to a remaining portion of the top surface. The bevel angle is greater than zero and less than ninety degrees. An intermediate layer having a substantially flat top surface is provided over the stop layer. A trench is formed in the intermediate layer via a removal process. The trench has a profile corresponding to the pole. The stop layer is a stop for the removal process. The method also includes providing the pole in the trench. The pole has a leading edge bevel corresponding to the bevel in the stop layer.
    Type: Grant
    Filed: December 8, 2009
    Date of Patent: February 19, 2013
    Assignee: Western Digital (Fremont), LLC
    Inventors: Guanghong Luo, Danning Yang, Weimin Si, Dujiang Wan, Yun-Fei Li, Lijie Guan, Ming Jiang
  • Patent number: 8377322
    Abstract: To provide a pattern forming method including: providing an active species supply source to at least one of a mold structure having a plurality of concave portions in its surface, and an object to be patterned; pressing the side of the mold structure, where the concave portions are provided, against the object so as to encapsulate the active species supply source in the concave portions; and oxidatively decomposing parts of the object which are in positions corresponding to the concave portions, by irradiating the active species supply source with excitation light through one of the mold structure and the object.
    Type: Grant
    Filed: June 16, 2009
    Date of Patent: February 19, 2013
    Assignee: Fujifilm Corporation
    Inventor: Satoshi Wakamatsu
  • Patent number: 8371019
    Abstract: A method for manufacturing a magnetic write head having a write pole with a very narrow track width, straight well defined sides and a well defined trailing edge width (e.g. track-width). The method includes uses two separate chemical mechanical polishing processes that stop at separate CMP stop layers. The first CMP stop layer is deposited directly over a RIEable fill layer. A RIE mask, is formed over the fill layer and first CMP stop layer, the RIE mask having an opening. A trench then is formed in the RIEable fill layer. A second CMP stop layer is then deposited into the trench and over the RIE mask, followed by plating of a magnetic material. First and second chemical mechanical polishing processes are then performed, the first stopping at the first CMP stop and the second stopping at the second CMP stop.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: February 12, 2013
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Sue Siyang Zhang, Yi Zheng, Qiping Zhong, Honglin Zhu
  • Patent number: 8361853
    Abstract: The present disclosure provides a semiconductor structure including a nanoribbon-containing layer of alternating graphene nanoribbons separated by alternating insulating ribbons. The alternating graphene nanoribbons are parallel to a surface of an underlying substrate and, in some embodiments, might be oriented along crystallographic directions of the substrate. The alternating insulating ribbons may comprise hydrogenated graphene, i.e., graphane, fluorinated graphene, or fluorographene. The semiconductor structure mentioned above can be formed by selectively converting portions of an initial graphene layer into alternating insulating ribbons, while the non-converted portions of the initial graphene form the alternating graphene nanoribbons. Semiconductor devices such as, for example, field effect transistors, can be formed atop the semiconductor structure provided in the present disclosure.
    Type: Grant
    Filed: October 12, 2010
    Date of Patent: January 29, 2013
    Assignee: International Business Machines Corporation
    Inventors: Guy Cohen, Christos D. Dimitrakopoulos, Alfred Grill, Robert L. Wisnieff
  • Patent number: 8353098
    Abstract: A method of manufacturing a perpendicular magnetic recording head capable of easily and accurately forming a main magnetic-pole layer having a shape suitable for concentrating a magnetic flux is provided. A nonmagnetic layer having a recessed section (a first recessed section and a second recessed section) is formed, and then an additional nonmagnetic layer is formed on an inner surface of the recessed section. Then, a magnetic layer is formed in the recessed section formed with the additional nonmagnetic layer, and then the magnetic layer is cut to form an air bearing surface, so as to form the main magnetic-pole layer.
    Type: Grant
    Filed: March 12, 2010
    Date of Patent: January 15, 2013
    Assignee: SAE Magnetics (H.K.) Ltd.
    Inventors: Tetsuya Mino, Naoto Matono, Ikuhito Onodera, Kazushi Nishiyama, Michitoshi Tsuchiya, Kenji Sasaki
  • Patent number: 8333008
    Abstract: A method and system for fabricating a perpendicular magnetic recording head, and the head so formed, are described. The method includes depositing an underlayer directly on an insulating layer. The underlayer preferably includes at least one of a nonferromagnetic metal, silicon oxide, and silicon nitride. A pole layer, which has a pole removal rate, is provided on the underlayer. The method and system further include forming a perpendicular magnetic recording pole from the pole layer. The perpendicular magnetic recording pole has a top and a bottom that is narrower than the top. The process of forming the perpendicular magnetic recording pole further includes removing a portion of the pole layer such that a pole removal rate for the pole layer is less than or substantially equal to a removal rate of the underlayer during the removing step.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: December 18, 2012
    Assignee: Western Digital (Fremont), LLC
    Inventors: Kyusik Sin, Lei Wang, Yingjian Chen
  • Patent number: 8322023
    Abstract: A method for fabricating a magnetic transducer is described. The magnetic transducer includes a pole having a pole tip and a flared region. The method Includes providing a first mask layer on the pole and providing a second mask layer on the first mask layer. The first mask layer is soluble in a predetermined solution and has a first thickness. The second mask layer has a second thickness greater than the first thickness. The method also includes forming a mask from the first mask layer and the second mask layer. The step of forming the mask layer includes using the predetermined solution. The mask has a pattern that exposes a portion of the pole tip and covers a portion of the flared region. The method also includes providing a wrap-around shield on at least the pole tip.
    Type: Grant
    Filed: November 10, 2009
    Date of Patent: December 4, 2012
    Assignee: Western Digital (Fremont), LLC
    Inventors: Xianzhong Zeng, Yunhe Huang, Ling Wang, Hai Sun
  • Patent number: 8316527
    Abstract: The method provides a magnetoresistive device. The magnetoresistive device is formed from a plurality of magnetoresistive layers. The method includes providing a mask. The mask covers a first portion of the magnetoresistive element layers in at least one device area. The magnetoresistive element(s) are defined using the mask. The method includes depositing hard bias layer(s). The method also includes providing a hard bias capping structure on the hard bias layer(s). The hard bias capping structure includes a first protective layer and a planarization stop layer. The first protective layer resides between the planarization stop layer and the hard bias layer(s). The method also includes performing a planarization. The planarization stop layer is configured for the planarization.
    Type: Grant
    Filed: April 1, 2008
    Date of Patent: November 27, 2012
    Assignee: Western Digital (Fremont), LLC
    Inventors: Liubo Hong, Honglin Zhu
  • Patent number: 8318034
    Abstract: In a surface processing method for processing a surface of a member made of silicon carbide (SiC) and having a fragmental layer on a surface thereof, the surface of the member having the fragmental layer is modified into a dense layer to reduce the number of particles generated from the surface of the member when the member is applied to a plasma processing apparatus. Here, the SiC of the surface of the member is recrystallized by heating the fragmental layer.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: November 27, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Naoyuki Satoh, Nobuyuki Nagayama, Keiichi Nagakubo
  • Patent number: 8307539
    Abstract: A method for modeling devices in a wafer comprises the step of providing the wafer comprising a first plurality of devices having a track width and a first stripe height, a second plurality of devices having the track width and a second stripe height, and a third plurality of devices having the track width and a third stripe height. The method further comprises the steps of measuring resistance values for the first, second and third plurality of devices to obtain a data set correlating a stripe height and a resistance value for each of the first, second and third plurality of devices, and estimating a linear relationship between resistance and inverse stripe height for the first, second and third plurality of devices based on the data set.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: November 13, 2012
    Assignee: Western Digital (Fremont), LLC
    Inventors: Steven C. Rudy, Eric R. Mckie, Mark D. Moravec