Specific Configuration Of Electrodes To Generate The Plasma Patents (Class 216/71)
  • Patent number: 7569256
    Abstract: In a parallel flat plate type plasma CVD apparatus, plasma damage of constituent parts in a reaction chamber due to irregularity of dry cleaning in the reaction chamber is reduced and the cost is lowered. In the parallel flat plate type plasma CVD apparatus in which high frequency voltages of pulse waves having mutually inverted waveforms are applied to an upper electrode and a lower electrode, and the inversion interval of the pulse wave can be arbitrarily changed, the interior of the reaction chamber is dry cleaned.
    Type: Grant
    Filed: April 12, 2007
    Date of Patent: August 4, 2009
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mitsuhiro Ichijo
  • Publication number: 20090134121
    Abstract: There is provided a plasma processing apparatus including a plasma generating unit for generating a plasma in a processing chamber in which a set processing is performed on a substrate serving as an object to be processed. The plasma processing apparatus further includes a particle moving unit for electrostatically driving particles in a region above the substrate to be removed out of the region above the substrate in the processing chamber while the processing on the substrate is performed by using the plasma. In addition, there is provided a plasma processing method of a plasma processing apparatus including the steps of generating plasma in a processing chamber in which a set processing is performed on a substrate serving as an object to be processed; and performing the processing on the substrate by the plasma.
    Type: Application
    Filed: January 26, 2009
    Publication date: May 28, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Tsuyoshi MORIYA, Hiroyuki Nakayama
  • Patent number: 7531102
    Abstract: First radicals and second radicals are simultaneous deposited into a space defined by two adjacent lines of photoresists and an underlying layer. A portion of the first radicals and the second radicals combine to form a polymer layer on the layer in the center of the space, and substantially simultaneously, another portion of thee first radicals remove the underlying layer near the base of the photoresists. The first radicals may be fluorine-rich and the second radicals may be carbon-rich.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: May 12, 2009
    Assignee: Intel Corporation
    Inventors: Qiquan Geng, Jeff J Xu, Everett B Lee, Michael T Ru, Hsu-en Yang, Chung Hui
  • Publication number: 20090078677
    Abstract: An integrated steerability array arrangement for managing plasma uniformity within a plasma processing environment to facilitate processing of a substrate is provided. The arrangement includes an array of electrical elements. The arrangement also includes an array of gas injectors, wherein the array of electrical elements and the array of gas injectors are arranged to create a plurality of plasma regions, each plasma region of the plurality of plasma regions being substantially similar. The arrangement further includes an array of pumps, wherein individual one of the array of pumps being interspersed among the array of electrical elements and the array of gas injectors. The array of pumps is configured to facilitate local removal of gas exhaust to maintain a uniform plasma region within the plasma processing environment.
    Type: Application
    Filed: June 24, 2008
    Publication date: March 26, 2009
    Inventor: Neil Benjamin
  • Publication number: 20090078678
    Abstract: A plasma processing apparatus for processing a substrate using plasma includes a first electrode configured to mount the substrate, a second electrode disposed to face the first electrode with a predetermined space, a chamber containing the first electrode and the second electrode, the chamber being capable of adjusting an inside atmosphere, a first electric power source device configured to apply a first RF voltage for controlling a self-bias voltage generated on the substrate to the first electrode, the first electric power source device applying a substantially constant width and a substantially constant value in a peak-to-peak voltage of an RF voltage of a first frequency at intervals, and a second electric power source device configured to apply a second RF voltage of a second frequency for generating plasma between the first and second electrodes to one of the first electrode and the second electrode.
    Type: Application
    Filed: September 12, 2008
    Publication date: March 26, 2009
    Inventors: Akihiro Kojima, Hisataka Hayashi, Akio Ui
  • Publication number: 20090045168
    Abstract: A surface treater system for three dimensional articles, especially elongated articles such as wires, cables and the like, increases the surface tension of the articles and thereby can be used to clean, etch and improve the wettabliity of the surface for inks, dyes, adhesives and the like. The treated article is supported by one or more guides that guide it through a long, narrow treatment zone. Two or more elongated electrodes are arranged in the treater to ionize working media within the treatment zone. The working media can be diffused and injected evenly along the entire length of the treatment zone to ensure consistent treatment along a long length of the treated article. An elongated barrier member can be provided to contain the working media in the treatment zone. Alternatively, working media can be injected and diffused from multiple, preferably opposing, sides of the treatment zone to further contain and disperse the working media, and provide essentially full-periphery surface treatment.
    Type: Application
    Filed: August 14, 2008
    Publication date: February 19, 2009
    Inventors: Jacob Hanson, Joseph Roethle
  • Patent number: 7491344
    Abstract: Disclosed herein is a method for etching a face of an object and more particularly a method for etching a rear face of a silicon substrate. The object having a silicon face is positioned so as to be spaced apart from a plasma-generating member by a predetermined interval distance. The plasma-generating member generates arc plasmas to form a plasma region. A reaction gas is allowed to pass through the plasma region to generate radicals having high energies and high densities. The radicals react with the object to etch the face of the object. The face of the object can be rapidly and uniformly etched.
    Type: Grant
    Filed: November 4, 2003
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-Sik Park, Chang-Jin Kang, Tae-Hyuk Ahn, Kyeong-Koo Chi, Sang-Hun Seo
  • Patent number: 7476328
    Abstract: A printed circuit board having prescribed conductive patterns formed on an insulating layer is provided about 20 mm apart from an AC electrode provided in a plasma etching device. An earth electrode is provided on the side opposing the AC electrode. More specifically, the printed circuit board is provided outside a sheath layer that is a region having a high plasma density generated in the vicinity of the AC electrode. The frequency of an AC power supply is preferably not more than 1 GHz. The pressure in the device is preferably in the range from 1.33×10?2 Pa to 1.33×102 Pa. The inter-electrode distance between the AC electrode and the earth electrode is preferably not more than 150 mm, more preferably from 40 mm to 100 mm.
    Type: Grant
    Filed: December 23, 2005
    Date of Patent: January 13, 2009
    Assignee: Nitto Denko Corporation
    Inventor: Takashi Oda
  • Patent number: 7465407
    Abstract: In a plasma processing method for supplying an electric power to a first electrode, making a first electrode have a ground potential, or making a first electrode have a floating potential while supplying gas to a plasma source arranged in a vicinity of an object to be processed at a pressure in a vicinity of an atmospheric pressure. The method includes processing a part of the object to be processed with a plasma in a state where an area of a surface of a potentially controlled second electrode, arranged in a position opposite to the plasma source via the object to be processed, is made superposed on the object to be processed smaller than an area of a surface of the plasma source superposed on the object to be processed.
    Type: Grant
    Filed: August 28, 2003
    Date of Patent: December 16, 2008
    Assignee: Panasonic Corporation
    Inventors: Mitsuo Saitoh, Tomohiro Okumura, Ichiro Nakayama
  • Publication number: 20080283501
    Abstract: A method of depositing or etching a micro- or nano-scale pattern on a work piece is disclosed, including the steps of: (a) placing the work piece in an electrochemical reactor in close proximity to a patterned tool; (b) connecting the work piece such that it is the anode if is to be etched or the cathode if it is to be deposited, and the patterned tool such that it is the counter electrode; (c) pumping electrolytic fluid necessary for the electrolytic operation of the cell formed between the two electrodes; and (d) applying a current across the electrodes to etch or deposit the work piece.
    Type: Application
    Filed: July 19, 2005
    Publication date: November 20, 2008
    Applicant: UNIVERSITY OF NEWCASTLE UPON TYNE
    Inventor: Sudipta Roy
  • Patent number: 7439188
    Abstract: A reactor for processing semiconductor wafers with electrodes and other surfaces that can be one of heated, textured and/or pre-coated in order to facilitate adherence of materials deposited thereon, and eliminate the disadvantages resulting from the spaulding, flaking and/or delaminating of such materials which can interfere with semiconductor wafer processing.
    Type: Grant
    Filed: June 22, 2001
    Date of Patent: October 21, 2008
    Assignee: Tegal Corporation
    Inventors: Stephen DeOrnellas, Leslie Jerde, Kurt Olson
  • Patent number: 7435687
    Abstract: The invention provides a plasma processing method and plasma processing device for manufacturing semiconductor devices in which the number of foreign particles being adhered to the wafer is reduced greatly and the yield is improved. In a plasma processing device having a plasma source capable of controlling plasma distribution, the shape of a sheath/bulk boundary above the wafer is controlled to a convexed shape when the plasma is turned on and off. By adding a step of applying a low source power and wafer bias power when the plasma is turned on and off in order to realize an out-high plasma distribution, it is possible to form a sheath that is thicker near the center of the wafer and thinner at the outer circumference portion thereof.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: October 14, 2008
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kenji Maeda, Tomoyuki Tamura, Hiroyuki Kobayashi, Kenetsu Yokogawa, Tadamitsu Kanekiyo
  • Publication number: 20080237186
    Abstract: A blow-off part 152 is provided with a blow-off port 1a? which is dimensioned small enough so as not to allow a blow-off stream to be blown off directly to a part of a wafer W which part is located at the more internal side of the wafer than the outer edge of the wafer W and not to be subjected to plasmatizing process. A suction part 151 is provided with a suction port 81A in associating with the blow-off part 152. The suction port 81A is disposed proximate to the blow-off port 1a? and forms a suction stream oriented generally in the reverse direction with respect to the blow-off stream.
    Type: Application
    Filed: October 31, 2007
    Publication date: October 2, 2008
    Inventors: Mitsuhide NOGAMI, Eiji Miyamoto
  • Publication number: 20080237187
    Abstract: A method for processing a substrate is disclosed. The method includes supporting the substrate in the plasma-processing chamber configured with a first electrode and a second electrode. The method also includes coupling a passive radio frequency (RF) circuit to the second electrode, the passive RF circuit being configured to adjust one or more of an RF impedance, an RF voltage potential, and a DC bias potential on the second electrode.
    Type: Application
    Filed: March 13, 2008
    Publication date: October 2, 2008
    Inventors: Rajinder Dhindsa, Alexei Marakhtanov, Eric Hudson, Andreas Fischer
  • Patent number: 7416677
    Abstract: An exhaust assembly is described for use in a plasma processing system, whereby secondary plasma is formed in the exhaust assembly between the processing space and chamber exhaust ports in order to reduce plasma leakage to a vacuum pumping system, or improve the uniformity of the processing plasma, or both. The exhaust assembly includes a powered exhaust plate in combination with a ground electrode is utilized to form the secondary plasma surrounding a peripheral edge of a substrate treated in the plasma processing system.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: August 26, 2008
    Assignee: Tokyo Electron Limited
    Inventor: Hiroyuki Takahashi
  • Publication number: 20080156772
    Abstract: Methods and apparatus for remedying arc-related damage to the substrate during plasma bevel etching. A plasma shield is disposed above the substrate to prevent plasma, which is generated in between two annular grounded plates, from reaching the exposed metallization on the substrate. Additionally or alternatively, a carbon-free fluorinated process source gas may be employed and/or the RF bias power may be ramped up gradually during plasma generation to alleviate arc-related damage during bevel etching. Also additionally or alternatively, helium and/or hydrogen may be added to the process source gas to alleviate arc-related damage during bevel etching.
    Type: Application
    Filed: December 29, 2006
    Publication date: July 3, 2008
    Inventors: Yunsang Kim, Jack Chen, Grace Fang, Andrew Bailey
  • Patent number: 7393460
    Abstract: The plasma processing method comprises the step of removing an organic material film forming an upper layer relative to a patterned SiOCH series film by the processing with a plasma of a process gas containing an O2 gas, wherein the plasma has an O2+ ion density not lower than 1×1011 cm?3 and an oxygen radical density not higher than 1×1014 cm?3.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: July 1, 2008
    Assignee: Tokyo Electron Limited
    Inventors: Masaru Hori, Kazuhiro Kubota
  • Patent number: 7390751
    Abstract: A dry etching method includes loading a wafer on a lower electrode having at least two cooling paths. Cooling fluids having different temperatures are supplied to each of the cooling paths of the lower electrode so that the multiple cooling paths are at different temperatures from one another. The wafer is etched during cooling.
    Type: Grant
    Filed: December 22, 2005
    Date of Patent: June 24, 2008
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Sang-Kwon Kim
  • Publication number: 20080110860
    Abstract: A method for processing a workpiece in a plasma reactor. The method comprises constraining plasma in the chamber away from the floor of the pumping annulus, providing an annular baffle while compensating for asymmetry of gas flow attributable to the pumping port, and providing a gas flow equalizer below the baffle having an eccentrically shaped opening. The method further includes modifying the radial distribution of plasma ion density and providing a magnetic plasma steering field having an edge high plasma ion density distribution tendency. The method further comprises locating the baffle at a sufficient distance below the workpiece to provide an edge low plasma ion density distribution tendency that compensates the edge high plasma ion density distribution tendency of the magnetic plasma steering field.
    Type: Application
    Filed: May 21, 2007
    Publication date: May 15, 2008
    Inventors: Matthew L. Miller, Daniel J. Hoffman, Steven C. Shannon, Michael Kutney, James Carducci, Andrew Nguyen
  • Publication number: 20080083700
    Abstract: Methods for processing wafers, wafer processing apparatus, micro-fluid ejection head substrates, and etching process are provided. One such method includes applying a clamping voltage to an electrostatic chuck sufficient to hold a wafer in a substantially planerized orientation adjacent to the electrostatic chuck. A heat transfer fluid flows through a three dimensional space between the wafer and the electrostatic chuck to cool the wafer by convective heat transfer during wafer processing.
    Type: Application
    Filed: November 21, 2006
    Publication date: April 10, 2008
    Applicant: LEXMARK INTERNATIONAL, INC.
    Inventors: David Laurier Bernard, Paul William Dryer, John William Krawczyk, Andrew Lee McNees, Girish Shivaji Patil, Richard Lee Warner
  • Patent number: 7335601
    Abstract: A method of manufacture includes processing an object in a chamber and subsequently generating an electrical force of attraction to float contaminants off of a region adjacent the processed object before the object is unloaded from the chamber. The object may be processed with the use of plasma. The plasma is produced by introducing a first gas into the chamber and applying a source power to the first gas. The plasma is extinguished after the object is processed with the use of the plasma. Then, a second gas is introduced into the chamber and a source power is applied to the second gas to generate the electrical force of attraction. At this time, the parameters are controlled so that particle contaminants are readily removed without any influence on the object. Also, the same electrode can be used to apply source power to both the first and second gas. Thus, the operation of removing the particle contaminants is relatively simple.
    Type: Grant
    Filed: October 24, 2005
    Date of Patent: February 26, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-Hyun Han, Seung-Ki Chae, Kee-Soo Park
  • Publication number: 20080035605
    Abstract: An exhaust assembly is described for use in a plasma processing system, whereby secondary plasma is formed in the exhaust assembly between the processing space and chamber exhaust ports in order to reduce plasma leakage to a vacuum pumping system, or improve the uniformity of the processing plasma, or both. The exhaust assembly includes a powered exhaust plate in combination with a ground electrode is utilized to form the secondary plasma surrounding a peripheral edge of a substrate treated in the plasma processing system.
    Type: Application
    Filed: August 11, 2006
    Publication date: February 14, 2008
    Applicant: TOKYO ELECTRON LIMITED
    Inventor: Hiroyuki Takahashi
  • Publication number: 20080023440
    Abstract: A method and system for treating a substrate using a ballistic electron beam is described, whereby the radial uniformity of the electron beam flux is adjusted by modulating the source radio frequency (RF) power. For example, a plasma processing system is described having a first RF power coupled to a lower electrode, which may support the substrate, a second RF power coupled to an upper electrode that opposes the lower electrode, and a negative high voltage direct current (DC) power coupled to the upper electrode to form the ballistic electron beam. The amplitude of the second RF power is modulated to affect changes in the uniformity of the ballistic electron beam flux.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Applicants: Tokyo Electron Limited, Texas Instruments
    Inventors: Lee Chen, Ping Jiang
  • Patent number: 7314574
    Abstract: An etching apparatus comprises a workpiece holder (21) for holding a workpiece (X), a plasma generator (10, 20) for generating a plasma (30) in a vacuum chamber (3), an orifice electrode (4) disposed between the workpiece holder (21) and the plasma generator (10, 20), and a grid electrode (5) disposed upstream of the orifice electrode (4) in the vacuum chamber (3). The orifice electrode (4) has orifices (4a) defined therein. The etching apparatus further comprises a voltage applying unit (25, 26) for applying a voltage between the orifice electrode (4) and the grid electrode (5) to accelerate ions from the plasma (30) generated by the plasma generator (10, 20) and to pass the extracted ions through the orifices (4a) in the orifice electrode (4), for generating a collimated neutral particle beam having an energy ranging from 10 eV to 50 eV.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: January 1, 2008
    Assignee: Ebara Corporation
    Inventors: Katsunori Ichiki, Kazuo Yamauchi, Hirokuni Hiyama, Seiji Samukawa
  • Patent number: 7309448
    Abstract: A process of selectively etching a sacrificial light absorbing material (SLAM) over a dielectric material, such as carbon doped oxide, on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a hydrofluorocarbon gas, an optional hydrogen-containing gas, an optional fluorine-rich fluorocarbon gas, a nitrogen gas, an oxygen gas, and an inert gas. The process could provide a SLAM to a dielectric material etching selectivity ratio greater than 10:1.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: December 18, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Hee Yeop Chae, Jeremiah T. P. Pender, Gerardo A. Delgadino, Xiaoye Zhao, Yan Ye
  • Patent number: 7306829
    Abstract: A plasma reactor has a reactor vessel and a pair of electrodes in the form of spaced apart and oppositely disposed metallic surfaces defining therebetween a plasma discharge space. At least one of the metallic surfaces is the surface of a metallic plate having a plurality of gas feed openings extending through the metallic surface towards said discharge space and from a distribution chamber extending along the plate opposite the discharge space. The distribution chamber has a wall opposite and distant from the plate and includes a gas inlet arrangement with a plurality of gas inlet openings distributed along the wall and connected to one or more gas feed lines to the reactor. A gas flow resistant coefficient between the one or more gas feed lines and at least a predominant portion of the connected inlet openings are at least substantially equal.
    Type: Grant
    Filed: November 21, 2002
    Date of Patent: December 11, 2007
    Assignee: Unaxis Balzers Aktiengesellschaft
    Inventors: Emmanuel Turlot, Jean-Baptiste Chevrier, Jacques Schmitt, Jean Barreiro
  • Patent number: 7291559
    Abstract: In a method of manufacturing a semiconductor device, a dummy sample and an actual device are prepared. The dummy sample and the actual device have substantially an identical layer and an identical resist pattern formed on the layer. Then, a dummy discharge is carried out. The layer and the resist pattern of the dummy sample are etched in an etching device so that the layer and the resist pattern of the dummy device are simultaneously slimmed. Finally, the layer and the resist pattern of the actual device are etched in the etching device after the etching of the dummy sample so that the layer and the resist pattern of the actual device are simultaneously slimmed.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: November 6, 2007
    Assignee: Oki Electric Industry Co., Ltd.
    Inventor: Akira Takahashi
  • Publication number: 20070251919
    Abstract: In the bevel etching apparatus relating to the present invention, a substrate is inserted between electrically connected electrodes. A high-frequency power source is connected to the electrodes, and ground potential is applied to a support unit that supports the substrate. Gas (atmosphere) is supplied to the gap between the electrodes and the application of the high-frequency electric power to the electrodes causes the generation of atmospheric-pressure glow discharge between the electrode and the substrate. Bevel etching is performed by rotating the substrate along the circumferential direction in this condition. According to this construction, the bevel etching can be simultaneously performed to the front surface, the rear surface and the side of the substrate without causing any configuration change in the substrate.
    Type: Application
    Filed: April 27, 2007
    Publication date: November 1, 2007
    Inventor: Shin-ichi Imai
  • Publication number: 20070246439
    Abstract: A gap filling method and a method for forming a memory device, including forming an insulating layer on a substrate, forming a gap region in the insulating layer, and repeatedly forming a phase change material layer and etching the phase change material layer to form a phase change material layer pattern in the gap region.
    Type: Application
    Filed: April 13, 2007
    Publication date: October 25, 2007
    Inventors: Jin-Il Lee, Choong-Man Lee, Sung-Lae Cho, Sang-Wook Lim, Hye-Young Park, Young-Lim Park
  • Publication number: 20070246440
    Abstract: A semiconductor memory device is provided in which a phase-change layer can be formed stably and electric current required to cause the phase change of the phase-change layer can be reduced. An edge portion of the phase-change layer is formed above a lower electrode. The edge portion is formed to assume a tapered shape in cross section such that the thickness of the phase-change layer varies above the contact area between the lower electrode and the phase-change layer. The tapered portion is filled with an oxide film. According to this configuration, the region in which the phase-change occurs can be restricted, and hence the phase-change layer can be heated efficiently, resulting in reduction of electric current required for heating.
    Type: Application
    Filed: April 18, 2007
    Publication date: October 25, 2007
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Homare Sato
  • Patent number: 7279429
    Abstract: In one embodiment, the present invention relates to a method for increasing the ignition reliability of a plasma in a plasma reactor, the method comprising: supplying a source gas to the plasma reactor, the source gas comprising: (a) at least one reactive compound; and (b) at least one ignition gas, wherein the at least one ignition gas increases the ignitability of the source gas as compared to the ignitability of the source gas lacking the at least one ignition gas.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: October 9, 2007
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Calvin T. Gabriel, Tzu-Yen Hsieh
  • Publication number: 20070193976
    Abstract: The invention provides a plasma processing apparatus and a plasma processing method capable of controlling the voltage of the processing substrate with high accuracy, thereby enabling a highly accurate plasma processing. According to the invention, a voltage Vw of the processing substrate is measured using a processing substrate with a voltage probe prepared in advance, and based on a bias voltage Vesc applied to an electrostatic chuck mechanism 200 and a bias current Iesc flowing through the electrostatic chuck mechanism 200, a capacity component Cesc which is an impedance representing the electric property of the electrostatic chuck mechanism 200 is computed numerically. Then, based on a predetermined expression, the voltage Vw of the processing substrate 102 is estimated using the bias voltage Vesc of the processing substrate 102 to be measured, the bias current Iesc flowing through the electrostatic chuck mechanism 200 and the capacity component Cesc which is the impedance acquired in advance.
    Type: Application
    Filed: August 21, 2006
    Publication date: August 23, 2007
    Inventors: Hitoshi Tamura, Naoki Yasui, Seiichi Watanabe
  • Patent number: 7223446
    Abstract: In a parallel flat plate type plasma CVD apparatus, plasma damage of constituent parts in a reaction chamber due to irregularity of dry cleaning in the reaction chamber is reduced and the cost is lowered. In the parallel flat plate type plasma CVD apparatus in which high frequency voltages of pulse waves having mutually inverted waveforms are applied to an upper electrode and a lower electrode, and the inversion interval of the pulse wave can be arbitrarily changed, the interior of the reaction chamber is dry cleaned.
    Type: Grant
    Filed: January 8, 2004
    Date of Patent: May 29, 2007
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Mitsuhiro Ichijo
  • Patent number: 7147793
    Abstract: An etch profile tailoring system (100), for use with an etching process carried out on a wafer (130), has a scavenging plate (170) with a baseline etch profile, and at least one etch profile tuning structure (such as a plug) (160) replaceably disposed with respect to the scavenging plate (170) and configured to alter the baseline etch profile during the etching process so as to arrive at a desired etch profile. A method of performing maintenance on an etch profile tailoring system (100) involves the steps of performing an etching process on a wafer in accordance with a desired etch profile, determining whether or not maintenance should be performed, and (if the maintenance decision indicates that maintenance should be performed) replacing with a second plug before conducting an etching process on additional wafers.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: December 12, 2006
    Assignee: Tokyo Electron Limited
    Inventor: Steven Fink
  • Patent number: 7144521
    Abstract: A method for etching a high aspect ratio feature through a mask into a layer to be etched over a substrate is provided. The substrate is placed in a process chamber, which is able to provide RF power at a first frequency, a second frequency different than the first frequency, and a third frequency different than the first and second frequency. An etchant gas is provided to the process chamber. A first etch step is provided, where the first frequency, the second frequency, and the third frequency are at power settings for the first etch step. A second etch step is provided, where the first frequency, the second frequency, and the third frequency are at a different power setting.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: December 5, 2006
    Assignee: Lam Research Corporation
    Inventors: Camelia Rusu, Rajinder Dhindsa, Eric A. Hudson, Mukund Srinivasan, Lumin Li, Felix Kozakevich
  • Patent number: 7144520
    Abstract: An etching apparatus comprises a workpiece holder (21) for holding a workpiece (X), a plasma generator (10, 20) for generating a plasma (30) in a vacuum chamber (3), an orifice electrode (4) disposed between the workpiece holder (21) and the plasma generator (10, 20), and a grid electrode (5) disposed upstream of the orifice electrode (4) in the vacuum chamber (3). The orifice electrode (4) has orifices (4a) defined therein. The etching apparatus further comprises a voltage applying unit (25, 26) for applying a voltage between the orifice electrode (4) and the grid electrode (5) to accelerate ions from the plasma (30) generated by the plasma generator (10, 20) and to pass the extracted ions through the orifices (4a) in the orifice electrode (4). A first collimated neutral particle beam is generated and applied to the workpiece (X) for etching a surface of a processing layer (60) of the workpiece (X).
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: December 5, 2006
    Assignees: Ebara Corporation, Japan as Represented by President of Tohoku University
    Inventors: Katsunori Ichiki, Kazuo Yamauchi, Hirokuni Hiyama, Seiji Samukawa
  • Patent number: 7135412
    Abstract: In the control method in a management system of semiconductor manufacturing equipment to enhance a product yield through a control of etching process, information of a corresponding lot for the etching process is recognized. It is checked whether the information of corresponding lot is for an etching process after a predetermined RF time of etching apparatus. RF time of the etching apparatus is compared with the predetermined RF time, and it is decided whether the etching process of corresponding lot can be performed in the etching apparatus if the etching process for the corresponding lot should be performed after a lapse of the predetermined RF time.
    Type: Grant
    Filed: December 8, 2004
    Date of Patent: November 14, 2006
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Min-Jae Na
  • Patent number: 7122125
    Abstract: An integrated etch process, for example as used for etching an anti-reflection layer and an underlying aluminum layer, in which the chamber wall polymerization is controlled by coating polymer onto the sidewall by a plasma deposition process prior to inserting the wafer into the chamber, etching the structure, and after removing the wafer from the chamber, plasma cleaning the polymer from the chamber wall. The process is process is particularly useful when the etching is performed in a multi-step process and the polymer is used for passivating the etched structure, for example, a sidewall in an etched structure and in which the first etching step deposits polymer and the second etching step removes polymer. The controlled polymerization eliminates interactions of the etching with the chamber wall material, produces repeatable results between wafers, and eliminates in the etching plasma instabilities associated with changing wall conditions.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: October 17, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Shashank C. Deshmukh, Thorsten B. Lill
  • Patent number: 7105100
    Abstract: A system and method for distributing gas to a substrate in a dry etch chamber make use of different flow channels to distribute the gas to different portions of a substrate. A first flow channel can be oriented to distribute gas to an inner portion of the substrate. A second flow channel can be oriented to distribute gas to an outer portion of the substrate. With different flow channels, the system and method enable separate control of gas distribution for different portions of the substrate. In particular, the flow channels allow separate control of gas flow rate, concentration, and flow time for different areas of the substrate. In this manner, gas distribution can be selectively controlled to compensate for different etch rates across the substrate surface. Also, gas distribution can be controlled as a function of etch rate patterns exhibited by different etch gasses used in successive process steps.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: September 12, 2006
    Assignee: Applied Materials, Inc.
    Inventor: Haruhiro H. Goto
  • Patent number: 7093560
    Abstract: A clamping ring configured to be coupled to a chamber structure of a plasma processing chamber is disclosed. The clamping ring has a plurality of holes for accommodating a plurality of fasteners. The clamping ring includes a plurality of flanges disposed around an outer periphery of the clamping ring, adjacent flanges of the plurality of flanges being disposed such that a hole of the plurality of holes that is disposed in between the adjacent flanges is about equidistant from the adjacent flanges. The plurality of flanges are configured to mate with the chamber structure. The clamping ring and the flanges are dimensioned such that when the plurality of flanges mate with the chamber structure, recesses between adjacent ones of the plurality of flanges form gaps between the clamping ring and the chamber structure.
    Type: Grant
    Filed: April 16, 2003
    Date of Patent: August 22, 2006
    Assignee: Lam Research Corporation
    Inventors: Jose Tong, Eric H. Lenz
  • Patent number: 7048869
    Abstract: In an oxide film etching process, a plasma having a suitable ratio of CF3, CF2, CF, F is necessary, and there is a problem in that the etching characteristic fluctuates with a temperature fluctuation of the etching chamber. Using a UHF type ECR plasma etching apparatus having a low electron temperature, a suitable dissociation can be obtained, and by maintaining the temperature of a side wall from 10° C. and 120° C., a stable etching characteristic can be obtained. Since oxide film etching using a low electron temperature and a high density plasma can be obtained, an etching result having a superior characteristic can be obtained, and, also, since the side wall temperature adjustment range is low, a simplified apparatus structure and a heat resistant performance countermeasure can be obtained easily.
    Type: Grant
    Filed: October 8, 1999
    Date of Patent: May 23, 2006
    Assignee: Hitachi, Ltd.
    Inventors: Kazue Takahashi, Toshio Masuda, Tetsunori Kaji, Ken'etsu Yokogawa
  • Patent number: 7029594
    Abstract: A plasma processing method for providing plasma processing to an object to be processed disposed within a vacuum processing chamber in which a process gas feeding device feeds process gas into the vacuum processing chamber, a wafer electrode is placed within the vacuum processing chamber for mounting the object to be processed, a wafer bias power generator applies self-bias voltage to the wafer electrode, and a plasma generator generates plasma within the vacuum processing chamber. The plasma processing method flattens either a positive side voltage or a negative side voltage of a voltage waveform of a high frequency voltage generated to the object at an arbitrary voltage.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: April 18, 2006
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Naoki Yasui, Masahiro Sumiya, Hitoshi Tamura, Seiichi Watanabe
  • Patent number: 7005032
    Abstract: To resolve a problem that an etching rate profile is changed by a position of a nozzle relative to a semiconductor wafer and accordingly, at a vicinity of an outer edge of the semiconductor wafer, an accurate machining result is difficult to achieve, gas including activated species produced by plasma is blown from a nozzle locally to a surface of the semiconductor wafer W supported on a wafer table concentrically therewith to thereby remove unevenness on the surface of the semiconductor wafer. In this case, the wafer table is provided with a radius larger than a radius of the semiconductor wafer supported thereby by an outstretched portion to thereby prevent an outer edge from being removed excessively by reflected gas.
    Type: Grant
    Filed: March 18, 2002
    Date of Patent: February 28, 2006
    Assignee: Speedfam Co., Ltd.
    Inventors: Michihiko Yanagisawa, Kazuyuki Tsuruoka, Chikai Tanaka
  • Patent number: 6972264
    Abstract: A method for dry-etching a Si substrate or a Si layer in a processing chamber includes the step of supplying an etching gas into the processing chamber, wherein the etching gas is a mixture gas including Cl2, O2 and NF3 and a residence time ? of the etching gas is equal to or greater than about 180 msec, the residence time ? being defined as: ?=pV/Q where p represents an inner pressure of the processing chamber; V, an effective volume of etching space formed on the Si substrate or the Si layer; and Q, a flow rate of the etching gas.
    Type: Grant
    Filed: September 5, 2003
    Date of Patent: December 6, 2005
    Assignee: Tokyo Electron Limited
    Inventors: Yoshitaka Saita, Masashi Yamaguchi
  • Patent number: 6926011
    Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: August 9, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bao-Ru Young, Chia-Shiung Tsai
  • Patent number: 6921722
    Abstract: There is provided a method of performing a surface treatment, such as coating, denaturation, modification and etching, on a surface of a substrate. The method comprises the steps of bringing a surface treatment gas into contact with a surface of a substrate, and irradiating the surface of the substrate with a fast particle beam to enhance an activity of the surface and/or the surface treatment gas, thereby facilitating a reaction between the surface and the gas. The fast particle beam may be selected from a group consisting of an electron beam, a charged particle beam, an atomic beam and molecular beam. For example, during a coating operation, chemical deposition of predetermined component elements of the gas onto the surface is effected and a predetermined portion of the surface of the substrate is irradiated with a particle beam to form a coating layer on the predetermined portion.
    Type: Grant
    Filed: May 30, 2001
    Date of Patent: July 26, 2005
    Assignee: Ebara Corporation
    Inventors: Naoaki Ogure, Kuniaki Horie, Yuji Araki, Hiroshi Nagasaka, Momoko Kakutani, Tohru Satake
  • Patent number: 6902683
    Abstract: A method of plasma-processing is provided which includes placing a sample on one of electrodes provided in a vacuum processing chamber and holding the sample onto the electrodes by an electrostatic attracting force. A processing gas is introduced into an environment in which said sample is placed, and the environment is evacuated to a pressure condition for processing said sample. The processing gas is then formed into a plasma under the pressure condition, the sample is processed by the plasma, and a pulse bias voltage having a pulse cycle of 0.1 ?m to 10 ?m is applied to the sample.
    Type: Grant
    Filed: May 5, 2000
    Date of Patent: June 7, 2005
    Assignee: Hitachi, Ltd.
    Inventors: Tetsunori Kaji, Shinichi Tachi, Toru Otsubo, Katsuya Watanabe, Katsuhiko Mitani, Junichi Tanaka
  • Patent number: 6896775
    Abstract: Magnetically enhanced plasma processing methods and apparatus are described. A magnetically enhanced plasma processing apparatus according to the present invention includes an anode and a cathode that is positioned adjacent to the anode. An ionization source generates a weakly-ionized plasma proximate to the cathode. A magnet is positioned to generate a magnetic field proximate to the weakly-ionized plasma. The magnetic field substantially traps electrons in the weakly-ionized plasma proximate to the cathode. A power supply produces an electric field in a gap between the anode and the cathode. The electric field generates excited atoms in the weakly-ionized plasma and generates secondary electrons from the cathode. The secondary electrons ionize the excited atoms, thereby creating a strongly-ionized plasma.
    Type: Grant
    Filed: October 29, 2002
    Date of Patent: May 24, 2005
    Assignee: Zond, Inc.
    Inventor: Roman Chistyakov
  • Patent number: 6889697
    Abstract: A three-step polymer removal process that reverses the conventional sequence in which polymer is removed. In the preferred embodiment of the present invention the polymer is first removed from the Gas Deposition Table, after this the polymer is stripped from the inner surface of the created contact hole.
    Type: Grant
    Filed: November 12, 2002
    Date of Patent: May 10, 2005
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Bao-Ru Young, Chia-Shiung Tsai
  • Patent number: 6863835
    Abstract: A plasma chamber apparatus and method employing a magnet system to block the plasma within the chamber interior from reaching the exhaust pump. An exhaust channel between the chamber interior and the pump includes a magnet and at least one deflector that creates turbulence in the flow of exhaust gases. The magnetic field and the turbulence produced by the deflector both increase the rate of recombination of charged particles in the gases, thereby reducing the concentration of charged particles sufficiently to quench the plasma downstream of the magnet and deflector, thereby preventing the plasma body within the chamber from reaching the exhaust pump. The plasma confinement effect of the magnetic field permits the use of a wider and/or less sinuous exhaust channel than would be required to block the plasma without the magnetic field.
    Type: Grant
    Filed: April 25, 2000
    Date of Patent: March 8, 2005
    Inventors: James D. Carducci, Hamid Noorbakhsh, Evans Y. Lee, Hongqing Shan, Siamak Salimian, Paul E. Luscher, Michael D. Welch