Using Plasma Patents (Class 216/67)
  • Patent number: 10541250
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryohei Kitao, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
  • Patent number: 10529633
    Abstract: A method of forming integrated circuit (IC) chips. After masking a layer of a material to be etched, the layer is subjected to an atomic layer etch (ALE). During the ALE, etch effluent is measured with a calorimetric probe. The calorimetric probe results reflect a species of particles resulting from etching the material. The measured etch results are checked until the results indicate the particle content is below a threshold value. When the content is below the threshold ALE is complete and IC chip fabrication continues normally.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sebastian U. Engelmann, Eric A. Joseph
  • Patent number: 10529581
    Abstract: Methods for isotropic etching at least a portion of a silicon-containing layer on a sidewall of high-aspect-ratio (HAR) apertures formed on a substrate in a reaction chamber are disclosed. The HAR aperture formed by plasma etching a stack of alternating layers of a first silicon-containing layer and a second silicon-containing layer, the second silicon-containing layer is different from the first silicon-containing layer. The method comprising the steps of: a) introducing a fluorine containing etching gas selected from the group consisting of nitrosyl fluoride (FNO), trifluoroamine oxide (F3NO), nitryl fluoride (FNO2) and combinations thereof into the reaction chamber; and b) removing at least a portion of the second silicon-containing layers by selectively etching the second silicon-containing layers versus the first silicon-containing layers with the fluorine containing etching gas to produce recesses between the first silicon-containing layers on the sidewall of the HAR aperture.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 7, 2020
    Assignees: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude, Air Liquide Electronics U.S. LP
    Inventors: Chih-Yu Hsu, Peng Shen, Takashi Teramoto, Nathan Stafford, Jiro Yokota
  • Patent number: 10522429
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following operations. (a) A substrate is patterned. (b) A polymer layer is formed on the patterned substrate. (c) The polymer layer is patterned. Steps (a), (b) and (c) are repeated alternatingly. An intensity of an emission light generated by a reaction of a plasma and a product produced in steps (a), (b) and (c) is detected. An endpoint in patterning the substrate is determined according to the intensity of the emission light generated by the reaction of the plasma and the product produced in only one step of steps (a), (b) and (c). A sampling rate of the intensity is ranged from 1 pt/20 ms to 1 pt/100 ms. A smooth function is used to process the intensity of the emission light generated by the reaction of the plasma and the product.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu
  • Patent number: 10510512
    Abstract: Embodiments of method and system for controlling plasma performance are described. In an embodiment a method may include supplying power at a first set of power parameters to a plasma chamber. Additionally, the method may include forming plasma within the plasma chamber using the first set of power parameters. The method may also include measuring power coupling to the plasma at the first set of power parameters. Also, the method may include supplying power at a second set of power parameters to the plasma chamber. The method may additionally include measuring power coupling to the plasma at the second set of power parameters to the plasma. The method may also include adjusting the first set of power parameters based, at least in part, on the measuring of the power coupling at the second set of power parameters.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Megan Doppel, Kazuki Moyama, Chelsea DuBose, Justin Moses
  • Patent number: 10504699
    Abstract: Embodiments described herein include a modular high-frequency emission source comprising a plurality of high-frequency emission modules and a phase controller. In an embodiment, each high-frequency emission module comprises an oscillator module, an amplification module, and an applicator. In an embodiment, each oscillator module comprises a voltage control circuit and a voltage controlled oscillator. In an embodiment, each amplification module is coupled to an oscillator module, in an embodiment, each applicator is coupled to an amplification module. In an embodiment, the phase controller is communicatively coupled to each oscillator module.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 10, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Philip Allan Kraus, Thai Cheng Chua, Christian Amormino, Dmitry A. Dzilno
  • Patent number: 10488750
    Abstract: In a mask blank comprising a transparent substrate and a single layer or multilayer film formed thereon, the film is formed only on the front surface of the substrate, but not on the side surface, chamfer, front surface-chamfer boundary, and back surface-chamfer boundary. The mask blank contains few particle defects, especially the number of particle defects with a certain size is zero.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 26, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yukio Inazuki, Hideo Kaneko
  • Patent number: 10475704
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 12, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Mitsuru Hiroshima, Mitsuhiro Okune
  • Patent number: 10424460
    Abstract: A plasma source includes a ring plasma chamber, a primary winding around an exterior of the ring plasma chamber, multiple ferrites, wherein the ring plasma chamber passes through each of the ferrites and multiple plasma chamber outlets coupling the plasma chamber to a process chamber. Each one of the plasma chamber outlets having a respective plasma restriction. A system and method for generating a plasma are also described.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 24, 2019
    Assignee: Lam Research Corporation
    Inventors: Ali Shajii, Richard Gottscho, Souheil Benzerrouk, Andrew Cowe, Siddharth P. Nagarkatti, William R. Entley
  • Patent number: 10410877
    Abstract: An etching method for etching a silicon oxide film is provided that includes generating a plasma from a gas including a hydrogen-containing gas and a fluorine-containing gas using a high frequency power for plasma generation, and etching the silicon oxide film using the generated plasma. The fluorine-containing gas includes a hydrofluorocarbon gas, and the sticking coefficient of radicals generated from the hydrofluorocarbon gas is higher than the sticking coefficient of radicals generated from carbon tetrafluoride (CF4).
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 10, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Ryuichi Takashima, Taku Gohira, Yoshinobu Ooya
  • Patent number: 10410838
    Abstract: An apparatus (9) for plasma treating multiple containers. The apparatus includes a manifold (2) comprising at least a first chamber with multiple outlet openings and multiple hollow, electrically-conductive nozzles (10) for at least one of delivering or exhausting plasma-generating gas. The multiple hollow, electrically-conductive nozzles are connected to the multiple outlet openings and protrude from the manifold. A method of plasma treating multiple containers is also disclosed. The method includes providing a reactor system comprising an apparatus disclosed herein, inserting the multiple hollow, electrically-conductive nozzles into the multiple containers (30), evacuating the multiple containers, grounding the multiple hollow, electrically-conductive nozzles while applying radio frequency power to the multiple containers, providing a gas inside the containers, and generating a plasma. At least one of evacuating or providing the gas is carried out through the hollow, electrically-conductive nozzles.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: September 10, 2019
    Assignee: 3M Innovative Properties Company
    Inventors: Daniel R. Hanson, Moses M. David, David J. White, Jean A. Kelly, Todd D. Alband
  • Patent number: 10399723
    Abstract: A system includes a cold plasma applicator configured to couple directly to a container, wherein the cold plasma applicator is configured to generate a cold plasma within the container. A method includes operating a cold plasma applicator to generate a cold plasma to treat contents within a container, wherein the cold plasma applicator is configured to directly couple to the container, or the cold plasma applicator comprises a varying geometry application surface having a plurality of protruding electrode portions spaced apart from one another to define a plurality of intermediate recessed portions, or a combination thereof.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: September 3, 2019
    Assignee: PLASMOLOGY4, INC.
    Inventors: Emilia M. Kulaga, Steven A. Myers, Marc C. Jacofsky, Jeffrey I. Meyers
  • Patent number: 10395935
    Abstract: A plasma processing apparatus includes a plasma processing chamber processing a sample using plasma, a radio frequency power supply supplying radio frequency power for generating the plasma, a sample stage including an electrode electrostatically chucking the sample, mounting the sample thereon, a DC power supply applying DC voltage to the electrode, and a control device shifting the DC voltage previously set, in a negative direction by a first shift amount during discharge of the plasma, shifting the DC voltage having been shifted in the negative direction by the first shift amount, in a positive direction by a second shift amount after the discharge of the plasma. The first shift amount has a value changing potential over a surface of the sample to 0 V, upon shifting the DC voltage in the positive direction. The second shift amount has a value obtained based on a floating potential of the plasma.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 27, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masaki Ishiguro, Masahiro Sumiya, Shigeru Shirayone, Kazuyuki Ikenaga, Tomoyuki Tamura
  • Patent number: 10361091
    Abstract: A method for etching features into a porous low-k dielectric etch layer is provided. A plurality of cycles is performed in a plasma processing chamber. Each cycle comprises a deposition phase and an activation phase. The deposition phase comprises flowing a deposition gas comprising a fluorocarbon and/or hydrofluorocarbon gas, creating a plasma in the plasma processing chamber using the deposition gas, depositing a fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the deposition gas. The activation phase comprises flowing an activation gas comprising a noble gas and a carbon etching additive, creating a plasma in the plasma processing chamber using the activation gas, providing an activation bias in the plasma processing chamber, wherein the activation bias causes the etching of the low-k dielectric layer, with consumption of the fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the activation gas.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Lam Research Corporation
    Inventors: Eric Hudson, Shashank Deshmukh, Sonny Li, Chia-Chun Wang, Prabhakara Gopaladasu, Zihao Ouyang
  • Patent number: 10347465
    Abstract: Embodiments of the present invention relate to apparatus for enhancing deposition rate and improving a plasma profile during plasma processing of a substrate. According to embodiments, the apparatus includes a tuning electrode disposed in a substrate support pedestal and electrically coupled to a variable capacitor. The capacitance is controlled to control the RF and resulting plasma coupling to the tuning electrode. The plasma profile and the resulting deposition rate and deposited film thickness across the substrate are correspondingly controlled by adjusting the capacitance and impedance at the tuning electrode.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 9, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mohamad A. Ayoub, Jian J. Chen, Amit K. Bansal
  • Patent number: 10312101
    Abstract: A substrate processing method includes a fluorine-based gas supply step of supplying a fluorine-based gas into a processing chamber where a substrate having a silicon-based film is accommodated, a purge gas supply step of supplying a purge gas for discharging the supplied fluorine-based gas into the processing chamber. The substrate processing method further includes a nitrogen-based gas supply step of supplying a nitrogen-based gas into the processing chamber from which the fluorine-based gas has been discharged. In the substrate processing method, at least in the fluorine-based gas supply step and the purge gas supply step, a temperature of the substrate is maintained at 60° C. or less.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 4, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shuji Moriya, Masahiko Tomita
  • Patent number: 10304692
    Abstract: A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Robert L. Bruce, Sebastian U. Engelmann, Nathan P. Marchack, Hiroyuki Miyazoe, Jeffrey C. Shearer, Takefumi Suzuki
  • Patent number: 10290506
    Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: May 14, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Akiteru Ko
  • Patent number: 10217611
    Abstract: A plasma processing apparatus or a plasma processing method that processes a wafer to be processed, which is placed on a surface of a sample stage arranged in a processing chamber inside a vacuum container, using a plasma formed in the processing chamber, the apparatus or method including processing the wafer by adjusting a first high-frequency power to be supplied to a first electrode arranged inside the sample stage and a second high-frequency power to be supplied, via a resonant circuit, to a second electrode which is arranged in an inner side of a ring-shaped member made of a dielectric arranged on an outer peripheral side of a surface of the sample stage on which the wafer is placed, during the processing.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: February 26, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tooru Aramaki, Kenetsu Yokogawa, Masaru Izawa
  • Patent number: 10211153
    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Elbert E. Huang, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath, Chih-Chao Yang
  • Patent number: 10186428
    Abstract: Exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. Methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The methods may also include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region, and the substrate may include a region of exposed oxide. Methods may also include providing a hydrogen-containing precursor to the processing region. The methods may further include removing at least a portion of the exposed oxide while maintaining a relative humidity within the processing region below about 50%. Subsequent to the removal, the methods may include increasing the relative humidity within the processing region to greater than or about 50%. The methods may further include removing an additional amount of the exposed oxide.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: January 22, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Lin Xu, Zhijun Chen, Jiayin Huang, Anchuan Wang
  • Patent number: 10163610
    Abstract: An edge ring assembly for a plasma processing chamber is provided, including: an edge ring configured to surround an electrostatic chuck (ESC) that is configured for electrical connection to a first RF power supply, the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface; an annular electrode disposed below the edge ring in the annular step and above the annular shelf; a dielectric ring disposed below the annular electrode for isolating the annular electrode from the ESC, the dielectric ring positioned in the annular step over the annular shelf; and, a plurality of insulated connectors disposed through the ESC and through the dielectric ring, each of the plurality of insulated connectors providing electrical connection between a second RF power supply and the annular electrode.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 25, 2018
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Tom A. Kamp, Alexander Paterson
  • Patent number: 10134625
    Abstract: In accordance with various embodiments of the disclosed subject matter, a shallow trench isolation structure and a fabricating method thereof are provided. The method for forming the shallow trench isolation structure may include: providing a semiconductor substrate; forming a shallow trench in the semiconductor substrate; forming a first insulating layer on a surface of the semiconductor substrate and in the shallow trench, a portion of the first insulating layer in the shallow trench includes an opening; etching the first insulating layer to increase a width of the opening; after etching the first insulating layer, performing a plasma treatment to an exposed surface of the first insulating layer; after the plasma treatment, cleaning the surface of the first insulating layer; and after cleaning the surface of the first insulating layer, filling a second insulating layer into the shallow trench.
    Type: Grant
    Filed: August 26, 2016
    Date of Patent: November 20, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Hao Deng, Yan Yan, Jun Yang, Tingting Peng
  • Patent number: 10121674
    Abstract: Disclosed is a method of etching a silicon layer by removing an oxide film formed on a workpiece which includes the silicon layer and a mask provided on the silicon layer. The method includes: (a) forming a denatured region by generating plasma of a first processing gas containing hydrogen, nitrogen, and fluorine within a processing container accommodating the workpiece therein to denature an oxide film formed on a surface of the workpiece; (b1) removing the denatured region by generating plasma of a rare gas within the processing container; and (c) etching the silicon layer by generating plasma of a second processing gas within the processing container.
    Type: Grant
    Filed: July 20, 2017
    Date of Patent: November 6, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Akinori Kitamura, Eiji Suzuki
  • Patent number: 10121640
    Abstract: The present invention provides a plasma processing method that uses a plasma processing apparatus including a plasma processing chamber in which a sample is plasma processed, a first radio-frequency power supply that supplies a first radio-frequency power for generating plasma, and a second radio-frequency power supply that supplies a second radio-frequency power to a sample stage on which the sample is mounted, wherein the plasma processing method includes the steps of modulating the first radio-frequency power by a first pulse; and controlling a plasma dissociation state to create a desired dissociation state by gradually controlling a duty ratio of the first pulse as a plasma processing time elapses.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: November 6, 2018
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Satoru Muto, Tetsuo Ono, Yasuo Ohgoshi, Hirofumi Eitoku
  • Patent number: 10121639
    Abstract: A method for processing substrate in a chamber, which has at least one plasma generating source, a reactive gas source for providing reactive gas into the interior region of the chamber, and a non-reactive gas source for providing non-reactive gas into the interior region, is provided. The method includes performing a mixed-mode pulsing (MMP) preparation phase, including flowing reactive gas into the interior region and forming a first plasma to process the substrate that is disposed on a work piece holder. The method further includes performing a MMP reactive phase, including flowing at least non-reactive gas into the interior region, and forming a second plasma to process the substrate, the second plasma is formed with a reactive gas flow during the MMP reactive phase that is less than a reactive gas flow during the MMP preparation phase. Perform the method steps a plurality of times.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: November 6, 2018
    Assignee: Lam Research Corporation
    Inventor: Keren Jacobs Kanarik
  • Patent number: 10111313
    Abstract: According to one embodiment, a plasma processing apparatus includes: a processing chamber; a decompression section configured to decompress inside of the processing chamber; a member including a control section to be inserted into a depression provided on mounting side of a workpiece, the control section being configured to thereby control at least one of in-plane distribution of capacitance of a region including the workpiece and in-plane distribution of temperature of the workpiece; a mounting section provided inside the processing chamber; a plasma generating section configured to supply electromagnetic energy to a region for generating a plasma for performing plasma processing on the workpiece; and a gas supply section configured to supply a process gas to the region for generating a plasma. The control section performs control so that at least one of the in-plane distribution of capacitance and the in-plane distribution of temperature is made uniform.
    Type: Grant
    Filed: March 19, 2013
    Date of Patent: October 23, 2018
    Assignee: SHIBAURA MECHATRONICS CORPORATION
    Inventors: Takeharu Motokawa, Tokuhisa Ooiwa, Kensuke Demura, Tomoaki Yoshimori, Makoto Karyu, Yoshihisa Kase, Hidehito Azumano
  • Patent number: 10103011
    Abstract: A plasma processing apparatus 1 includes a chamber 10, a mounting table 16, a focus ring 24a, a first electrode plate 36 and a second electrode plate 35. The focus ring 24a is provided around the mounting table 16 to surround a mounting surface of the mounting table 16. The first electrode plate 36 is provided above the mounting table 16. The second electrode plate 35 is provided around the first electrode plate 36 to surround the first electrode plate 36 and is insulated from the first electrode plate 36. The plasma processing apparatus 1, in a first process, performs a preset processing on a semiconductor wafer W mounted on the mounting surface with plasma generated within the chamber, and, in a second process, increases an absolute value of a negative DC voltage applied to the second electrode plate 35 depending on an elapsed time of the first process.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: October 16, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hiroki Kishi, Jisoo Suh
  • Patent number: 10090191
    Abstract: A method includes performing one or more times of a sequence and reducing a film thickness of a fluorocarbon-containing film formed by performing one or more times of the sequence. Each of the one or more times of the sequence includes forming the fluorocarbon-containing film on a processing target object by generating plasma of a processing gas containing a fluorocarbon gas and not containing an oxygen gas; and etching a first region with radicals of fluorocarbon contained in the fluorocarbon-containing film. In the method, an alternating repetition in which the one or more times of the sequence and the reducing of the film thickness of the fluorocarbon-containing film are alternately repeated is performed.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: October 2, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Maju Tomura, Takayuki Katsunuma, Masanobu Honda
  • Patent number: 10087525
    Abstract: A reaction system for processing semiconductor substrates is disclosed. The reaction system includes a susceptor for holding the substrate as well as a baseplate as a part of housing for the reaction system. A pin located on the susceptor can interact with a baseplate feature located on the baseplate to result in a variable gap between the susceptor and the baseplate. The baseplate feature may take the form of a series of steps, a wedge, or a milled-out feature.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: October 2, 2018
    Assignee: ASM IP Holding B.V.
    Inventors: Michael Schmotzer, Shawn Whaley
  • Patent number: 10062609
    Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo Kyung You, Jong Min Baek, Sang Shin Jang, Byung Hee Kim, Vietha Nguyen, Nae In Lee, Woo Jin Lee, Eun Ji Jung, Kyu Hee Han
  • Patent number: 10062576
    Abstract: A method of plasma etching one or more features in a silicon substrate includes performing a main etch using a cyclical etch process in which a deposition step and an etch step are alternately repeated, and performing an over etch to complete the plasma etching of the features. The over etch includes one or more etch steps of a first kind and one or more etch steps of a second kind, each of the etch steps of the first and second kind include etching by ion bombardment of the silicon substrate. The ion bombardment during the one or more etch steps of the second kind has an inward inclination with respect to ion bombardment during the one or more etch steps of the first kind.
    Type: Grant
    Filed: May 8, 2017
    Date of Patent: August 28, 2018
    Assignee: SPTS TECHNOLOGIES LIMITED
    Inventors: Nicolas Launay, Maxine Varvara
  • Patent number: 10056233
    Abstract: Embodiments of the disclosure generally relate to a hybrid plasma processing system incorporating a remote plasma source (RPS) unit with a capacitively coupled plasma (CCP) unit for substrate processing. In one embodiment, the hybrid plasma processing system includes a CCP unit, comprising a lid having one or more through holes, and an ion suppression element, wherein the lid and the ion suppression element define a plasma excitation region, a RPS unit coupled to the CCP unit, and a gas distribution plate disposed between the ion suppression element and a substrate support, wherein the gas distribution plate and the substrate support defines a substrate processing region. In cases where process requires higher power, both CCP and RPS units may be used to generate plasma excited species so that some power burden is shifted from the CCP unit to the RPS unit, which allows the CCP unit to operate at lower power.
    Type: Grant
    Filed: June 28, 2017
    Date of Patent: August 21, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Xinglong Chen, Saurabh Garg, Jang-Gyoo Yang
  • Patent number: 10056232
    Abstract: A charged particle beam apparatus according to this invention includes: a gas introduction chamber, into which raw gas is introduced; a plasma generation chamber connected to the gas introduction chamber; a coil that is wound along an outer circumference of the plasma generation chamber and to which high-frequency power is applied; an electrode arranged at a boundary between the gas introduction chamber and the plasma generation chamber and having a plurality of through-holes formed therein; a plasma electrode that is provided apart from the electrode; a detection unit for detecting whether or not the plasma has been ignited in the plasma generation chamber; and a controller that controls, based on the result of detection by the detection unit, a voltage to be supplied to the plasma electrode in association with a predetermined pressure for supplying the raw gas.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: August 21, 2018
    Assignee: Hitachi High-Tech Science Corporation
    Inventors: Hiroshi Oba, Yasuhiko Sugiyama
  • Patent number: 10047439
    Abstract: A method and system for removing control action effects from inline measurement data for tool condition monitoring is disclosed. An exemplary method includes determining a control action effect that contributes to an inline measurement, wherein the inline measurement indicates a wafer characteristic of a wafer processed by a process tool; and evaluating the inline measurement without the control action effect contribution to determine a condition of the process tool.
    Type: Grant
    Filed: December 8, 2011
    Date of Patent: August 14, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Feng Tsai, Chia-Tong Ho, Sunny Wu, Jo Fei Wang, Jong-I Mou, Chin-Hsiang Lin
  • Patent number: 10043684
    Abstract: Systems and methods of etching a semiconductor substrate may include flowing an oxygen-containing precursor into a substrate processing region of a semiconductor processing chamber. The substrate processing region may house the semiconductor substrate, and the semiconductor substrate may include an exposed metal-containing material. The methods may include flowing a nitrogen-containing precursor into the substrate processing region. The methods may further include removing an amount of the metal-containing material.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: August 7, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Ranga Rao Arnepalli, Prerna Sonthalia Goradia, Robert Jan Visser, Nitin Ingle, Mikhail Korolik, Jayeeta Biswas, Saurabh Lodha
  • Patent number: 10037883
    Abstract: Embodiments described herein generally relate to an apparatus and methods for reducing the deposition of polymers in a semiconductor processing chamber. A heater jacket and heat sources are provided and may be configured to maintain a uniform temperature profile of the processing chamber. A method of maintaining a uniform temperature profile of a dielectric ceiling of the processing chamber is also provided.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: July 31, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Robert Chebi, Alfredo Granados, Zhao H. Ceng, Jianqi Wang, Rajan Balesan
  • Patent number: 10037890
    Abstract: A method for selectively etching an etch layer with respect to a mask is provided. An etch process is provided comprising a plurality of etch cycles, wherein each etch cycle comprises providing a deposition phase and an etch phase. The deposition phase comprises providing a flow of a deposition phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio, providing a RF power, which forms the deposition phase gas into a plasma, and stopping the deposition phase. The etch phase, comprises providing a flow of an etch phase gas, comprising a fluorocarbon or hydrofluorocarbon containing gas and an oxygen containing gas with a fluorocarbon or hydrofluorocarbon to oxygen ratio that is lower than the fluorocarbon or hydrofluorocarbon to oxygen ratio of the deposition phase gas, providing a RF power, and stopping the etch phase.
    Type: Grant
    Filed: October 11, 2016
    Date of Patent: July 31, 2018
    Assignee: Lam Research Corporation
    Inventors: Adarsh Basavalingappa, Peng Wang, Bhaskar Nagabhirava, Michael Goss, Prabhakara Gopaladasu, Randolph Knarr, Stefan Schmitz, Phil Friddle
  • Patent number: 10026591
    Abstract: An ion beam etching device includes a grid provided between a treatment chamber and a plasma generation chamber, and for forming an ion beam by drawing ions from the plasma generation chamber; a gas introduction unit for introducing discharge gas into the plasma generation chamber; an exhaust for exhausting the treatment chamber; a substrate holder; a control unit to receive a measurement result of an in-plane film thickness distribution before the substrate is processed; and an electromagnetic coil provided outside of the plasma generation chamber in a ceiling portion opposite to the grid of the plasma generation chamber. The electromagnetic coil includes an outer coil provided on an outer circumference of the ceiling portion and an inner coil provided on an inner circumference of the ceiling portion, and the control unit controls the currents applied to the outer coil and the inner coil in accordance with the measurement result.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: July 17, 2018
    Assignee: Canon Anelva Corporation
    Inventors: Yoshimitsu Kodaira, Yukito Nakagawa, Motozo Kurita
  • Patent number: 10026643
    Abstract: Some embodiments include methods of forming voids within semiconductor constructions. In some embodiments the voids may be utilized as microstructures for distributing coolant, for guiding electromagnetic radiation, or for separation and/or characterization of materials. Some embodiments include constructions having micro-structures therein which correspond to voids, conduits, insulative structures, semiconductor structures or conductive structures.
    Type: Grant
    Filed: August 27, 2017
    Date of Patent: July 17, 2018
    Assignee: Micron Technology, Inc.
    Inventor: David H. Wells
  • Patent number: 10002744
    Abstract: This disclosure relates to a plasma processing system for controlling plasma density near the edge or perimeter of a substrate that is being processed. The plasma processing system may include a plasma chamber that can receive and process the substrate using plasma for etching the substrate, doping the substrate, or depositing a film on the substrate. This disclosure relates to a plasma processing system that may include a power electrode that may be opposite a bias electrode and a focus ring electrode that surrounds the substrate. In one embodiment, the power electrode may be coupled to a direct current (DC) source. Power applied to the bias electrode may be used to draw ions to the substrate. The plasma density may be made more uniform by applying a focus ring voltage to the focus ring that is disposed around the substrate and/or the bias electrode.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: June 19, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Lee Chen, Peter L. G. Ventzek, Barton G. Lane
  • Patent number: 9997333
    Abstract: A method for achieving sub-pulsing during a state is described. The method includes receiving a clock signal from a clock source, the clock signal having two states and generating a pulsed signal from the clock signal. The pulsed signal has sub-states within one of the states. The sub-states alternate with respect to each other at a frequency greater than a frequency of the states. The method includes providing the pulsed signal to control power of a radio frequency (RF) signal that is generated by an RF generator. The power is controlled to be synchronous with the pulsed signal.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: June 12, 2018
    Assignee: Lam Research Corporation
    Inventors: John C. Valcore, Jr., Harmeet Singh, Bradford J. Lyndaker
  • Patent number: 9994480
    Abstract: The present invention relates in a first aspect to a method for etching a primary preform or core rod. The present invention moreover relates in a second aspect to the etched primary preform thus obtained and moreover to a final preform and optical fibers obtained therefrom and to a method of preparing optical fibers therefrom.
    Type: Grant
    Filed: October 14, 2016
    Date of Patent: June 12, 2018
    Assignee: Draka Comteq, B.V.
    Inventors: Igor Milicevic, Mattheus Jacobus Nicolaas Van Stralen, Gertjan Krabshuis, Johannes Antoon Hartsuiker
  • Patent number: 9984896
    Abstract: The present invention is a fluorohydrocarbon represented by R—F wherein R represents an isobutyl group or a t-butyl group), the fluorohydrocarbon having a purity of 99.9% by volume or more and a total butenes content of 1,000 ppm by volume or less; a use of the fluorohydrocarbon as a plasma etching gas; and a plasma etching method comprising selectively subjecting an inorganic nitride film stacked on silicon or a silicon oxide film to plasma etching using the fluorohydrocarbon.
    Type: Grant
    Filed: October 28, 2014
    Date of Patent: May 29, 2018
    Assignee: ZEON CORPORATION
    Inventor: Tatsuya Sugimoto
  • Patent number: 9978606
    Abstract: Methods and apparatus for processing substrates are provided. In some embodiments, methods of processing substrates includes: (a) providing a process gas comprising a polymer-forming gas and an etching gas between a first electrode and a second electrode within the processing volume, wherein the first electrode is opposite the second electrode; (b) applying a first voltage waveform from a first RF power source to the second electrode to form a plasma from the process gas, wherein the plasma has a first ion energy to deposit a polymer layer directly atop a dielectric layer of the substrate; and (c) adjusting the first voltage waveform to a second voltage waveform to increase an ion energy of the plasma from the first ion energy to a second ion energy, wherein the plasma at the second ion energy ceases to deposit the polymer layer and proceeds to etch the polymer layer and the dielectric layer.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: May 22, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventor: Ankur Agarwal
  • Patent number: 9966239
    Abstract: This disclosure relates to a plasma processing system for controlling plasma density across a substrate and maintaining a tight ion energy distribution within the plasma. In one embodiment, this may include using a dual plasma chamber system including a non-ambipolar plasma chamber and a DC plasma chamber adjacent to the non-ambipolar system. The DC plasma chamber provide power to generate the plasma by rotating the incoming power between four inputs from a VHF power source. In one instance, the power to each of the four inputs are at least 90 degrees out of phase from each other.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: May 8, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Lee Chen, Zhiying Chen
  • Patent number: 9960142
    Abstract: A package component includes a surface dielectric layer having a first planar surface, and a metal pad in the surface dielectric layer. The metal pad includes a diffusion barrier layer that includes sidewall portions, and a metallic material encircled by the sidewall portions of the diffusion barrier layer. The metallic material has a second planar surface level with the first planar surface. An air gap extends from the second planar surface of the metallic material into the metallic material. An edge of the air gap is aligned to an edge of the metallic material.
    Type: Grant
    Filed: March 16, 2016
    Date of Patent: May 1, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Ying Chen, Dun-Nian Yaung
  • Patent number: 9953854
    Abstract: A method of adsorbing a target object on a mounting table is provided. The mounting table is provided within a processing vessel that partitions a depressurizable space in a processing apparatus which processes a processing target object within the space. Further, the processing apparatus serves as a plasma processing apparatus. The method includes mounting the target object on an electrostatic chuck of the mounting table; and applying three AC voltages having different phases to three electrodes of the electrostatic chuck, respectively.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: April 24, 2018
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yasuharu Sasaki, Akihito Fushimi
  • Patent number: 9947715
    Abstract: The present invention makes it possible to improve the performance of a semiconductor device. After anisotropic etching is applied to an insulating film covering a gate electrode of a transfer transistor and a sidewall spacer is formed over the sidewall of the gate electrode, a damaged layer formed in the interior of a semiconductor substrate by the anisotropic etching is removed by oxidizing the surface of the semiconductor substrate, forming a sacrificial oxide film, and removing the sacrificial oxide film.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: April 17, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Tadashi Yamaguchi
  • Patent number: 9945033
    Abstract: Apparatus for processing substrates are provided herein. In some embodiments, plasma processing apparatus may include a process chamber having a dielectric lid and an interior processing volume beneath the dielectric lid, a first RF coil to couple RF energy into the processing volume, and an RF shielded lid heater coupled to a top surface of the dielectric lid. The RF shielded lid heater may include an annular member, and a plurality of spokes, wherein each of the plurality of spokes includes one of (a) a first portion that extends downward from the annular and couples the annular member to a second portion of the spoke that extends radially inward, or (b) a first portion that extends radially outward from the annular member.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: April 17, 2018
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Samer Banna, Vladimir Knyazik, Waheb Bishara, Valentin Todorow