Using Plasma Patents (Class 216/67)
  • Patent number: 11367597
    Abstract: An electrostatic chuck includes a chuck base having a first hole, an upper plate provided on the chuck base, the upper plate having a second hole aligned with the first hole, and an adhesive layer attaching the upper plate to the chuck base, the adhesive layer having a thickness that is less than a diameter of the first hole and equal to a diameter of the second hole.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: June 21, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yongwoo Lee, Youngjin Noh, Dowon Kim, Donghyeon Na, Seungbo Shim
  • Patent number: 11361944
    Abstract: A plasma processing method, including: a trenched substrate preparation process of preparing a trenched substrate having trenches having a bottom exposing an oxide film; and an oxide film removal process of exposing the trenched substrate to a plasma, to remove the oxide film. The oxide film removal process includes a plurality of cycles, each cycle including: an oxide film etching step of etching the oxide film; and a cleaning step of removing an attached matter on inner walls of the trenches, after the oxide film etching step.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: June 14, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita
  • Patent number: 11359279
    Abstract: A cleaning method for dry cleaning a susceptor disposed in a process chamber of a film deposition apparatus is provided. In the method, a protective member is placed on a substrate receiving region provided in the susceptor. A cleaning gas is supplied to the susceptor having the protective member placed on the substrate receiving region, thereby removing a film deposited on a surface of the susceptor by etching.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: June 14, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Hitoshi Kato, Makoto Ishigo, Jun Sato
  • Patent number: 11355352
    Abstract: A plasma etching method for plasma-etching an object including an etching target film and a patterned mask. The plasma etching method includes a first step of plasma-etching the etching target film using the mask, and a second step of depositing a silicon-containing film using plasma of a silicon-containing gas on at least a part of a side wall of the etching target film etched by the first step.
    Type: Grant
    Filed: May 29, 2020
    Date of Patent: June 7, 2022
    Assignee: Tokyo Electron Limited
    Inventors: Keiji Kitagaito, Fumiya Kobayashi, Maju Tomura
  • Patent number: 11315788
    Abstract: A process of realizing a silicon micropattern having a large aspect ratio in a semiconductor-manufacturing process, and a novel wet etching method that includes treating an organic carbon film layer so that a hydrofluoric-acid-resistant material is selectively attached to the organic carbon film layer and then wet etching the same using an aqueous solution containing hydrofluoric acid, thus forming a pattern, are proposed. In the method of forming the pattern by wet etching, etching is performed so that an active region having a depth of several ?m in an object to be etched is not damaged when a pattern having a small CD is formed, thereby exhibiting an effect of providing a method of forming a micropattern.
    Type: Grant
    Filed: January 9, 2019
    Date of Patent: April 26, 2022
    Assignee: YOUNG CHANG CHEMICAL CO., LTD
    Inventors: Su Jin Lee, Gi Hong Kim, Seung Hun Lee
  • Patent number: 11316103
    Abstract: A process flow for forming magnetic tunnel junction (MTJ) nanopillars with minimal sidewall residue and minimal sidewall damage is disclosed wherein a pattern is first formed in a hard mask that is an uppermost MTJ layer. Thereafter, the hard mask sidewall is etch transferred through the remaining MTJ layers including a reference layer, free layer, and tunnel barrier between the free layer and reference layer. The etch transfer may be completed in a single RIE step that features a physical component involving inert gas ions or plasma, and a chemical component comprised of ions or plasma generated from one or more of methanol, ethanol, ammonia, and CO. In other embodiments, a chemical treatment with one of the aforementioned chemicals, and a volatilization at 50° C. to 450° C. may follow an etch transfer through the MTJ stack with an ion beam etch or plasma etch involving inert gas ions.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: April 26, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Dongna Shen, Yu-Jen Wang, Ru-Ying Tong, Vignesh Sundar, Sahil Patel
  • Patent number: 11295981
    Abstract: Disclosed are semiconductor devices including through vias and methods of fabricating the same. The methods may include forming a first structure including a metal pattern and a second structure on the first structure. The metal pattern includes an upper surface facing the second structure. The methods may also include etching the second structure to form a via hole exposing the metal pattern, oxidizing a first etch residue in the via hole to convert the first etch residue into an oxidized first etch residue, and removing the oxidized first etch residue. After removing the oxidized first etch residue, the upper surface of the metal pattern may include a first portion that includes a recess and has a first surface roughness and a second portion that is different from the first portion and has a second surface roughness. The first surface roughness may be greater than the second surface roughness.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: April 5, 2022
    Inventors: Yi Koan Hong, Taeseong Kim, Kwangjin Moon
  • Patent number: 11260433
    Abstract: There is provided a cleaning method of a substrate processing apparatus comprising cleaning an inside of an exhaust pipe through which a gas of an inside of a processing container is exhausted. The cleaning the inside of the exhaust pipe includes: removing a deposit on a downstream side of an opening/closing valve in the exhaust pipe by supplying a first exhaust pipe cleaning gas containing fluorine to the downstream side of the opening/closing valve in the exhaust pipe in a state in which the opening/closing valve provided in a middle of the exhaust pipe is closed; and removing a deposit on an upstream side of the opening/closing valve in the exhaust pipe by supplying a second exhaust pipe cleaning gas not containing fluorine as a gas constituent element to the inside of the processing container in a state in which the opening/closing valve is opened.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: March 1, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yoshihiro Takezawa, Daisuke Suzuki, Hiroyuki Hayashi, Sena Fujita, Tatsuya Miyahara, Jyunji Ariga, Shinya Kikuchi
  • Patent number: 11264247
    Abstract: According to one or more embodiments, a method for forming an etching mask includes forming a mask layer including a first organic material on a processing object, processing the mask layer to form a pattern including an opening, exposing the mask layer to a first oxidizing gas containing a first metal material such that the first metal material penetrates into the mask layer, and then exposing the mask layer to a first oxidizing gas including hydrogen peroxide or ozone to oxidize the first metal material.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: March 1, 2022
    Assignee: KIOXIA CORPORATION
    Inventor: Hironobu Sato
  • Patent number: 11232971
    Abstract: A workpiece holding mechanism, a process system and a manufacturing method of a semiconductor structure are provided. The workpiece holding mechanism is used in a vacuum chamber, and includes a stage, a platen and a workpiece clamper. The platen is disposed over the stage, and configured to support a workpiece. The workpiece clamper is standing on the stage, and configured to clamp the workpiece from above the workpiece. The workpiece clamper includes a plurality of supporting elements and an elevated structure. The supporting elements are connected between the stage and the elevated structure. The platen is surrounded by the supporting elements. The elevated structure is configured to physically contact a peripheral region of the workpiece from above the workpiece.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Jui Kuo, Hui-Jung Tsai, Keng-Han Lin
  • Patent number: 11227773
    Abstract: A method for controlling an electrostatic attractor, which attracts an electrode to a gas plate provided in an upper portion of a plasma processing apparatus, includes, among a plasma generation period in which plasma is generated by the plasma processing apparatus and an idle period in which no plasma is generated by the plasma processing apparatus, applying voltages having polarities different from each other to first and second electrodes of the electrostatic attractor in at least the idle period.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: January 18, 2022
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Gen Tamamushi
  • Patent number: 11221793
    Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages and an on-die data buffer coupled to the memory array on a same chip and configured to buffer a plurality of batches of program data between a host and the memory array. The on-die data buffer may include SRAM cells. The 3D memory device also includes a controller coupled to the on-die data buffer on the same chip. The controller may be configured to receive control instructions for performing a first pass program and a second pass program on memory cells in a page. The controller may also be configured to buffer, in the on-die data buffer, first program data for a first pass program and second program data for a second pass program from a host and retrieve the first program data from the on-die data buffer.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: January 11, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yue Ping Li, Wei Jun Wan, Chun Yuan Hou
  • Patent number: 11217487
    Abstract: A method for forming a semiconductor arrangement includes forming a first gate structure over a first active region. The first gate structure includes a first conductive layer. An etch process is performed using a process gas mixture to recess the first gate structure and define a recess. The etch process comprises a first phase to form a polymer layer over the first conductive layer and to modify a portion of the first conductive layer to form a modified portion of the first conductive layer and a second phase to remove the polymer layer and to remove the modified portion of the first conductive layer.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yi-Chen Lo, Li-Te Lin, Pinyen Lin
  • Patent number: 11205577
    Abstract: An etching method including: (a) providing a workpiece including a first region made of a first material and a second region made of a second material defining a recess, the first region filling the recess of the second region while covering the second region; (b) generating plasma of a first fluorocarbon gas to etch the first region until before exposing the second region; (c) generating plasma of a second fluorocarbon gas to form fluorocarbon deposits on the first region; (d) generating plasma of an inert gas to etch the first region by fluorocarbon radicals contained in the fluorocarbon deposits; and (e) repeating step (c) and step (d) one or more times until after exposing the second region. An etching rate of the first material of the first region is higher than that of the second material of the second region with respect to the second fluorocarbon gas.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: December 21, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Hikaru Watanabe, Akihiro Tsuji
  • Patent number: 11201038
    Abstract: A support assembly includes an electrostatic chuck, a lower electrode, one or more conductive members and a ring-shaped insulating member. The lower electrode has a chuck support surface which supports the electrostatic chuck and a ring support surface which supports an edge ring and surrounds the chuck support surface. A contact electrode is formed on the ring support surface. The conductive members electrically connect the contact electrode and the edge ring. The insulating member is interposed between the ring support surface of the lower electrode and the edge ring while enclosing the conductive members.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 14, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Takehiro Ueda
  • Patent number: 11189797
    Abstract: Provided are a display panel, a plasma etching method and a system. After patterning a metal film layer on a substrate with a chlorine-containing gas, a post-treatment for suppressing corrosion is implemented by using plasma containing an oxygen-containing gas and a hydrogen-fluoride-containing gas. Thus, the surface of the metal film layer is an aluminum ion-containing crystal, which solves the technical problem of corrosion of the aluminum layer in the plasma etching technology of the prior art.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: November 30, 2021
    Assignee: WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
    Inventor: Pengbin Zhang
  • Patent number: 11145493
    Abstract: A plasma etching apparatus includes a processing vessel, a stage, a gas supply, a first high frequency power supply, a second high frequency power supply and a control device. The stage is provided and configured to place thereon a substrate. The gas supply is configured to supply a processing gas. The first high frequency power supply is configured to supply a first high frequency power. The second high frequency power supply is configured to supply a second high frequency power to the stage. The control device controls a supply and a stop of the supply of each of the first and the second high frequency powers at every preset cycle. The first and the second high frequency powers are supplied exclusively. A ratio of a supply time with respect to a single cycle of the first high frequency power is lower than that of the second high frequency power.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: October 12, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Satoshi Tanaka
  • Patent number: 11120978
    Abstract: A system and method to increase surface friction across a hydrophobic, anti-fouling, and oleophobic coated substrate. The substrate has a hydrophobic surface defined by a surface friction. The system works to increases the surface friction, or roughness, across the hydrophobic surface. The increase in surface friction is accomplished by generating power through an ion source to create an ion cloud. The ion cloud is generated in proximity to the substrate. The ions interact with the hydrophobic surface to create a roughing effect thereon. A gas carrier device introduces an inert carrier gas through the ion cloud to increase density of the ions, which in turn increases surface friction. The system is variable, selectively increasing and decreasing surface friction by: varying the duration that the hydrophobic surface is exposed to the ion cloud; varying power applied to ion source; and varying distance between the ion cloud and the hydrophobic surface.
    Type: Grant
    Filed: November 5, 2019
    Date of Patent: September 14, 2021
    Assignee: QUANTUM INNOVATIONS, INC.
    Inventors: Norman L. Kester, Peter Voin, Danny Charles Gilkison, Philip H. Post, John B. Glarum
  • Patent number: 11062884
    Abstract: The present invention provides a plasma processing apparatus and a plasma processing method which improve the uniformity and accordingly the yield in an etching treatment of a sample.
    Type: Grant
    Filed: February 27, 2019
    Date of Patent: July 13, 2021
    Assignee: HITACHI HIGH-TECH CORPORATION
    Inventor: Yoshiyuki Hironaka
  • Patent number: 11056392
    Abstract: A method for forming a FinFET device is described. The method includes the following steps. A substrate is patterned to form fins. Dummy gate stack is formed on the substrate and over the fins, wherein the dummy gate stack may be formed by the following steps: a dummy layer is formed; a first etching step is performed on the dummy layer with a bromine containing etching gas to form a dummy strip; a second etching step is performed on the dummy strip with a chlorine containing etching gas to form the dummy gate stack. The dummy gate stack is replaced with a gate stack.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chien Li, Wei-Shuo Ho, Huang-Chao Chang, Wei-Zhe Jhang
  • Patent number: 11056317
    Abstract: A microwave plasma source that generates a microwave plasma in a processing space in which a target substrate is processed, includes: a microwave generation part for generating microwave; a waveguide through which the microwave generated by the microwave generation part propagates; an antenna part including a slot antenna having a predetermined pattern of slots formed therein and being configured to radiate the microwave propagating through the waveguide into the processing space and a microwave-transmitting plate being made of a dielectric material and being configured to transmit the microwave radiated from the slots therethrough and supply the microwave into the processing space; a temperature detector for detecting a temperature at a predetermined position in a microwave propagation path leading to the slot antenna; and an abnormality detection part for receiving the temperature detected by the temperature detector and detect an abnormality in the microwave propagation path based on the detected temperatu
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 6, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yasuaki Taniike
  • Patent number: 11043391
    Abstract: A method of etching silicon-containing film formed on an electrode layer of a floating potential is provided. The etching is performed in a processing vessel while supplying gas, a first high frequency electric power of a first frequency, and a second high frequency electric power of a second frequency less than the first frequency. The method includes a step of supplying, during etching of the silicon-containing film, the first high frequency electric power as a continuous wave and the second high frequency electric power as a pulse wave having a duty cycle of 20% or less, upon a distance from the electrode layer to a bottom of an etching pattern formed on the silicon-containing film becoming not more than a predetermined distance.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 22, 2021
    Assignee: Tokyo Electron Limited
    Inventor: Yusuke Saitoh
  • Patent number: 10998169
    Abstract: A method of plasma processing includes generating a first sequence of source power pulses, generating a second sequence of bias power pulses, combining the bias power pulses of the second sequence with the source power pulses of the first sequence to form a combined sequence of alternating source power pulses and bias power pulses, and, using the combined sequence, generating a plasma comprising ions and processing a substrate by delivering the ions to a major surface of the substrate.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 4, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Peter Ventzek, Zhiying Chen, Alok Ranjan
  • Patent number: 10964550
    Abstract: A method for surface planarization of an object using a light source of a specific wavelength according to an embodiment includes: providing an object in a main chamber; injecting an etching gas into the main chamber; inputting the light source of a specific wavelength onto a surface of the object; and controlling a temperature of the object. According to the method, it is possible to minimize the side effects such as scratches or contamination of the sample that occur in a conventional chemical-mechanical planarization process. In addition, it is possible to allow precise planarization in nanometers (nm) and simultaneously perform planarization to a side surface of a device as well as a large-sized surface, thereby reducing cost and time required for the planarization process. Moreover, since the surface roughness and the electrical conductivity are improved, it is possible to increase the efficiency and output of the LED device.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: March 30, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Gumin Kang, Il Ki Han, S. Joon Kwon, Young-Hwan Kim, Hyungduk Ko, Chun Keun Kim
  • Patent number: 10957533
    Abstract: Embodiments of the present disclosure provide methods and apparatus for forming and patterning features in a film stack disposed on a substrate. In one embodiment, a method for patterning a conductive layer on a substrate includes supplying a gas mixture comprising a chlorine containing gas at a first flow rate to etch a first conductive layer disposed on the substrate, lowing the chlorine containing gas in the first gas mixture to a second flow rate lower than the first flow rate to continue etching the first conductive layer, and increasing the chlorine containing gas in the first gas mixture to a third flow rate greater than the second flow rate to remove the first conductive layer from the substrate.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Hao Jiang, He Ren, Hao Chen, Mehul B. Naik
  • Patent number: 10950419
    Abstract: Shrouds and substrate treating systems including the same are provided. Substrate treating systems may include a process chamber, a supporter, and a plasma source that is spaced apart from the supporter in a vertical direction. The substrate treating systems may also include a shroud configured to contain the plasma therein. The shroud may include a sidewall portion and a first flange portion extending horizontally from the sidewall portion and including a plurality of first slits that extend through a thickness of the first flange portion. The first flange portion may define a first opening, and a portion of the supporter may extend through the first opening. The sidewall portion may include a plurality of second slits, and each of the plurality of second slits may extend through a thickness of the sidewall portion and may extend from one of the plurality of first slits toward the plasma source.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: March 16, 2021
    Inventors: Edward Sung, Hyuk Kim, Daehyun Jang, Sung Il Cho
  • Patent number: 10950458
    Abstract: An etching method is provided. The etching method is performed on a substrate having a first film to a third film. The third film is provided on an underlying region, the second film is provided on the third film, the first film is provided on the second film. The second film contains silicon and nitrogen. The first film to the third film are etched in sequence. Plasma of a processing gas containing fluorine and hydrogen is used in the etching of the first film to the third film. A temperature of the substrate is set to be equal to or less than 20° C. at least in the etching of the second film.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yasutaka Hama, Shinya Morikita, Kiyohito Ito
  • Patent number: 10950483
    Abstract: In an embodiment, a system includes: a base with a bore hole, wherein the base is configured to secure a wafer at a first position on the base; a pin extending through the bore hole; a focus ring horizontally surrounding the wafer at the first position and extending upwardly from the base, wherein the wafer is configured to be moved vertically between the first position and a second position above the focus ring via the pin; and a slit valve above the focus ring, wherein the wafer is configured to be moved horizontally between the second position and the slit valve via a robotic arm.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Lisng Tzeng, Chen-Chun Yan, Yao-Pin Yang
  • Patent number: 10944051
    Abstract: A method of cleaning a substrate processing apparatus that etches a film including a metal includes (a) providing an inert gas, and removing a metal-containing deposition by plasma generated from the inert gas; and (b) after (a), providing a gas containing a fluorine-containing gas and an oxygen-containing gas, and removing a silicon-containing deposition by plasma generated from the gas containing the fluorine-containing gas and the oxygen-containing gas.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: March 9, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Kubo, Song yun Kang, Keiichi Shimoda, Tetsuya Ohishi
  • Patent number: 10867777
    Abstract: A plasma processing method includes: plasma-processing a substrate placed on a surface of a placement table while causing a coolant of 0° C. or lower to flow through a coolant flow path formed inside the table; placing a dummy substrate on the surface of the placement table in place of the substrate; and removing a reaction product generated due to the plasma processing of the substrate by the plasma of the processing gas from a peripheral edge portion of the surface of the placement table while heating the surface of placement table by the plasma of the processing gas via the dummy substrate in a state where the dummy substrate is placed on the surface of the placement table.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 15, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Wataru Takayama, Muneyuki Omi, Rei Ibuka, Dai Igarashi, Takayuki Suzuki, Takahiro Murakami
  • Patent number: 10854773
    Abstract: A method of manufacturing a semiconductor light emitting device includes: forming an active layer of an aluminum gallium nitride (AlGaN)-based semiconductor material on an n-type clad layer of an n-type AlGaN-based semiconductor material; forming a p-type semiconductor layer on the active layer; dry-etching portions of the p-type semiconductor layer, the active layer, and the n-type clad layer so as to expose a partial region of the n-type clad layer; causing nitrogen atoms (N) to react with the partial region of the n-type clad layer exposed; and forming an n-side electrode on the partial region of the n-type clad layer that the nitrogen atoms are caused to react with.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 1, 2020
    Assignee: Nikkiso Co., Ltd.
    Inventors: Kazushige Igarashi, Noritaka Niwa, Tetsuhiko Inazu
  • Patent number: 10854448
    Abstract: A plasma sputtering device including one or a plurality of plasma generating devices each including an insulating tube having an expanding inner diameter and having a gas injection port formed in an end portion or a side portion thereof, a first electromagnet or a permanent magnet group which can apply a static magnetic field, and a high frequency antenna; a second electromagnet which is disposed in a region downstream of the plasma generating device(s) and which can form a curved magnetic force line structure; a target mechanism which includes a permanent magnet embedded therein and a cooling mechanism and which can apply a DC or high frequency voltage; a substrate stage facing the target mechanism; a second permanent magnet group around the substrate stage; and a heat insulating mechanism between a target material and the target mechanism.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 1, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kazunori Takahashi, Jun Fukushima, Akira Ando, Yasumasa Sasaki
  • Patent number: 10838297
    Abstract: A method of patterning a cylindrical tool, including providing a stamp including a base and a layer of solid state ionic conductor thereon, applying a negative of a predetermined pattern of features on a major surface of the solid state ionic conductor, providing a cylindrical tool having a metallic surface positioned proximate the stamp, and applying an electric field between the metallic surface and a cathode while moving the stamp against the metallic surface in rolling line contact so as to impart the predetermined pattern of features onto the metallic surface, wherein the cathode is either the base or a conductive element positioned adjacent to the base. The positive of the predetermined pattern of features may include a multiplicity of nano-sized features.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 17, 2020
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: James Zhu, Daniel M. Lentz, Karl K. Stensvad, David J. Tarnowski
  • Patent number: 10825656
    Abstract: Systems and methods for controlling directionality of ion flux at an edge region within a plasma chamber are described. One of the systems includes a radio frequency (RF) generator that is configured to generate an RF signal, an impedance matching circuit coupled to the RF generator for receiving the RF signal to generate a modified RF signal, and a plasma chamber. The plasma chamber includes an edge ring and a coupling ring located below the edge ring and coupled to the first impedance matching circuit to receive the modified RF signal. The coupling ring includes an electrode that generates a capacitance between the electrode and the edge ring to control the directionality of the ion flux upon receiving the modified RF signal.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 3, 2020
    Assignee: Lam Research Corporation
    Inventors: Michael C. Kellogg, Alexei Marakhtanov, John Patrick Holland, Zhigang Chen, Felix Kozakevich, Kenneth Lucchesi
  • Patent number: 10804120
    Abstract: A temperature controller of a plasma-processing apparatus including a heating unit and a cooling unit. The heating unit is configured to heat a liner on an inner surface of a plasma chamber in which a plasma is formed. The cooling unit is configured to cool the liner to controls a temperature of an upper electrode in the plasma chamber.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Moon Ha, Min-Kyu Sung, Seung-Hee Cho, Seong-Chul Choi, Kyung-Sun Kim, Sang-Ho Lee
  • Patent number: 10773282
    Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: September 15, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Brian J. Coppa, Deepak Vedhachalam, Francois C. Dassapa
  • Patent number: 10770539
    Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventors: Chunshan Yin, Cheong Min Hong, Yu Chen
  • Patent number: 10763126
    Abstract: An etching apparatus includes: a placement table serving as a lower electrode and configured to place a workpiece to be subjected to an etching processing thereon; a DC power supply configured to generate a negative DC voltage applied to the placement table; and a controller configured to: periodically apply a negative DC voltage to the placement table from the DC power supply when the etching processing on the workpiece placed on the placement table is initiated, and decrease a frequency of the negative DC voltage applied to the placement table with an elapse of processing time of the etching processing.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 1, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Nagami, Kazuya Nagaseki
  • Patent number: 10741406
    Abstract: Disclosed is a dry etching method for etching a laminated film of silicon oxide layers and silicon nitride layers on a substrate. The dry etching method includes providing a mask on the laminated film, generating a plasma from a dry etching agent and etching the laminated film by the plasma through the mask under a bias voltage of 500 V or higher to form a through hole in the laminated film vertically to the layers, wherein the dry etching agent contains at least C3H2F4, an unsaturated perfluorocarbon represented by CxFy and an oxidizing gas, and wherein a volume of the unsaturated perfluorocarbon contained in the dry etching agent is 0.1 to 10 times a volume of the C3H2F4 contained in the dry etching agent.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 11, 2020
    Assignee: Central Glass Company, Limited
    Inventors: Hiroyuki Oomori, Akifumi Yao
  • Patent number: 10741367
    Abstract: A method of processing a substrate is provided. The method includes loading a substrate in a processing chamber. The substrate is supported on a bottom electrode and the processing chamber includes a top electrode opposing the bottom electrode. The method includes placing a plasma containment structure over a selected portion of the surface of the substrate to define a plasma containment region of the selected portion of the surface of the substrate. Then, injecting at least one process gas into the plasma containment region and biasing the top electrode and the bottom electrode. The method further includes exhausting process byproducts from the plasma containment region and moving the plasma containment region relative to the substrate to selectively passes over the entire surface of the substrate.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 11, 2020
    Assignee: Lam Research Corporation
    Inventor: Eric Hudson
  • Patent number: 10727072
    Abstract: A method for fabrication of free standing mechanical and photonic structures is presented. A resist mask is applied to a bulk substrate. The bulk substrate is attached to a movable platform. The bulk substrate is exposed to an ion stream produced by a reactive ion beam etching source. The platform is moved relative to the ion stream to facilitate undercutting a portion of the bulk substrate otherwise shielded by the mask.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: July 28, 2020
    Assignee: President and Fellows of Harvard College
    Inventors: Haig Avedis Atikian, Marko Loncar
  • Patent number: 10692702
    Abstract: Disclosed is a substrate treating apparatus which includes a chamber, a support unit, a dielectric plate, a gas supplying unit, an antenna, and a heating unit. The chamber has a processing space therein, and an upper surface of the processing space is opened. The support unit is disposed in the chamber and supports a substrate. The dielectric plate is installed on the opened upper surface of the chamber to cover the opened upper surface. The gas supplying unit supplies a gas in the chamber. The antenna is disposed above the dielectric plate and creates plasma from the gas. The heating unit is disposed above the antenna and heats the dielectric plate.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: June 23, 2020
    Assignee: SEMES CO., LTD.
    Inventors: Hyung Joon Kim, Hyungchul Moon
  • Patent number: 10658174
    Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 19, 2020
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
  • Patent number: 10629467
    Abstract: An electrostatic chuck assembly includes a dielectric plate having an absorption electrode to generate an electrostatic force, the dielectric plate securing a substrate by the electrostatic force, a conductive base plate under the dielectric plate to be applied with a high frequency electric power, the conductive base plate being an electrode to generate plasma, and an insulating plate under the base plate, the insulating plate having an insulation body and an insulation sink, and the insulation sink having a dielectric constant lower than that of the insulation body.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ohyung Kwon, Kyung-Sun Kim, Jae-Hoon Kim, Doug-Yong Sung
  • Patent number: 10622219
    Abstract: A method and a system for monitoring a plasma chamber are provided. The method includes receiving process chamber characteristics from the plasma chamber; determining whether one or more variables associated with the process chamber characteristics are within predetermined specification. The method further includes updating a status of the plasma chamber to failure when the chamber characteristics are not within the predetermined specification. The method generates a warning notification when the chamber characteristics are within predetermined specification and when an operation status of the plasma chamber received from a fault detection system indicates a failure.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 14, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Jun Shinagawa
  • Patent number: 10600619
    Abstract: A plasma processing method in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: March 24, 2020
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yoshiharu Inoue, Tetsuo Ono, Michikazu Morimoto, Masaki Fujii, Masakazu Miyaji
  • Patent number: 10593783
    Abstract: In a processing method according to one exemplary embodiment, a first nitrified region of a workpiece is etched. The first nitrified region is provided on a first protrusion made of silicon. The workpiece further has a second protrusion, a second nitrified region, and an organic region. The second protrusion is made of silicon. The second nitrified region contains silicon and nitrogen and is provided on the second protrusion. The organic region covers the first and second protrusions and the first and second nitrified regions. In the processing method, the organic region is partially etched to expose the first nitrified region. Then, a silicon oxide film is formed to cover the surface of an intermediate product produced from the workpiece. Then, the silicon oxide film is etched to expose an upper surface of the first nitrified region. Then, the first nitrified region is isotropically etched.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: March 17, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Takino, Kentarou Fujita, Yusuke Yanagisawa
  • Patent number: 10559590
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Patent number: 10546748
    Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer is formed conformally over sidewalls and horizontal surfaces of protruding features on a substrate. A passivation layer is then formed over tin oxide on the sidewalls, and tin oxide is then removed from the horizontal surfaces of the protruding features without being removed at the sidewalls of the protruding features. The material of the protruding features is then removed while leaving the tin oxide that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers. Hydrogen-based and chlorine-based dry etch chemistries are used to selectively etch tin oxide in a presence of a variety of materials. In another method a patterned tin oxide hardmask layer is formed on a substrate by forming a patterned layer over an unpatterned tin oxide and transferring the pattern to the tin oxide.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Jengyi Yu, Samantha Tan, Yu Jiang, Hui-Jung Wu, Richard Wise, Yang Pan, Nader Shamma, Boris Volosskiy
  • Patent number: 10546768
    Abstract: An electrostatic chucking apparatus includes a movable member arranged for movement relative to an axial axis, at least one electrostatic chuck coupled to the movable member, and a stationary member. At least one moving insulated electrode is coupled to the movable member, and at least one stationary insulated electrode is coupled to the stationary member in an axial position corresponding to the at least one moving insulated electrode. A slip ring contact couples electrical energy from the at least one stationary insulated electrode to the at least one moving insulated electrode.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 28, 2020
    Assignee: Corning Incorporated
    Inventors: Daniel Robert Boughton, James Gerard Fagan, Valerie Elise Mebert