Using Plasma Patents (Class 216/67)
  • Patent number: 10998169
    Abstract: A method of plasma processing includes generating a first sequence of source power pulses, generating a second sequence of bias power pulses, combining the bias power pulses of the second sequence with the source power pulses of the first sequence to form a combined sequence of alternating source power pulses and bias power pulses, and, using the combined sequence, generating a plasma comprising ions and processing a substrate by delivering the ions to a major surface of the substrate.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: May 4, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Peter Ventzek, Zhiying Chen, Alok Ranjan
  • Patent number: 10964550
    Abstract: A method for surface planarization of an object using a light source of a specific wavelength according to an embodiment includes: providing an object in a main chamber; injecting an etching gas into the main chamber; inputting the light source of a specific wavelength onto a surface of the object; and controlling a temperature of the object. According to the method, it is possible to minimize the side effects such as scratches or contamination of the sample that occur in a conventional chemical-mechanical planarization process. In addition, it is possible to allow precise planarization in nanometers (nm) and simultaneously perform planarization to a side surface of a device as well as a large-sized surface, thereby reducing cost and time required for the planarization process. Moreover, since the surface roughness and the electrical conductivity are improved, it is possible to increase the efficiency and output of the LED device.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: March 30, 2021
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Gumin Kang, Il Ki Han, S. Joon Kwon, Young-Hwan Kim, Hyungduk Ko, Chun Keun Kim
  • Patent number: 10957533
    Abstract: Embodiments of the present disclosure provide methods and apparatus for forming and patterning features in a film stack disposed on a substrate. In one embodiment, a method for patterning a conductive layer on a substrate includes supplying a gas mixture comprising a chlorine containing gas at a first flow rate to etch a first conductive layer disposed on the substrate, lowing the chlorine containing gas in the first gas mixture to a second flow rate lower than the first flow rate to continue etching the first conductive layer, and increasing the chlorine containing gas in the first gas mixture to a third flow rate greater than the second flow rate to remove the first conductive layer from the substrate.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: March 23, 2021
    Assignee: Applied Materials, Inc.
    Inventors: Hao Jiang, He Ren, Hao Chen, Mehul B. Naik
  • Patent number: 10950458
    Abstract: An etching method is provided. The etching method is performed on a substrate having a first film to a third film. The third film is provided on an underlying region, the second film is provided on the third film, the first film is provided on the second film. The second film contains silicon and nitrogen. The first film to the third film are etched in sequence. Plasma of a processing gas containing fluorine and hydrogen is used in the etching of the first film to the third film. A temperature of the substrate is set to be equal to or less than 20° C. at least in the etching of the second film.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: March 16, 2021
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yasutaka Hama, Shinya Morikita, Kiyohito Ito
  • Patent number: 10950419
    Abstract: Shrouds and substrate treating systems including the same are provided. Substrate treating systems may include a process chamber, a supporter, and a plasma source that is spaced apart from the supporter in a vertical direction. The substrate treating systems may also include a shroud configured to contain the plasma therein. The shroud may include a sidewall portion and a first flange portion extending horizontally from the sidewall portion and including a plurality of first slits that extend through a thickness of the first flange portion. The first flange portion may define a first opening, and a portion of the supporter may extend through the first opening. The sidewall portion may include a plurality of second slits, and each of the plurality of second slits may extend through a thickness of the sidewall portion and may extend from one of the plurality of first slits toward the plasma source.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: March 16, 2021
    Inventors: Edward Sung, Hyuk Kim, Daehyun Jang, Sung Il Cho
  • Patent number: 10950483
    Abstract: In an embodiment, a system includes: a base with a bore hole, wherein the base is configured to secure a wafer at a first position on the base; a pin extending through the bore hole; a focus ring horizontally surrounding the wafer at the first position and extending upwardly from the base, wherein the wafer is configured to be moved vertically between the first position and a second position above the focus ring via the pin; and a slit valve above the focus ring, wherein the wafer is configured to be moved horizontally between the second position and the slit valve via a robotic arm.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huan-Lisng Tzeng, Chen-Chun Yan, Yao-Pin Yang
  • Patent number: 10944051
    Abstract: A method of cleaning a substrate processing apparatus that etches a film including a metal includes (a) providing an inert gas, and removing a metal-containing deposition by plasma generated from the inert gas; and (b) after (a), providing a gas containing a fluorine-containing gas and an oxygen-containing gas, and removing a silicon-containing deposition by plasma generated from the gas containing the fluorine-containing gas and the oxygen-containing gas.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: March 9, 2021
    Assignee: Tokyo Electron Limited
    Inventors: Takuya Kubo, Song yun Kang, Keiichi Shimoda, Tetsuya Ohishi
  • Patent number: 10867777
    Abstract: A plasma processing method includes: plasma-processing a substrate placed on a surface of a placement table while causing a coolant of 0° C. or lower to flow through a coolant flow path formed inside the table; placing a dummy substrate on the surface of the placement table in place of the substrate; and removing a reaction product generated due to the plasma processing of the substrate by the plasma of the processing gas from a peripheral edge portion of the surface of the placement table while heating the surface of placement table by the plasma of the processing gas via the dummy substrate in a state where the dummy substrate is placed on the surface of the placement table.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 15, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Wataru Takayama, Muneyuki Omi, Rei Ibuka, Dai Igarashi, Takayuki Suzuki, Takahiro Murakami
  • Patent number: 10854448
    Abstract: A plasma sputtering device including one or a plurality of plasma generating devices each including an insulating tube having an expanding inner diameter and having a gas injection port formed in an end portion or a side portion thereof, a first electromagnet or a permanent magnet group which can apply a static magnetic field, and a high frequency antenna; a second electromagnet which is disposed in a region downstream of the plasma generating device(s) and which can form a curved magnetic force line structure; a target mechanism which includes a permanent magnet embedded therein and a cooling mechanism and which can apply a DC or high frequency voltage; a substrate stage facing the target mechanism; a second permanent magnet group around the substrate stage; and a heat insulating mechanism between a target material and the target mechanism.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 1, 2020
    Assignee: TOHOKU UNIVERSITY
    Inventors: Kazunori Takahashi, Jun Fukushima, Akira Ando, Yasumasa Sasaki
  • Patent number: 10854773
    Abstract: A method of manufacturing a semiconductor light emitting device includes: forming an active layer of an aluminum gallium nitride (AlGaN)-based semiconductor material on an n-type clad layer of an n-type AlGaN-based semiconductor material; forming a p-type semiconductor layer on the active layer; dry-etching portions of the p-type semiconductor layer, the active layer, and the n-type clad layer so as to expose a partial region of the n-type clad layer; causing nitrogen atoms (N) to react with the partial region of the n-type clad layer exposed; and forming an n-side electrode on the partial region of the n-type clad layer that the nitrogen atoms are caused to react with.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: December 1, 2020
    Assignee: Nikkiso Co., Ltd.
    Inventors: Kazushige Igarashi, Noritaka Niwa, Tetsuhiko Inazu
  • Patent number: 10838297
    Abstract: A method of patterning a cylindrical tool, including providing a stamp including a base and a layer of solid state ionic conductor thereon, applying a negative of a predetermined pattern of features on a major surface of the solid state ionic conductor, providing a cylindrical tool having a metallic surface positioned proximate the stamp, and applying an electric field between the metallic surface and a cathode while moving the stamp against the metallic surface in rolling line contact so as to impart the predetermined pattern of features onto the metallic surface, wherein the cathode is either the base or a conductive element positioned adjacent to the base. The positive of the predetermined pattern of features may include a multiplicity of nano-sized features.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: November 17, 2020
    Assignee: 3M INNOVATIVE PROPERTIES COMPANY
    Inventors: James Zhu, Daniel M. Lentz, Karl K. Stensvad, David J. Tarnowski
  • Patent number: 10825656
    Abstract: Systems and methods for controlling directionality of ion flux at an edge region within a plasma chamber are described. One of the systems includes a radio frequency (RF) generator that is configured to generate an RF signal, an impedance matching circuit coupled to the RF generator for receiving the RF signal to generate a modified RF signal, and a plasma chamber. The plasma chamber includes an edge ring and a coupling ring located below the edge ring and coupled to the first impedance matching circuit to receive the modified RF signal. The coupling ring includes an electrode that generates a capacitance between the electrode and the edge ring to control the directionality of the ion flux upon receiving the modified RF signal.
    Type: Grant
    Filed: March 18, 2020
    Date of Patent: November 3, 2020
    Assignee: Lam Research Corporation
    Inventors: Michael C. Kellogg, Alexei Marakhtanov, John Patrick Holland, Zhigang Chen, Felix Kozakevich, Kenneth Lucchesi
  • Patent number: 10804120
    Abstract: A temperature controller of a plasma-processing apparatus including a heating unit and a cooling unit. The heating unit is configured to heat a liner on an inner surface of a plasma chamber in which a plasma is formed. The cooling unit is configured to cool the liner to controls a temperature of an upper electrode in the plasma chamber.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: October 13, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seong-Moon Ha, Min-Kyu Sung, Seung-Hee Cho, Seong-Chul Choi, Kyung-Sun Kim, Sang-Ho Lee
  • Patent number: 10773282
    Abstract: Described herein are architectures, platforms and methods for acquiring optical emission spectra from an optical emission spectroscopy system by flowing a dry cleaning gas into a plasma processing chamber of the plasma processing system and igniting a plasma in the plasma processing chamber to initiate the waferless dry cleaning process.
    Type: Grant
    Filed: March 24, 2017
    Date of Patent: September 15, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Brian J. Coppa, Deepak Vedhachalam, Francois C. Dassapa
  • Patent number: 10770539
    Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventors: Chunshan Yin, Cheong Min Hong, Yu Chen
  • Patent number: 10763126
    Abstract: An etching apparatus includes: a placement table serving as a lower electrode and configured to place a workpiece to be subjected to an etching processing thereon; a DC power supply configured to generate a negative DC voltage applied to the placement table; and a controller configured to: periodically apply a negative DC voltage to the placement table from the DC power supply when the etching processing on the workpiece placed on the placement table is initiated, and decrease a frequency of the negative DC voltage applied to the placement table with an elapse of processing time of the etching processing.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: September 1, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Koichi Nagami, Kazuya Nagaseki
  • Patent number: 10741367
    Abstract: A method of processing a substrate is provided. The method includes loading a substrate in a processing chamber. The substrate is supported on a bottom electrode and the processing chamber includes a top electrode opposing the bottom electrode. The method includes placing a plasma containment structure over a selected portion of the surface of the substrate to define a plasma containment region of the selected portion of the surface of the substrate. Then, injecting at least one process gas into the plasma containment region and biasing the top electrode and the bottom electrode. The method further includes exhausting process byproducts from the plasma containment region and moving the plasma containment region relative to the substrate to selectively passes over the entire surface of the substrate.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: August 11, 2020
    Assignee: Lam Research Corporation
    Inventor: Eric Hudson
  • Patent number: 10741406
    Abstract: Disclosed is a dry etching method for etching a laminated film of silicon oxide layers and silicon nitride layers on a substrate. The dry etching method includes providing a mask on the laminated film, generating a plasma from a dry etching agent and etching the laminated film by the plasma through the mask under a bias voltage of 500 V or higher to form a through hole in the laminated film vertically to the layers, wherein the dry etching agent contains at least C3H2F4, an unsaturated perfluorocarbon represented by CxFy and an oxidizing gas, and wherein a volume of the unsaturated perfluorocarbon contained in the dry etching agent is 0.1 to 10 times a volume of the C3H2F4 contained in the dry etching agent.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 11, 2020
    Assignee: Central Glass Company, Limited
    Inventors: Hiroyuki Oomori, Akifumi Yao
  • Patent number: 10727072
    Abstract: A method for fabrication of free standing mechanical and photonic structures is presented. A resist mask is applied to a bulk substrate. The bulk substrate is attached to a movable platform. The bulk substrate is exposed to an ion stream produced by a reactive ion beam etching source. The platform is moved relative to the ion stream to facilitate undercutting a portion of the bulk substrate otherwise shielded by the mask.
    Type: Grant
    Filed: May 13, 2016
    Date of Patent: July 28, 2020
    Assignee: President and Fellows of Harvard College
    Inventors: Haig Avedis Atikian, Marko Loncar
  • Patent number: 10692702
    Abstract: Disclosed is a substrate treating apparatus which includes a chamber, a support unit, a dielectric plate, a gas supplying unit, an antenna, and a heating unit. The chamber has a processing space therein, and an upper surface of the processing space is opened. The support unit is disposed in the chamber and supports a substrate. The dielectric plate is installed on the opened upper surface of the chamber to cover the opened upper surface. The gas supplying unit supplies a gas in the chamber. The antenna is disposed above the dielectric plate and creates plasma from the gas. The heating unit is disposed above the antenna and heats the dielectric plate.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: June 23, 2020
    Assignee: SEMES CO., LTD.
    Inventors: Hyung Joon Kim, Hyungchul Moon
  • Patent number: 10658174
    Abstract: Methods and apparatuses for reducing roughness using integrated atomic layer deposition (ALD) and etch processes are described herein. In some implementations, after a mask is provided on a substrate, methods include depositing a conformal layer on the mask by ALD to reduce roughness and etching a layer underlying the mask to form patterned features having a reduced roughness. In some implementations, after a substrate is etched to a first depth to form features at the first depth in the substrate, methods include depositing a conformal layer by ALD on sidewalls of the features to protect sidewalls and reduce roughness during a subsequent etch process. The ALD and etch processes may be performed in a plasma chamber.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: May 19, 2020
    Assignee: Lam Research Corporation
    Inventors: Xiang Zhou, Naveed Ansari, Yoshie Kimura, Si-Yi Yi Li, Kazi Sultana, Radhika Mani, Duming Zhang, Haseeb Kazi, Chen Xu, Mitchell Brooks, Ganesh Upadhyaya
  • Patent number: 10629467
    Abstract: An electrostatic chuck assembly includes a dielectric plate having an absorption electrode to generate an electrostatic force, the dielectric plate securing a substrate by the electrostatic force, a conductive base plate under the dielectric plate to be applied with a high frequency electric power, the conductive base plate being an electrode to generate plasma, and an insulating plate under the base plate, the insulating plate having an insulation body and an insulation sink, and the insulation sink having a dielectric constant lower than that of the insulation body.
    Type: Grant
    Filed: May 30, 2017
    Date of Patent: April 21, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ohyung Kwon, Kyung-Sun Kim, Jae-Hoon Kim, Doug-Yong Sung
  • Patent number: 10622219
    Abstract: A method and a system for monitoring a plasma chamber are provided. The method includes receiving process chamber characteristics from the plasma chamber; determining whether one or more variables associated with the process chamber characteristics are within predetermined specification. The method further includes updating a status of the plasma chamber to failure when the chamber characteristics are not within the predetermined specification. The method generates a warning notification when the chamber characteristics are within predetermined specification and when an operation status of the plasma chamber received from a fault detection system indicates a failure.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 14, 2020
    Assignee: Tokyo Electron Limited
    Inventor: Jun Shinagawa
  • Patent number: 10600619
    Abstract: A plasma processing method in which a stable process region can be ensured in a wide range, from low microwave power to high microwave power. The plasma processing method includes making production of plasma easy in a region in which production of plasma by continuous discharge is difficult, and plasma-processing an object to be processed, with the generated plasma, wherein the plasma is produced by pulsed discharge in which ON and OFF are repeated, radio-frequency power for producing the pulsed discharge, during an ON period, is a power to facilitate production of plasma by continuous discharge, and a duty ratio of the pulsed discharge is controlled so that an average power of the radio-frequency power per cycle is power in the region in which production of plasma by continuous discharge is difficult.
    Type: Grant
    Filed: April 6, 2016
    Date of Patent: March 24, 2020
    Assignee: HITACHI HIGH-TECHNOLOGIES CORPORATION
    Inventors: Yoshiharu Inoue, Tetsuo Ono, Michikazu Morimoto, Masaki Fujii, Masakazu Miyaji
  • Patent number: 10593783
    Abstract: In a processing method according to one exemplary embodiment, a first nitrified region of a workpiece is etched. The first nitrified region is provided on a first protrusion made of silicon. The workpiece further has a second protrusion, a second nitrified region, and an organic region. The second protrusion is made of silicon. The second nitrified region contains silicon and nitrogen and is provided on the second protrusion. The organic region covers the first and second protrusions and the first and second nitrified regions. In the processing method, the organic region is partially etched to expose the first nitrified region. Then, a silicon oxide film is formed to cover the surface of an intermediate product produced from the workpiece. Then, the silicon oxide film is etched to expose an upper surface of the first nitrified region. Then, the first nitrified region is isotropically etched.
    Type: Grant
    Filed: February 13, 2019
    Date of Patent: March 17, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Yusuke Takino, Kentarou Fujita, Yusuke Yanagisawa
  • Patent number: 10559590
    Abstract: A three-dimensional semiconductor device includes an upper structure on a lower structure, the upper structure including conductive patterns, a semiconductor pattern connected to the lower structure through the upper structure, and an insulating spacer between the semiconductor pattern and the upper structure, a bottom surface of the insulating spacer being positioned at a vertical level equivalent to or higher than an uppermost surface of the lower structure.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: February 11, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Changhyun Lee, Chanjin Park, Byoungkeun Son, Sung-Il Chang
  • Patent number: 10546748
    Abstract: Tin oxide films are used as spacers and hardmasks in semiconductor device manufacturing. In one method, tin oxide layer is formed conformally over sidewalls and horizontal surfaces of protruding features on a substrate. A passivation layer is then formed over tin oxide on the sidewalls, and tin oxide is then removed from the horizontal surfaces of the protruding features without being removed at the sidewalls of the protruding features. The material of the protruding features is then removed while leaving the tin oxide that resided at the sidewalls of the protruding features, thereby forming tin oxide spacers. Hydrogen-based and chlorine-based dry etch chemistries are used to selectively etch tin oxide in a presence of a variety of materials. In another method a patterned tin oxide hardmask layer is formed on a substrate by forming a patterned layer over an unpatterned tin oxide and transferring the pattern to the tin oxide.
    Type: Grant
    Filed: February 12, 2018
    Date of Patent: January 28, 2020
    Assignee: Lam Research Corporation
    Inventors: Jengyi Yu, Samantha Tan, Yu Jiang, Hui-Jung Wu, Richard Wise, Yang Pan, Nader Shamma, Boris Volosskiy
  • Patent number: 10546768
    Abstract: An electrostatic chucking apparatus includes a movable member arranged for movement relative to an axial axis, at least one electrostatic chuck coupled to the movable member, and a stationary member. At least one moving insulated electrode is coupled to the movable member, and at least one stationary insulated electrode is coupled to the stationary member in an axial position corresponding to the at least one moving insulated electrode. A slip ring contact couples electrical energy from the at least one stationary insulated electrode to the at least one moving insulated electrode.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: January 28, 2020
    Assignee: Corning Incorporated
    Inventors: Daniel Robert Boughton, James Gerard Fagan, Valerie Elise Mebert
  • Patent number: 10541250
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryohei Kitao, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
  • Patent number: 10529581
    Abstract: Methods for isotropic etching at least a portion of a silicon-containing layer on a sidewall of high-aspect-ratio (HAR) apertures formed on a substrate in a reaction chamber are disclosed. The HAR aperture formed by plasma etching a stack of alternating layers of a first silicon-containing layer and a second silicon-containing layer, the second silicon-containing layer is different from the first silicon-containing layer. The method comprising the steps of: a) introducing a fluorine containing etching gas selected from the group consisting of nitrosyl fluoride (FNO), trifluoroamine oxide (F3NO), nitryl fluoride (FNO2) and combinations thereof into the reaction chamber; and b) removing at least a portion of the second silicon-containing layers by selectively etching the second silicon-containing layers versus the first silicon-containing layers with the fluorine containing etching gas to produce recesses between the first silicon-containing layers on the sidewall of the HAR aperture.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 7, 2020
    Assignees: L'Air Liquide, Société Anonyme pour l'Etude et l'Exploitation des Procédés Georges Claude, Air Liquide Electronics U.S. LP
    Inventors: Chih-Yu Hsu, Peng Shen, Takashi Teramoto, Nathan Stafford, Jiro Yokota
  • Patent number: 10529633
    Abstract: A method of forming integrated circuit (IC) chips. After masking a layer of a material to be etched, the layer is subjected to an atomic layer etch (ALE). During the ALE, etch effluent is measured with a calorimetric probe. The calorimetric probe results reflect a species of particles resulting from etching the material. The measured etch results are checked until the results indicate the particle content is below a threshold value. When the content is below the threshold ALE is complete and IC chip fabrication continues normally.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: January 7, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sebastian U. Engelmann, Eric A. Joseph
  • Patent number: 10522429
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes the following operations. (a) A substrate is patterned. (b) A polymer layer is formed on the patterned substrate. (c) The polymer layer is patterned. Steps (a), (b) and (c) are repeated alternatingly. An intensity of an emission light generated by a reaction of a plasma and a product produced in steps (a), (b) and (c) is detected. An endpoint in patterning the substrate is determined according to the intensity of the emission light generated by the reaction of the plasma and the product produced in only one step of steps (a), (b) and (c). A sampling rate of the intensity is ranged from 1 pt/20 ms to 1 pt/100 ms. A smooth function is used to process the intensity of the emission light generated by the reaction of the plasma and the product.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: December 31, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Lee-Chuan Tseng, Chang-Ming Wu
  • Patent number: 10510512
    Abstract: Embodiments of method and system for controlling plasma performance are described. In an embodiment a method may include supplying power at a first set of power parameters to a plasma chamber. Additionally, the method may include forming plasma within the plasma chamber using the first set of power parameters. The method may also include measuring power coupling to the plasma at the first set of power parameters. Also, the method may include supplying power at a second set of power parameters to the plasma chamber. The method may additionally include measuring power coupling to the plasma at the second set of power parameters to the plasma. The method may also include adjusting the first set of power parameters based, at least in part, on the measuring of the power coupling at the second set of power parameters.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: December 17, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Merritt Funk, Megan Doppel, Kazuki Moyama, Chelsea DuBose, Justin Moses
  • Patent number: 10504699
    Abstract: Embodiments described herein include a modular high-frequency emission source comprising a plurality of high-frequency emission modules and a phase controller. In an embodiment, each high-frequency emission module comprises an oscillator module, an amplification module, and an applicator. In an embodiment, each oscillator module comprises a voltage control circuit and a voltage controlled oscillator. In an embodiment, each amplification module is coupled to an oscillator module, in an embodiment, each applicator is coupled to an amplification module. In an embodiment, the phase controller is communicatively coupled to each oscillator module.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: December 10, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Philip Allan Kraus, Thai Cheng Chua, Christian Amormino, Dmitry A. Dzilno
  • Patent number: 10488750
    Abstract: In a mask blank comprising a transparent substrate and a single layer or multilayer film formed thereon, the film is formed only on the front surface of the substrate, but not on the side surface, chamfer, front surface-chamfer boundary, and back surface-chamfer boundary. The mask blank contains few particle defects, especially the number of particle defects with a certain size is zero.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 26, 2019
    Assignee: SHIN-ETSU CHEMICAL CO., LTD.
    Inventors: Yukio Inazuki, Hideo Kaneko
  • Patent number: 10475704
    Abstract: In a plasma processing step that is used in the method of manufacturing the element chip for manufacturing a plurality of element chips by dividing a substrate having a plurality of element regions, the substrate is divided into element chips 10 by exposing the substrate to a first plasma. Therefore, element chips having a first surface, a second surface, and a side surface connecting the first surface and the second surface are held spaced from each other on a carrier. A protection film covering the element chip is formed only on the side surface and it is possible to suppress creep-up of a conductive material to the side surface in the mounting step by exposing the element chips to second plasma in which a mixed gas of fluorocarbon and helium is used as a raw material gas.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: November 12, 2019
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Atsushi Harikai, Shogo Okita, Noriyuki Matsubara, Mitsuru Hiroshima, Mitsuhiro Okune
  • Patent number: 10424460
    Abstract: A plasma source includes a ring plasma chamber, a primary winding around an exterior of the ring plasma chamber, multiple ferrites, wherein the ring plasma chamber passes through each of the ferrites and multiple plasma chamber outlets coupling the plasma chamber to a process chamber. Each one of the plasma chamber outlets having a respective plasma restriction. A system and method for generating a plasma are also described.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: September 24, 2019
    Assignee: Lam Research Corporation
    Inventors: Ali Shajii, Richard Gottscho, Souheil Benzerrouk, Andrew Cowe, Siddharth P. Nagarkatti, William R. Entley
  • Patent number: 10410877
    Abstract: An etching method for etching a silicon oxide film is provided that includes generating a plasma from a gas including a hydrogen-containing gas and a fluorine-containing gas using a high frequency power for plasma generation, and etching the silicon oxide film using the generated plasma. The fluorine-containing gas includes a hydrofluorocarbon gas, and the sticking coefficient of radicals generated from the hydrofluorocarbon gas is higher than the sticking coefficient of radicals generated from carbon tetrafluoride (CF4).
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: September 10, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Ryuichi Takashima, Taku Gohira, Yoshinobu Ooya
  • Patent number: 10410838
    Abstract: An apparatus (9) for plasma treating multiple containers. The apparatus includes a manifold (2) comprising at least a first chamber with multiple outlet openings and multiple hollow, electrically-conductive nozzles (10) for at least one of delivering or exhausting plasma-generating gas. The multiple hollow, electrically-conductive nozzles are connected to the multiple outlet openings and protrude from the manifold. A method of plasma treating multiple containers is also disclosed. The method includes providing a reactor system comprising an apparatus disclosed herein, inserting the multiple hollow, electrically-conductive nozzles into the multiple containers (30), evacuating the multiple containers, grounding the multiple hollow, electrically-conductive nozzles while applying radio frequency power to the multiple containers, providing a gas inside the containers, and generating a plasma. At least one of evacuating or providing the gas is carried out through the hollow, electrically-conductive nozzles.
    Type: Grant
    Filed: May 6, 2010
    Date of Patent: September 10, 2019
    Assignee: 3M Innovative Properties Company
    Inventors: Daniel R. Hanson, Moses M. David, David J. White, Jean A. Kelly, Todd D. Alband
  • Patent number: 10399723
    Abstract: A system includes a cold plasma applicator configured to couple directly to a container, wherein the cold plasma applicator is configured to generate a cold plasma within the container. A method includes operating a cold plasma applicator to generate a cold plasma to treat contents within a container, wherein the cold plasma applicator is configured to directly couple to the container, or the cold plasma applicator comprises a varying geometry application surface having a plurality of protruding electrode portions spaced apart from one another to define a plurality of intermediate recessed portions, or a combination thereof.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: September 3, 2019
    Assignee: PLASMOLOGY4, INC.
    Inventors: Emilia M. Kulaga, Steven A. Myers, Marc C. Jacofsky, Jeffrey I. Meyers
  • Patent number: 10395935
    Abstract: A plasma processing apparatus includes a plasma processing chamber processing a sample using plasma, a radio frequency power supply supplying radio frequency power for generating the plasma, a sample stage including an electrode electrostatically chucking the sample, mounting the sample thereon, a DC power supply applying DC voltage to the electrode, and a control device shifting the DC voltage previously set, in a negative direction by a first shift amount during discharge of the plasma, shifting the DC voltage having been shifted in the negative direction by the first shift amount, in a positive direction by a second shift amount after the discharge of the plasma. The first shift amount has a value changing potential over a surface of the sample to 0 V, upon shifting the DC voltage in the positive direction. The second shift amount has a value obtained based on a floating potential of the plasma.
    Type: Grant
    Filed: February 26, 2018
    Date of Patent: August 27, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Masaki Ishiguro, Masahiro Sumiya, Shigeru Shirayone, Kazuyuki Ikenaga, Tomoyuki Tamura
  • Patent number: 10361091
    Abstract: A method for etching features into a porous low-k dielectric etch layer is provided. A plurality of cycles is performed in a plasma processing chamber. Each cycle comprises a deposition phase and an activation phase. The deposition phase comprises flowing a deposition gas comprising a fluorocarbon and/or hydrofluorocarbon gas, creating a plasma in the plasma processing chamber using the deposition gas, depositing a fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the deposition gas. The activation phase comprises flowing an activation gas comprising a noble gas and a carbon etching additive, creating a plasma in the plasma processing chamber using the activation gas, providing an activation bias in the plasma processing chamber, wherein the activation bias causes the etching of the low-k dielectric layer, with consumption of the fluorocarbon or hydrofluorocarbon containing layer, and stopping the flow of the activation gas.
    Type: Grant
    Filed: May 31, 2017
    Date of Patent: July 23, 2019
    Assignee: Lam Research Corporation
    Inventors: Eric Hudson, Shashank Deshmukh, Sonny Li, Chia-Chun Wang, Prabhakara Gopaladasu, Zihao Ouyang
  • Patent number: 10347465
    Abstract: Embodiments of the present invention relate to apparatus for enhancing deposition rate and improving a plasma profile during plasma processing of a substrate. According to embodiments, the apparatus includes a tuning electrode disposed in a substrate support pedestal and electrically coupled to a variable capacitor. The capacitance is controlled to control the RF and resulting plasma coupling to the tuning electrode. The plasma profile and the resulting deposition rate and deposited film thickness across the substrate are correspondingly controlled by adjusting the capacitance and impedance at the tuning electrode.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: July 9, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Mohamad A. Ayoub, Jian J. Chen, Amit K. Bansal
  • Patent number: 10312101
    Abstract: A substrate processing method includes a fluorine-based gas supply step of supplying a fluorine-based gas into a processing chamber where a substrate having a silicon-based film is accommodated, a purge gas supply step of supplying a purge gas for discharging the supplied fluorine-based gas into the processing chamber. The substrate processing method further includes a nitrogen-based gas supply step of supplying a nitrogen-based gas into the processing chamber from which the fluorine-based gas has been discharged. In the substrate processing method, at least in the fluorine-based gas supply step and the purge gas supply step, a temperature of the substrate is maintained at 60° C. or less.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: June 4, 2019
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Shuji Moriya, Masahiko Tomita
  • Patent number: 10304692
    Abstract: A method of forming field effect transistor (FET) circuits, and forming Integrated Circuit (IC) chips with the FET circuits. After forming gate sidewall spacers, filling with insulation and planarizing to the top of the sidewall spacers, self-aligned source/drain contacts are etched through the insulation and said gate dielectric layer to source/drain regions. A combination fluoroether/hydrofluoroether-hydrofluorocarbon (*FE-HFC) plasma etch etches the source/drain contacts self-aligned. The self-aligned contacts are filled with conductive material, and FETs are wired together into circuits, connecting to FETs through the self-aligned contacts.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 28, 2019
    Assignee: International Business Machines Corporation
    Inventors: John C. Arnold, Robert L. Bruce, Sebastian U. Engelmann, Nathan P. Marchack, Hiroyuki Miyazoe, Jeffrey C. Shearer, Takefumi Suzuki
  • Patent number: 10290506
    Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).
    Type: Grant
    Filed: February 13, 2017
    Date of Patent: May 14, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Alok Ranjan, Akiteru Ko
  • Patent number: 10217611
    Abstract: A plasma processing apparatus or a plasma processing method that processes a wafer to be processed, which is placed on a surface of a sample stage arranged in a processing chamber inside a vacuum container, using a plasma formed in the processing chamber, the apparatus or method including processing the wafer by adjusting a first high-frequency power to be supplied to a first electrode arranged inside the sample stage and a second high-frequency power to be supplied, via a resonant circuit, to a second electrode which is arranged in an inner side of a ring-shaped member made of a dielectric arranged on an outer peripheral side of a surface of the sample stage on which the wafer is placed, during the processing.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: February 26, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Tooru Aramaki, Kenetsu Yokogawa, Masaru Izawa
  • Patent number: 10211153
    Abstract: A low aspect ratio interconnect is provided and includes a metallization layer, a liner and a metallic interconnect. The metallization layer includes bottommost and uppermost surfaces. The uppermost surface has a maximum post-deposition height from the bottommost surface at first metallization layer portions. The metallization layer defines a trench at second metallization layer portions. The liner includes is disposed to line the trench and includes liner sidewalls that have terminal edges that extend to the maximum post-deposition height and lie coplanar with the uppermost surface at the first metallization layer portions. The metallic interconnect is disposed on the liner to fill a trench remainder and has an uppermost interconnect surface that extends to the maximum post-deposition height and lies coplanar with the uppermost surface at the first metallization layer portions.
    Type: Grant
    Filed: August 30, 2016
    Date of Patent: February 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Benjamin D. Briggs, Elbert E. Huang, Raghuveer R. Patlolla, Cornelius Brown Peethala, David L. Rath, Chih-Chao Yang
  • Patent number: 10186428
    Abstract: Exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. Methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The methods may also include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region, and the substrate may include a region of exposed oxide. Methods may also include providing a hydrogen-containing precursor to the processing region. The methods may further include removing at least a portion of the exposed oxide while maintaining a relative humidity within the processing region below about 50%. Subsequent to the removal, the methods may include increasing the relative humidity within the processing region to greater than or about 50%. The methods may further include removing an additional amount of the exposed oxide.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: January 22, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Lin Xu, Zhijun Chen, Jiayin Huang, Anchuan Wang
  • Patent number: 10163610
    Abstract: An edge ring assembly for a plasma processing chamber is provided, including: an edge ring configured to surround an electrostatic chuck (ESC) that is configured for electrical connection to a first RF power supply, the ESC having a top surface for supporting a substrate and an annular step surrounding the top surface, the annular step defining an annular shelf that is lower than the top surface; an annular electrode disposed below the edge ring in the annular step and above the annular shelf; a dielectric ring disposed below the annular electrode for isolating the annular electrode from the ESC, the dielectric ring positioned in the annular step over the annular shelf; and, a plurality of insulated connectors disposed through the ESC and through the dielectric ring, each of the plurality of insulated connectors providing electrical connection between a second RF power supply and the annular electrode.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: December 25, 2018
    Assignee: Lam Research Corporation
    Inventors: Saravanapriyan Sriraman, Tom A. Kamp, Alexander Paterson