Abstract: Disclosed is a process for plasma etching a mask patterned dielectric film to form vias on a semiconductor wafer, so that the resulting etched structure is devoid of residues on the walls of the structure. A via is an opening through a dielectric material through which a point of contact of underlying metal with a metal film deposited over the dielectric is made. The underlying metal, when exposed to plasma, has a tendency to sputter onto the vertical wall portions of the contact via structures. The metal-containing sputtered material forms a residue that essentially cannot be removed in the subsequent photoresist stripping process typically used in semiconductor manufacturing. The plasma etch process in accordance with the invention enables removal of the sputtered metal by utilizing with the basic dielectric etch gases a gas that reacts with the metal to form volatile compounds which are readily evacuable.

Abstract: A process for dry etching a copper containing film formed on a substrate is performed by using an etching gas while heating at a temperature below 200.degree. C. The etching gas is selectable from the group consisting of a mixed gas of a N containing gas, an O containing gas, a N and O containing gas, or a mixed gas of a N containing gas, an O containing gas and a F containing gas, or a mixed gas of a N and O containing gas and a F containing gas. By this etching gas, Cu(NO.sub.3).sub.2 is formed to be sublimed.

Abstract: A process for an improved solder terminal is disclosed. The improved solder terminal is made of a bottom metallic adhesion layer, a CrCu intermediate layer on top of the adhesion layer, a solder bonding layer above the CrCu layer and a solder top layer. The adhesion layer is either TiW or TiN. A process for fabricating an improved terminal metal consists of depositing an adhesive metallic layer, a layer of CrCu over the adhesive layer and a layer of solder bonding material, over which a solder layer is formed in selective regions and the underlying layers are etched using solder regions as a mask.

Abstract: A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped.A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained an S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.

Abstract: A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped. A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained a S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.

Abstract: A method of etching openings in oxide layers is disclosed. A hard mask layer is formed on the oxide layer. The hard mask layer is then patterned by a photoresist layer and an etch is performed to form openings in the hard mask. Next, the patterning layer may be removed and an etch is performed to remove the oxide in the regions defined by the hard mask layer openings. The etch with hard mask has minimized aspect ratio dependency, so that openings of different sizes may be formed simultaneously. An etch that may be carried out with Freon 134a (C.sub.2 H.sub.2 F.sub.4) to provide superior oxide:nitride selectivity is also disclosed. Additionally, the etch may be carried out at high temperature for improved wall profile without loss of selectivity. For deep openings, a two step etch process is disclosed, with a polymer clean step between the etches to remove polymer build up from first etch, and allow the etch to proceed to an increased depth.

Abstract: A signal line structure for TFT-LCD and a method for fabricating the same are disclosed. The method comprises the steps of: forming a first metal and a second metal, in due order, on a glass substrate; defining the width (W.sub.1) of the second metal and subsequently, applying an etching process to the second metal; and depositing a third metal entirely on the resulting structure and defining the width (W.sub.2) of signal line so as to simultaneously remove the unnecessary portions of the first metal and said third metal. The signal line structure fabricated by the method is structured to comprise an insulating substrate; a first metal formed on the insulating substrate, having a good adhesiveness to said insulating substrate; a second metal formed on the first metal, having a low resistance; a third metal comprised of the same material that the first metal is, the third metal together with the first metal surrounding the second metal to prevent the oxidation of said second metal.

Abstract: Manufacturing techniques for forming waveguide channels and devices. A trench is formed in a cladding layer through an opening in a conductive layer. The trench is then filled with an active waveguide polymer and the conductive layer is patterned such that the active waveguide polymer may be poled. Also, a trench may be isotropically etched through a cladding layer to an underlying etch stop layer. The etch stop layer is thereafter removed from within the trench region to expose a previously formed, smooth, underlying cladding layer. Finally, a waveguide formed in a cladding layer, bounded in width by an overlying barrier layer, underlies a masking layer having a gap formed therein. Within the gap, a portion of the waveguide channel along with juxtaposing sections of the barrier layer are exposed. An etch is thereafter performed to remove the portion of the waveguide polymer in the waveguide channel bounded by both the masking layer and the barrier layer.

Abstract: A subtractive method for making a Levenson type lithographic phase shift mask using a sacrificial etch monitor film in which some of the monitor film is left standing on the opaque portions of the mask. The monitor film otherwise is consumed when it is simultaneously etched with selected portions of the mask substrate to produce recesses of desired depth in the substrate. The etching is stopped upon detecting that the etched monitor film is completely consumed. The technique also is adapted for the fabrication of a RIM type lithographic phase shift mask combined with the Levenson type phase shift mask in the same mask. The technique further is adapted to include 90 degree shift transitions at the end of the Levenson line-space pairs of the mask. The monitor film left standing on the opaque portions of the mask provides self-aligned phase error correction to offset sidewall scattering in the Levenson type mask.

Abstract: The method comprises the steps of providing a substrate wafer (10); depositing a first layer of resist (12) upon the substrate wafer (10); removing selected areas of the first resist layer (12), thereby to provide first etch windows; forming first cavities (16) in the substrate wafer (10) by a first etching process through the first windows; bonding a relatively thick membrane wafer (24) to the substrate wafer (10), thereby covering the cavities (16); polishing the surface of the relatively thick membrane wafer (24) thereby to produce a relatively thin membrane (24a); depositing a second layer of resist (33) on the relatively thin membrane (24a); removing selected areas of the second deposited resist layer, thereby to provide second etch windows (40); etching away the relatively thin membrane (24a) in the region of the second etch windows (40) until the first cavities (16) are exposed, thereby to form in the relatively thin membrane (24a) a free standing resonator structure (18 ) suspended on a plurality of c