Substrate Contains Elemental Metal, Alloy Thereof, Or Metal Compound Patents (Class 216/75)
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Patent number: 6726829Abstract: Disclosed herewithin is an apparatus for fabricating a stent which involves processing a tubular member whereby no connection points to join the edges of a flat pattern are necessary. The process includes the steps of: a) preparing the surface of a tubular member, b) coating the outside surface of the tubular member with a photo-sensitive resist material, c) placing the tubular member in an apparatus designed to simultaneously rotate the tubular member while passing a specially configured photographic frame negative between a light source and the tubular member, d) exposing the tubular member to a photoresist developer, e) rinsing the excess developer and uncured resist from the exposed tubular member, f) sealing the inner lumen of the tubular member, and g) treating the tubular member with a chemical or electro-chemical process to remove uncovered metal. By modifying the photographic negative, this process can be employed to fabricate a virtually unlimited number of stent designs and configurations.Type: GrantFiled: November 1, 2001Date of Patent: April 27, 2004Assignee: SciMed Life Systems, Inc.Inventor: Thomas Trozera
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Patent number: 6723252Abstract: The present invention includes a two-step etching process for notching the P1 pole of the write head element of a magnetic head. In a first step, the preferred embodiment utilizes a combination of C2F6 and argon gases (designated as C2F6/Ar) as the etchant gas to preferentially etch portions of the alumna write gap layer. Thereafter, in the second step, argon is used as the etchant gas to preferentially etch the P1 pole material. The C2F6/Ar etchant gas preferably includes C2F6 gas in a concentration range of from 50% to 90%, with a preferred concentration range being from 70% to 80%. The etching of the alumna write gap layer is preferably conducted with a first echant ion beam angle of from 5° to 30°, and a second etchant ion beam angle of from 65° to 85°.Type: GrantFiled: June 16, 2000Date of Patent: April 20, 2004Assignee: International Business Machines CorporationInventors: Richard Hsiao, John I. Kim
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Patent number: 6720659Abstract: Insulating films 21 through 24 of CF films (fluorine-contained carbon films) are formed on a substrate (not shown). In addition, Cu wiring layers 25 and 26 are formed on the CF films 21 and 23 via an adhesion layer 29 which comprises a Ti layer and a TiC layer. By forming the insulating films 21 through 24 of CF films, Cu in the wiring layers is prevented from diffusing into the insulating films 21 through 24. The relative dielectric constant of the CF film is smaller than the relative dielectric constant of a BCB film.Type: GrantFiled: September 12, 2000Date of Patent: April 13, 2004Assignee: Tokyo Electron LimitedInventor: Takashi Akahori
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Patent number: 6709609Abstract: We have discovered a method of reducing the effect of material sputtered/etched during the preheating of a substrate. One embodiment of the method pertains to preheating a substrate which includes a metal-containing layer which is to be pattern etched subsequent to preheating. The method includes exposing the substrate to a preheating plasma which produces a deposit or residue during preheating which is more easily etched than said metal-containing layer during the subsequent plasma etching of said metal-containing layer.Type: GrantFiled: December 22, 2000Date of Patent: March 23, 2004Assignee: Applied Materials Inc.Inventors: Jeng H. Hwang, Xiaoyi Chen
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Patent number: 6709610Abstract: A method for removing from a microelectronic device structure a noble metal residue including at least one metal selected from the group consisting of platinum, palladium, iridium and rhodium, by contacting the microelectronic device structure with a cleaning gas including a reactive halide composition, e.g., XeF2, SF6, SiF4, Si2F6 or SiF3 and SiF2 radicals. The method may be carried out in a batch-cleaning mode, in which fresh charges of cleaning gas are successively introduced to a chamber containing the residue-bearing microelectronic device structure. Each charge is purged from the chamber after reaction with the residue, and the charging/purging is continued until the residue has been at least partially removed to a desired extent. Alternatively, the cleaning gas may be continuously flowed through the chamber containing the microelectronic device structure, until the noble metal residue has been sufficiently removed.Type: GrantFiled: January 24, 2001Date of Patent: March 23, 2004Assignee: Advanced Technology Materials, Inc.Inventors: Peter C. Van Buskirk, Frank DiMeo, Jr., Peter S. Kirlin, Thomas H. Baum
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Patent number: 6706465Abstract: A substrate with a negative type photoresist applied rotates and is continuously subjected to surface exposure, heating, and developing/etching/removing the resist each in a dry process. As a result, signal projections are formed onto the surface, which is machined to a stamper size.Type: GrantFiled: August 3, 2000Date of Patent: March 16, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Kazuhiko Sano
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Patent number: 6692648Abstract: We have discovered a method of reducing the effect of material sputtered/etched during the preheating of a substrate. One embodiment of the method pertains to the preheating of a substrate which includes a material which is to be pattern etched at a temperature in excess of 150° C. The method comprises exposing the substrate to a preheating plasma generated from a plasma source gas which includes a reactive gas that aids in the production of a sputtered/etched residue during the preheating which is more easily etched during a subsequent pattern etching step than the material which is being pattern etched. In another embodiment of the method, the reactive gas in the preheating plasma source gas is slightly reactive with the material which is to etched during the subsequent pattern etching step.Type: GrantFiled: December 22, 2000Date of Patent: February 17, 2004Assignee: Applied Materials Inc.Inventors: Jeng H. Hwang, Xiaoyi Chen
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Patent number: 6689283Abstract: A dry etching is performed using a mask made of a titanium nitride under a reaction gas of a carbon monoxide with an additive of a nitrogen containing compound gas.Type: GrantFiled: March 26, 2001Date of Patent: February 10, 2004Assignee: TDK CorporationInventors: Kazuhiro Hattori, Kenji Uchiyama
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Patent number: 6685848Abstract: A dry-etching method comprises the step of dry-etching a metal thin film as a chromium-containing half-tone phase-shift film, wherein the method is characterized by using, as an etching gas, a mixed gas including (a) a reactive ion etching gas, which contains an oxygen-containing gas and a halogen-containing gas, and (b) a reducing gas added to the gas component (a), in the process for dry-etching the metal thin film. The dry-etching method permits the production of a half-tone phase-shift photomask by forming patterns to be transferred to a wafer on a photomask blank for a chromium-containing half-tone phase-shift mask. The photomask can in turn be used for manufacturing semiconductor circuits. The method permits the decrease of the dimensional difference due to the coexistence of coarse and dense patterns in a plane and the production of a high precision pattern-etched product.Type: GrantFiled: July 27, 1999Date of Patent: February 3, 2004Assignees: Ulvac Coating Corporation, Mitsubishi Denki Kabushiki KaishaInventors: Takaei Sasaki, Noriyuki Harashima, Satoshi Aoyama, Shouichi Sakamoto
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Publication number: 20040007246Abstract: A method and system for cleaning collector optics in a light source chamber. In producing, for example, extreme ultraviolet light for lithography, debris such as tungsten can accumulate on optical components near a light source in the light source chamber.Type: ApplicationFiled: July 15, 2002Publication date: January 15, 2004Inventors: Michael Chan, Robert Bristol, Mark Doczy
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Patent number: 6676843Abstract: A method for magnetic patterning of conductors includes imparting a pattern of magnetization into a magnetic material and depositing a substance onto the magnetic material that preferentially gathers according to the pattern in the magnetic material. A set of conductors are then formed such that the substance controls a pattern for the conductors.Type: GrantFiled: April 26, 2001Date of Patent: January 13, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventor: Richard H Henze
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Patent number: 6666983Abstract: The present invention is directed to an article with a patterned appearance provided by a visually observable contrast between one or more genereally transparent thin film coatings deposited over a substrate. At least one of the deposited coatings exhibits a reflected color and/or contrast and visible differing transmitted color and/or contrast or a plurality of coatings together exhibit different reflected colors and/or contrasts. The coatings are selected from the group of: metals depositable by magnetron sputtering vacuum deposition, chemical vapor deposition, pyrolytic coating, or sol-gel techniques, metal oxide coatings, metal nitride coatings, semi-conductor containing coatings, metal oxynitrides and mixtures thereof. The present invention is also directed to a method of making the articles having a visually observable patterned appearance involving masking and applying the coating or applying the coating and removing a portion of the coating to form the pattern.Type: GrantFiled: October 3, 2002Date of Patent: December 23, 2003Assignee: PPG Industries Ohio, Inc.Inventors: Gary J. Marietti, Mehran Arbab, James J. Finley
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Patent number: 6663786Abstract: Embedded flush circuitry features are provided by depositing a conductive seed layer on the front side of a sacrificial carrier; plating a layer of conductive metal onto the seed layer and personalizing circuitry features. The front side of the carrier film is embedded into a dielectric material and the sacrificial carrier film is removed.Type: GrantFiled: June 14, 2001Date of Patent: December 16, 2003Assignee: International Business Machines CorporationInventors: Robert Douglas Edwards, Jeffrey Alan Knight, Allen Frederick Moring, James W. Wilson
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Patent number: 6660406Abstract: There are provided an electrodeposited copper foil with carrier that can be used for manufacturing a printed wiring board that excels in the finished accuracy of the resistor circuit in comparison with a conventional printed wiring board with resistor circuits, and a method for manufacturing such a printed wiring board with resistor circuits.Type: GrantFiled: June 20, 2001Date of Patent: December 9, 2003Assignee: Mitsui Mining & Smelting Co., Ltd.Inventors: Takuya Yamamoto, Takashi Kataoka, Naotomi Takahashi
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Patent number: 6660647Abstract: A surface processing method of a sample having a mask layer that does not contain carbon as a major component formed on a substance to be processed, the substance being a metal, semiconductor and insulator deposited on a silicon substrate, includes the steps of installing the sample on a sample board in a vacuum container, generating a plasma that consists of a mixture of halogen gas and adhesive gas inside the vacuum container, applying a radio frequency bias voltage having a frequency ranging from 200 kHz to 20 MHz on the sample board, and controlling a periodic on-off of the radio frequency bias voltage with an on-off control frequency ranging from 100 Hz to 10 kHz.Type: GrantFiled: January 11, 2001Date of Patent: December 9, 2003Assignee: Hitachi, Ltd.Inventors: Tetsuo Ono, Takafumi Tokunaga, Tadashi Umezawa, Motohiko Yoshigai, Tatsumi Mizutani, Tokuo Kure, Masayuki Kojima, Takashi Sato, Yasushi Goto
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Patent number: 6656372Abstract: The invention includes methods of forming magnetoresistive devices. In one method, a construction is formed which includes a first magnetic layer, a non-magnetic layer over the first magnetic layer, and a second magnetic layer over the non-magnetic layer. A first pattern is extended through the second magnetic layer and to the non-magnetic layer with an etch selective for the material of the second magnetic layer relative to the material of the non-magnetic layer. A dielectric material is formed over the patterned second magnetic layer, and subsequently a second etch is utilized to extend a second pattern through the non-magnetic layer and at least partway into the first magnetic layer.Type: GrantFiled: October 4, 2001Date of Patent: December 2, 2003Assignee: Micron Technology, Inc.Inventor: Donald L. Yates
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Patent number: 6656376Abstract: A cleaning process for cleaning CVD units is disclosed. In the cleaning process, alkaline earth metal and/or metal-containing process residues, which form an amorphous film on reactor walls, are removed using a dry etching medium containing free diketones at a greatly reduced pressure and an elevated temperature. In the process, the free diketones react with the alkaline earth metals or metals to form volatile complexes.Type: GrantFiled: July 26, 1999Date of Patent: December 2, 2003Assignee: Siemens AktiengesellschaftInventors: Elke Fritsch, Christine Dehm, Hermann Wendt, Volker Weinrich
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Publication number: 20030205553Abstract: Ruthenium, osmium and their oxides can be etched simply and rapidly by supplying an atomic oxygen-donating gas, typically ozone, to the aforementioned metals and their oxides through catalysis between the metals and their oxides, and the ozone without any damages to wafers and reactors and application of the catalysis not only to the etching but also to chamber cleaning ensures stable operation of reactors and production of high quality devices.Type: ApplicationFiled: June 13, 2003Publication date: November 6, 2003Inventors: Miwako Nakahara, Toshiyuki Arai, Shigeru Ohno, Takashi Yunogami, Sukeyoshi Tsunekawa, Kazuto Watanabe
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Publication number: 20030205556Abstract: A process to form a capillary that is well insulated from its environment is described. Said process has two stages. The first stage, which is the same for both of the invention's two embodiments, comprises forming a micro-channel in the surface of a sheet of glassy material. For the first embodiment, this sheet is bonded to a layer of oxide, that lies on the surface of a sheet of silicon, thereby sealing in the capillary. After all silicon has been selectively removed, a thin membrane of oxide remains. Using a low temperature bonding process, a second sheet of glassy material is then bonded to this membrane. In the second embodiment, the silicon is not fully removed. Instead, the oxide layer of the first embodiment is replaced by an oxide/nitride/oxide trilayer which provides improved electrical insulation between the capillary and the remaining silicon at a lower level of inter-layer stress.Type: ApplicationFiled: May 2, 2002Publication date: November 6, 2003Applicant: Institute of MicroelectronicsInventors: Yu Chen, Janak Singh
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Patent number: 6630402Abstract: In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded comers which are believed to reduce the stresses transferred to a surrounding dielectric layer.Type: GrantFiled: November 21, 2001Date of Patent: October 7, 2003Assignee: General Semiconductor, Inc.Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato
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Patent number: 6623653Abstract: A method has been provided for etching adjoining layers of indium tin oxide (ITO) and silicon in a single, continuous dry etching process. A conventional dry etching gas, such as HI, is used to etch ITO using RF or plasma energy. When the silicon layer underlying the ITO layer is reached, oxygen or nitrogen is added to etching gas to improve the selectivity of ITO to silicon. In some aspects of the invention an etch-stop layer is formed in the silicon layer. A specific example of fabricating a bottom gate thin film transistor (TFT) is also provided where adjoining layers of source metal, ITO, and channel silicon are etched in the same dry etch step.Type: GrantFiled: June 12, 2001Date of Patent: September 23, 2003Assignee: Sharp Laboratories of America, Inc.Inventors: Gaku Furuta, Apostolos Voutsas
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Publication number: 20030173333Abstract: A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF6 and Ar, the volumetric flow ratio of SF6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF4 and Ar, the volumetric flow ratio of CF4 to other components of the second process gas being from about 1:0 to about 1:10.Type: ApplicationFiled: February 3, 2003Publication date: September 18, 2003Applicant: Applied Materials, Inc.Inventors: Xikun Wang, Scott Williams, Shaoher X. Pan
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Patent number: 6613243Abstract: A method of producing surface features in a substrate includes steps of forming a film having a composition that varies in the direction of its thickness on the substrate, forming a mask on the heterogeneous film, etching the film to thereby pattern the film, and etching the structure that includes the patterned film to erode the film and correspondingly shape the substrate as the film is so being eroded. In this way, the pattern of the film is transferred to the substrate in a manner dependent on the selectivity of one or both of the etching processes as well as the thickness of the discrete mask layers, or in the case of a continuously graded film, the “slope” of the stoichiometric change with respect to position in the overall thickness of the film.Type: GrantFiled: July 25, 2001Date of Patent: September 2, 2003Assignee: Shipley Company, L.L.C.Inventor: Neal Ricks
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Patent number: 6608250Abstract: A thermoelectric device with improved efficiency is provided. In one embodiment, the thermoelectric device includes an electrical conductor thermally coupled to a cold plate and a thermoelement electrically coupled to the electrical conductor. The thermoelement is constructed from a thermoelectric material and has a plurality of tips through which the thermoelement is electrically coupled to the electrical conductor. The thermoelectric tips provide a low resistive connection while minimizing thermal conduction between the electrical conductor and the thermoelement.Type: GrantFiled: December 7, 2000Date of Patent: August 19, 2003Assignee: International Business Machines CorporationInventor: Uttam Shyamalindu Ghoshal
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Patent number: 6602428Abstract: A sensor for measuring a physical amount such as an amount of air includes a membrane structure composed of metal stripes sandwiched between first and second insulating layers. A metal layer made of platinum or the like is formed on the first insulating layer and then heat-treated to improve its properties. Then, the metal layer is etched into a form of the metal stripes. The second insulating layer made of a material such as silicon dioxide is formed on the etched metal stripes. Since the metal layer is heat-treated before it is etched into the form of metal stripes, the metal stripes are not deformed by the heat-treatment. The second insulating layer can be formed on the metal stripes without generating cracks in the second insulating layer.Type: GrantFiled: November 26, 2001Date of Patent: August 5, 2003Assignee: Denso CorporationInventors: Hiroyuki Wado, Makiko Sugiura, Toshimasa Yamamoto, Yukihiro Takeuchi, Yasushi Kohno
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Publication number: 20030136758Abstract: There is provided a grating fabrication device and method to form gratings on a semiconductor substrate. The substrate is loaded into a reactor filled with an etchant solution, and an array of parallel light of interference light with different periods is projected onto the substrate to etch the portion of the substrate that is exposed to the light via an oxidation-reduction reaction. At the same time, the inclination angle of the substrate is selectively varied to obtain the different grating periods.Type: ApplicationFiled: January 9, 2003Publication date: July 24, 2003Inventor: Dong-Soo Bang
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Patent number: 6585904Abstract: A process is revealed whereby resistors can be manufactured integral with a printed circuit board by plating the resistors onto the insulative substrate. Uniformization of the insulative substrate through etching and oxidation of the plated resistor are discussed as techniques for improving the uniformity and consistency of the plated resistors. Trimming and baking are also disclosed as methods for adjusting and stabilizing the resistance of the plated resistors.Type: GrantFiled: February 15, 2001Date of Patent: July 1, 2003Inventors: Peter Kukanskis, Dennis Fritz, Frank Durso, Steven Castaldi, David Sawoska
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Patent number: 6586049Abstract: A method of patterning at least one object layer, includes a step of forming a mask on the object layer, and a step of selectively etching the object layer using the mask. The mask is made of a magnetic metallic compound with a basic metal of nickel or cobalt containing at least group 3B element and/or group 5B element.Type: GrantFiled: December 11, 2000Date of Patent: July 1, 2003Assignee: TDK CorporationInventors: Yasufumi Uno, Toru Inoue, Tetsuya Mino, Koji Matsukuma
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Patent number: 6582617Abstract: Provided is a method of etching an etch layer using a polycarbonate layer as a mask. The method includes placing an etch structure in a reaction chamber, the etch structure including an etch layer underlying a polycarbonate layer, the polycarbonate layer having apertures. The etch layer is then etched using a low-pressure high density plasma generate at a pressure in the range of approximately 1 to 30 millitorr where the ionized particle concentration is at least 1011 ions/cm3 and where the ionized particle concentration is substantially equal throughout the volume of the reaction chamber. To increase the etch rate, the etch structure can be cooled or biased. To decrease the etch rate, an inert gas can be added to the process gas mixture used to form the plasma.Type: GrantFiled: April 29, 1999Date of Patent: June 24, 2003Assignee: Candescent Technologies CorporationInventor: Chungdee Pong
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Patent number: 6579565Abstract: A multilayered circuit board is produced by: a. laminating a copper foil conductor layer and a nickel foil or nickel plating etch-stopping layer by simultaneously press-bonding the nickel and copper layer to form a multilayered clad sheet; b. selectively etching the multilayered clad sheet; c. forming an insulating layer and an outer conductor layer on the surface of the clad sheet; d. patterning the outer conductor layer; and e. electrically connecting the internal conductor layer and the outer conductor layer by interposing a columnar conductor formed in the base by etching.Type: GrantFiled: July 1, 2002Date of Patent: June 17, 2003Assignee: Toyo Kohan Co., Ltd.Inventors: Kinji Saijo, Shinji Ohsawa, Kazuo Yoshida
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Patent number: 6579806Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing a rapid etch rate. In particular, the method employs the use of a plasma source gas where the chemically functional etchant species are generated from a combination of sulfur hexafluoride (SF6) and nitrogen (N2), where the sulfur hexafluoride and nitrogen are provided in a volumetric flow rate ratio within the range of about 1:2.5 to about 6:1.Type: GrantFiled: May 7, 2002Date of Patent: June 17, 2003Assignee: Applied Materials Inc.Inventors: Padmapani Nallan, Hakeem Oluseyi
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Patent number: 6576152Abstract: In a dry etching method for etching a structure obtained by successively depositing, on a substrate, a gate insulating film, a silicon base film, a tungsten film or an alloy film containing tungsten, the dry etching includes a first process of dry-etching the tungsten film or the alloy film including tungsten, and a second process of dry-etching the silicon base film, and the first process employs, as an etching gas, a gas mixture obtained by mixing O2 gas into a gas including at least C and F, with the flow ratio of the O2 gas being 10˜50% by volume percentages. This dry etching method realizes highly-precise dry etching by which a vertical configuration of the poly-metal structure is obtained, and the selection ratio of W with respect to poly-Si can be controlled and, moreover, penetration through the underlying gate oxide film is prevented.Type: GrantFiled: July 6, 2001Date of Patent: June 10, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventor: Tetsuya Matsutani
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Patent number: 6572782Abstract: Recycling process for CdTe/CdS thin film-solar cell modules in which the modules are mechanically disintegrated into module fragments, the module fragments are exposed to an oxygen-containing atmosphere at a temperature of at least 300° C. causing a pyrolysis of adhesive material contained in the module fragments in form of a hydrocarbon based plastics material and the gaseous decomposition products that are generated during the pyrolysis are discharged, and, afterwards, the module fragments freed from the adhesive means are exposed to a chlorine-containing gas atmosphere at a temperature of more than 400° C. causing an etching process wherein the CdCl2 and TeCl4 that are generated in the etching process are made to condense and precipitate by cooling.Type: GrantFiled: August 24, 2001Date of Patent: June 3, 2003Assignee: ANTEC Solar GmbHInventors: Manuel Diequez Campo, Dieter Bonnet, Rainer Gegenwart, Jutta Beier
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Patent number: 6569775Abstract: A method of improving plasma processing of a semiconductor wafer by exposing the wafer or the plasma to photons while the wafer is being processed. One embodiment of the method comprises the steps of etching an aluminum layer and, during the etching, exposing the semiconductor wafer containing the aluminum layer to photons that photodesorb copper chloride from the surface of the layer thus improving the etch process performance.Type: GrantFiled: February 17, 2000Date of Patent: May 27, 2003Assignee: Applied Materials, Inc.Inventors: Peter K. Loewenhardt, John M. Yamartino, Hui Chen, Diana Xiaobing Ma
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Publication number: 20030092279Abstract: This invention relates to a method of forming a dual damascene via, in particular to a method of forming a dual damascene via by using a metal hard mask layer. The present invention uses a metal layer to be a hard mask layer to make the surface of the isolation layer become a level and smooth surface and not become a rounding convex and to prevent the via being connected with others vias to cause the leakage defects after forming the shape of the via.Type: ApplicationFiled: November 13, 2001Publication date: May 15, 2003Applicant: UNITED MICROELECTRONICS CORP.Inventors: Teng-Chun Tsai, Chia-Lin Hsu
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Patent number: 6552256Abstract: A multi-stage cooler is formed from monolithically integrated thermionic and thermoelectric coolers, wherein the thermionic and thermoelectric coolers each have a separate electrical connection and a common ground, thereby forming a three terminal device. The thermionic cooler is comprised of a superlattice barrier surrounded by cathode and anode layers grown onto an appropriate substrate, one or more metal contacts with a finite surface area deposited on top of the cathode layer, and one or more mesas of different areas formed by etching around the contacts to the anode layer. The thermoelectric cooler is defined by metal contacts deposited on the anode layer or the substrate itself. A backside metal is deposited on the substrate for connecting to the common ground.Type: GrantFiled: March 6, 2001Date of Patent: April 22, 2003Assignee: The Regents of the University of CaliforniaInventors: Ali Shakouri, Christopher J. LaBounty, John E. Bowers
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Patent number: 6547978Abstract: Copper can be pattern etched in a manner which provides the desired feature dimension and integrity, at acceptable rates, and with selectivity over adjacent materials. To provide for feature integrity, the portion of the copper feature surface which has been etched to the desired dimensions and shape must be protected during the etching of adjacent feature surfaces. This is particularly important for feature sizes less than about 0.5 &mgr;m, where presence of even a limited amount of a corrosive agent can eat away a large portion of the feature.Type: GrantFiled: December 13, 2001Date of Patent: April 15, 2003Assignee: Applied Materials Inc.Inventors: Yan Ye, Allen Zhao, Xiancan Deng, Diana Xiaobing Ma, Chang-Lin Hsieh
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Publication number: 20030062338Abstract: Corruption of features formed by etching a metal-containing web in a continuous etch process is reduced by distorting the original design or designs of the features to compensate for localized areas subject to excessive etching during the continuous etch process. In the case of a planar speaker diaphragm, for example, the width of the portions of the trace that are in a cross-machine direction is increased to compensate for the higher etching rate caused by the motion through the etch bath. While this causes the modified trace design to appear to be distorted relative to the original trace design, the etched trace resulting from the modified trace design has improved uniformity and greater fidelity to the original trace design than if the original trace design had been used in the continuous etch process.Type: ApplicationFiled: November 12, 2002Publication date: April 3, 2003Inventor: Laurence MC Lai
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Patent number: 6536449Abstract: Systems and methods are provided for selectively removing unwanted material from a surface of a semiconductor wafer without causing damage to or etching of underlying portions of the semiconductor. One embodiment of the invention includes the use of reactive species from a plasma source to facilitate the removal of residues remaining after metal etching on a silicon wafer, where the gases employed in creating the plasma include hydrogen, halogens such as fluorine, and little or no oxygen.Type: GrantFiled: November 16, 1998Date of Patent: March 25, 2003Assignee: Mattson Technology Inc.Inventors: Craig Ranft, Wolfgang Helle, Robert Guerra, Brady F. Cole
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Publication number: 20030052079Abstract: A method of processing specimens, an apparatus therefor, and a method of manufacture of a magnetic head are provided wherein a complicated conventional post processing step for removing corrosion products is eliminated by a corrosion prevention processing for removing only a residual chlorine compound produced in the gas plasma etching. More specifically, the method is comprised of the steps of: forming a lamination film including a seed layer made of NiFe alloy, an upper magnetic pole made of NiFe alloy connected to the seed layer, a gap layer made of oxide film in close contact with the seed layer, and a shield layer made of NiFe alloy in close contact with the gap layer; plasma-etching the seed layer with a gas which contains chlorine using the upper magnetic pole as a mask; and after that removing the residual chlorine compound by a plasma post treatment with a gas plasma which contains H2O or methanol.Type: ApplicationFiled: October 25, 2002Publication date: March 20, 2003Inventors: Ken Yoshioka, Yoshimi Torii, Moriaki Fuyama, Tomohiro Okada, Saburou Kanai, Takehito Usui, Hitoshi Harata
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Publication number: 20030019841Abstract: Methods of using reactive gases containing a perfluoroketone having 4 to 7 carbon atoms for removing unwanted deposits that build up in a vapor reactor, for etching dielectric and metallic materials in a vapor reactor, and for doping a material in a vapor reactor are described. The perfluoroketones perform as well as or better than the standard perfluorocarbons used in the semiconductor industry but have minimal impact on global warming.Type: ApplicationFiled: April 24, 2001Publication date: January 30, 2003Applicant: 3M Innovative Properties CompanyInventors: Susrut Kesari, Fred E. Behr, Michael G. Costello, Richard M. Flynn, Richard M. Minday, John G. Owens, Daniel R. Vitcak, Larry A. Zazzera
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Patent number: 6511463Abstract: Microneedle arrays are fabricated by providing a sacrificial mold including a substrate and an array of posts, preferably solid posts, projecting therefrom. A first material is coated on the sacrificial mold including on the substrate and on the array of posts. The sacrificial mold is removed to provide an array of hollow tubes projecting from a base. The inner and outer surfaces of the array of hollow tubes are coated with a second material to create the array of microneedles projecting from the base. The sacrificial mold may be fabricated by fabricating a master mold, including an array of channels that extend into the master mold from a face thereof. A third material is molded into the channels and on the face of the master mold, to create the sacrificial mold. The sacrificial mold then is separated from the master mold. Alternatively, wire bonding may be used to wire bond an array of wires to a substrate to create the sacrificial mold.Type: GrantFiled: November 18, 1999Date of Patent: January 28, 2003Assignee: JDS Uniphase CorporationInventors: Robert L. Wood, Henry A. Wynands, Karen W. Markus
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Patent number: 6511918Abstract: The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound and at least one oxidizing agent. The concentration of the oxidizing agent is thereby set higher than the concentration of the halogen compound.Type: GrantFiled: June 4, 2001Date of Patent: January 28, 2003Assignee: Infineon Technologies AGInventors: Stephan Wege, Kerstin Krahl
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Publication number: 20030006215Abstract: An etchant and a method for roughening a copper surface each capable of permitting copper with roughened surface which exhibits acid resistance and permits a copper conductive pattern and an outer layer material to be firmly bonded to each other therethrough in manufacturing of a printed wiring board to simplify the manufacturing. The etchant may contain an oxo acid such as sulfuric acid, peroxide such as hydrogen peroxide and an auxiliary component such as an azole and chlorine. The azole may comprise benzotriazole (BTA). The chlorine may be in the form of sodium chloride (NaCl). The etchant permits a copper surface to be roughened in an acicular manner.Type: ApplicationFiled: July 28, 1997Publication date: January 9, 2003Inventors: YOSHIHIKO MORIKAWA, KAZUNORI SENBIKI, NOBUHIRO YAMAZAKI
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Patent number: 6503845Abstract: A method of plasma etching a patterned tantalum nitride layer, which provides an advantageous etch rate and good profile control. The method employs a plasma source gas comprising a primary etchant to provide a reasonable tantalum etch rate, and a secondary etchant/profile-control additive to improve the etched feature profile. The primary etchant is either a fluorine-comprising or an inorganic chlorine-comprising gas. Where a fluorine-comprising gas is the primary etchant, the profile-control additive is a chlorine-comprising gas. Where the chlorine-comprising gas is the primary etchant, the profile-control additive is an inorganic bromine-comprising gas. By changing the ratio of the primary etchant to the profile-control additive, the etch rate and etch profile of the tantalum nitride can be controlled. For best results, the plasma is preferably a high density plasma (minimum electron density of 1011e−/cm3), and a bias power is applied to the semiconductor substrate to increase the etching anisotropy.Type: GrantFiled: May 1, 2001Date of Patent: January 7, 2003Assignee: Applied Materials Inc.Inventor: Padmapani Nallan
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Patent number: 6500351Abstract: A recording head pole production process, and a pole made by the process, in which a combination of wet and dry etching steps are utilized to advantageously provide an undercut in the relatively high magnetic moment material beneath a photoresist area used to define the pole such that any re-deposited layer of material which occurs on the sides of the pole and photoresist area during the dry etching operation is advantageously rendered substantially discontinuous, or weakly linked, and the re-deposited material remaining on the pole itself following a photoresist strip can then be removed by being subjected to a stream of gaseous particles and ultimately carried away by the accompanying gas stream itself. In a particular embodiment disclosed herein the relatively high magnetic moment material may comprise a sputter deposited layer of cobalt-zirconium-tantalum (CoZrTa), iron-aluminum-nitride (FeAlN), iron-tantalum-nitride (FeTaN), iron-nitride (FeN) or similar materials.Type: GrantFiled: May 24, 1999Date of Patent: December 31, 2002Assignee: Maxtor CorporationInventors: Andrew L. Wu, Jeffrey G. Greiman, Lawrence G. Neumann, Vijay K. Basra
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Patent number: 6500767Abstract: A method of etching a metallic layer having an anti-reflection layer thereon. The method includes performing a first etching operation using a fixed set of processing parameters to etch the anti-reflection layer and remove a specified thickness of the metallic layer. Thereafter, a second etching operation is conducted to etch the remaining metallic layer.Type: GrantFiled: June 5, 2001Date of Patent: December 31, 2002Assignee: Macronix International Co., Ltd.Inventors: Jen-Jiann Chiou, Shin-Yi Tsai
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Publication number: 20020197457Abstract: An impregnated printed circuit board and a manufacturing method for the same are disclosed, in which the surface for installing semiconductor devices is uniform. The manufacturing method includes the following steps. That is, a resist is spread on a metal sheet, and copper is coated on areas of the metal sheet other than the areas of the resist. The resist is removed, and another metal sheet is disposed in parallel to and slightly separated from the above metal sheet. Then an insulating resin is inserted into between the two metal sheets, and they are pressed together. Then the metal sheets are removed, thereby completing the manufacture of the impregnated printed circuit board. Thus the component-installing surface is smoothly flat, and any height difference between the circuit pattern and the base sheet is eliminated. Therefore, the formation of a short circuit or open circuit can be prevented.Type: ApplicationFiled: June 17, 2002Publication date: December 26, 2002Applicant: Global Circuit Co., Lts.Inventor: Jae Suk Eum
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Patent number: 6498109Abstract: A process for plasma etching metal films comprising the steps of forming a noble gas plasma, then transporting the noble gas plasma to a mixing chamber. An organohalide is added to the noble gas plasma in the mixing chamber. The organohalide is selected to have a vapor pressure allowing the formation of activated complexes to etch the metal films and form organometallic compounds as the etch byproducts. The activated complexes thus formed are transported downstream to an etching chamber. In the etching chamber the selected substrate is exposed to the activated complexes, causing the substrate to be etched and organometallic compounds to be formed as byproducts from the reaction of the activated complexes and etching of the substrate. The organometallic byproducts can then be removed from the etch chamber.Type: GrantFiled: March 1, 2001Date of Patent: December 24, 2002Assignee: Micron Technology, Inc.Inventor: Ravi Iyer
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Publication number: 20020190025Abstract: The invention encompasses methods for etching and/or over-etching tungsten stack structures, especially tungsten-polysilicon stack structures. The etching methods of the invention preferably employ a Cl2/NF3 etchant, optionally including O2 and/or helium. The over-etching methods of the invention preferably use a NF3/N2/O2 etchant. The methods of the invention enable effective etching of tungsten-polysilicon stacks where topographic variation is present across the substrate and/or where other tungsten stacks of different structure are also being etched.Type: ApplicationFiled: June 15, 2001Publication date: December 19, 2002Applicant: International Business Machines CorporationInventor: Munir D. Naeem