Substrate Contains Elemental Metal, Alloy Thereof, Or Metal Compound Patents (Class 216/75)
  • Patent number: 6491832
    Abstract: A method of processing specimens, an apparatus therefor, and a method of manufacture of a magnetic head are provided wherein a complicated conventional post processing step for removing corrosion products is eliminated by a corrosion prevention processing for removing only a residual chlorine compound produced in the gas plasma etching. More specifically, the method is comprised of the steps of: forming a lamination film including a seed layer made of NiFe alloy, an upper magnetic pole made of NiFe alloy connected to the seed layer, a gap layer made of oxide film in close contact with the seed layer, and a shield layer made of NiFe alloy in close contact with the gap layer; plasma-etching the seed layer with a gas which contains chlorine using the upper magnetic pole as a mask; and after that removing the residual chlorine compound by a plasma post treatment with a gas plasma which contains H2O or methanol.
    Type: Grant
    Filed: January 28, 2000
    Date of Patent: December 10, 2002
    Assignees: Hitachi, Ltd., Hitachi Metals, Ltd.
    Inventors: Ken Yoshioka, Yoshimi Torii, Moriaki Fuyama, Tomohiro Okada, Saburou Kanai, Takehito Usui, Hitoshi Harata
  • Patent number: 6489247
    Abstract: Copper can be pattern etched in a manner which provides the desired feature dimension and integrity, at acceptable rates, and with selectivity over adjacent materials. To provide for feature integrity, the portion of the copper feature surface which has been etched to the desired dimensions and shape must be protected during the etching of adjacent feature surfaces. To avoid the trapping of reactive species interior of the etched copper surface, hydrogen is applied to that surface. Hydrogen is adsorbed on the copper exterior surface and may be absorbed into the exterior surface of the copper, so that it is available to react with species which would otherwise penetrate that exterior surface and react with the copper interior to that surface. Sufficient hydrogen must be applied to the exterior surface of the etched portion of the copper feature to prevent incident reactive species present due to etching of adjacent feature surfaces from penetrating the previously etched feature exterior surface.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: December 3, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Yan Ye, Allen Zhao, Xiancan Deng, Diana Xiaobing Ma
  • Patent number: 6488862
    Abstract: Copper can be pattern etched at acceptable rates and with selectivity over adjacent materials using an etch process which utilizes a solely physical process which we have termed “enhanced physical bombardment”. Enhanced physical bombardment requires an increase in ion density and/or an increase in ion energy of ionized species which strike the substrate surface. To assist in the removal of excited copper atoms from the surface being etched, the power to the ion generation source and/or the substrate offset bias source may be pulsed. In addition, when the bombarding ions are supplied from a remote source, the supply of these ions may be pulsed. Further, thermal phoresis may be used by maintaining a substrate temperature which is higher than the temperature of a surface in the etch chamber.
    Type: Grant
    Filed: October 27, 1999
    Date of Patent: December 3, 2002
    Assignee: Applied Materials Inc.
    Inventors: Yan Ye, Diana Xiaobing Ma, Gerald Yin
  • Patent number: 6479396
    Abstract: In a process of preparing a via in a semiconductor substrate wafer in which vias are landed on tungsten, and in which resist is stripped using plasma or chemical based processes that do not remove the veils formed during the etch, the improvement of concurrently removing veil material, controlling the interface of the tungsten, and stripping the resist, comprising: a) depositing and patterning tungsten on a substrate; b) depositing an oxide as an interlevel dielectric on the tungsten; c) patterning the oxide using photolithography and a photoresist; d) etching the oxide using a plasma generated etching method in which veils made up of metals, carbon based materials and oxide based materials are formed on the tungsten and sidewalls of the vias; and e) stripping the resist using a dry polymer removal method employing process gases and reducing gases to concurrently cause resist stripping, removal of the veils, and control of the tungsten interface.
    Type: Grant
    Filed: February 28, 2001
    Date of Patent: November 12, 2002
    Assignee: Infineon Technologies Richmond, LP
    Inventors: Han Xu, Amy Ying Shen, Phillip Gerard Clark, Jr.
  • Patent number: 6475400
    Abstract: A method for controlling the sheet resistance of thin film resistors. The sheet resistance can be inexpensively controlled within a tight tolerance by determining a desired final value for the sheet resistance of thin film resistor material to be deposited on a substrate, depositing the resistor material on the substrate using a deposition process which is consistent enough to achieve a target sheet resistance within a first specified tolerance, the resistor material being deposited to achieve a target sheet resistance which is equal to the desired final value minus the first specified tolerance, and removing a small amount of material from the surface of the deposited thin film resistor material by etching or ion bombardment to raise the sheet resistance to the desired final value within a second specified tolerance characteristic of the removing process where the second specified tolerance is less than the first specified tolerance.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: November 5, 2002
    Assignee: TRW Inc.
    Inventor: Michael D. Lammert
  • Publication number: 20020158039
    Abstract: A method for fabricating an electrically isolated MEMS device having an outer stationary MEMS element and an inner movable MEMS element is provided that does not use a sacrificial layer. Rather, a pair of spacers are defined on the outer portions of the upper surface of a conductive wafer, and an insulating material is deposited thereon. The spacers are attached to a substrate to define an internal void therein. The wafer is then patterned to form the outer MEMS element as well as a conductive member for the inner MEMS element, separated from the outer MEMS element by a gap. A portion of the insulating layer that is disposed in the gap is then removed, thereby releasing the inner MEMS element from the stationary MEMS element.
    Type: Application
    Filed: April 26, 2001
    Publication date: October 31, 2002
    Inventors: Richard D. Harris, Robert J. Kretschmann, Michael J. Knieser, Mark A. Lucak
  • Publication number: 20020158044
    Abstract: A method for magnetic patterning of conductors includes imparting a pattern of magnetization into a magnetic material and depositing a substance onto the magnetic material that preferentially gathers according to the pattern in the magnetic material. A set of conductors are then formed such that the substance controls a pattern for the conductors.
    Type: Application
    Filed: April 26, 2001
    Publication date: October 31, 2002
    Inventor: Richard H. Henze
  • Patent number: 6471878
    Abstract: A method for forming a radio frequency responsive target formed of a pattern of thin dipoles, each of which has a position and angular orientation within the pattern, which produce a composite analog radio frequency signal in response to an interrogating signal. A first metallic film layer is deposited on top of a non-conductive substrate, an etchant resistant pattern correspondent to the thin dipole pattern is deposited on top of the first metallic film layer, and a second metallic layer occupying the first metallic layer in at least one area without etchant is applied on top of the first metallic film layer. The etchant resistant pattern is removed to expose portions of the first metallic film layer, and the second metallic layer and the exposed portions of the first metallic film layer are etched simultaneously.
    Type: Grant
    Filed: June 9, 1999
    Date of Patent: October 29, 2002
    Assignee: Gordion Holding Corporation
    Inventors: Morton Greene, G. William Hurley
  • Patent number: 6464889
    Abstract: An irregularly etched metallic medical implant device is provided having random non-uniform relief patterns on the surface ranging from about 0.3 &mgr;m to less than about 20 &mgr;m in depth. The random, irregular surface as defined by the etch micromorphology and respective dimensional properties is sobtained by exposing a surface to a reactive plasma in a chamber wherein said reactive plasma produces a reaction product with the surface to thereby etch the surface, said reaction product or a complex thereof having a vapor pressure lower than a pressure in the chamber; providing a dynamic masking agent during the etching process; and removing the reaction products.
    Type: Grant
    Filed: January 25, 2000
    Date of Patent: October 15, 2002
    Assignee: Etex Corporation
    Inventors: Dosuk D. Lee, Atul Nagras, Pramod Chakravarthy, Anthony M. Majahad
  • Patent number: 6451215
    Abstract: The present invention relates to a method of producing a magneto-resistive tunnel junction head comprising a tunnel multilayered film having a tunnel barrier layer, a ferromagnetic free layer and a ferromagnetic pinned layer such that the tunnel barrier layer is held between the ferromagnetic free layer and the ferromagnetic pinned layer. The method comprises a laminating step of forming the tunnel barrier layer and a non-magnetic metal protect layer in turn on the ferromagnetic pinned layer, an insulating layer forming step of forming side insulating layers on both sides of a lamination body having the ferromagnetic pinned layer, the tunnel barrier layer and the non-magnetic metal protect layer, a cleaning step of cleaning the surface of the non-magnetic metal protect layer, and a ferromagnetic free layer forming step of forming the ferromagnetic free layer such that the ferromagnetic free layer faces the ferromagnetic pinned layer via the cleaned surface.
    Type: Grant
    Filed: April 4, 2000
    Date of Patent: September 17, 2002
    Assignee: TDK Corporation
    Inventors: Koji Shimazawa, Satoru Araki, Haruyuki Morita
  • Patent number: 6451240
    Abstract: A microneedle array is manufactured using a mold preparation procedure that begins by placing an optical mask over a layer of PMMA material, exposing the PMMA material to x-rays, then developing using a photoresist process. The remaining PMMA material is then electroplated with metal. Once the metal has reached an appropriate thickness, it is detached to become a metal mold that is used in a microembossing procedure, in which the metal mold is pressed against a heated layer of plastic material. Once the mold is pressed down to its proper distance, the plastic material is cooled until solidified, and the mold is then detached, thereby leaving behind an array of microneedles.
    Type: Grant
    Filed: May 26, 2000
    Date of Patent: September 17, 2002
    Assignee: The Procter & Gamble Company
    Inventors: Faiz Feisal Sherman, Vadim Vladimirovich Yuzhakov, Vladimir Gartstein, Grover David Owens
  • Publication number: 20020121497
    Abstract: A preferred embodiment of a stent provides a folded strut section that provides both structural rigidity and reduction in foreshortening of the stent mechanism. A flexible section provides flexibility for delivery of the stent mechanism. In a second embodiment, flexible section columns are angled with respect to each other, and to the longitudinal axis of the stent. These relatively flexible sections are oppositely phased in order to negate any torsion along their length. In yet another embodiment, the flexible connector can take on an undulating shape (like an “N”), but such that the longitudinal axis of the connector is not parallel with the longitudinal axis of the stent. Finally, a new method is disclosed for making stents. The method consists of performing a standard photochemical machining process of cutting, cleaning and coating the tube with a photoresist.
    Type: Application
    Filed: March 2, 2001
    Publication date: September 5, 2002
    Inventor: Charles V. Tomonto
  • Patent number: 6444083
    Abstract: A corrosion resistant component of semiconductor processing equipment such as a plasma chamber includes a metal surface such as aluminum or aluminum alloy, stainless steel, or refractory metal coated with a phosphorus nickel plating and an outer ceramic coating such as alumina, silicon carbide, silicon nitride, boron carbide or aluminum nitride. The phosphorus nickel plating can be deposited by electroless plating and the ceramic coating can be deposited by thermal spraying. To promote adhesion of the ceramic coating, the phosphorus nickel plating can be subjected to a surface roughening treatment prior to depositing the ceramic coating.
    Type: Grant
    Filed: June 30, 1999
    Date of Patent: September 3, 2002
    Assignee: Lam Research Corporation
    Inventors: Robert Steger, Chris Chang
  • Publication number: 20020117471
    Abstract: We have discovered a method of reducing the effect of material sputtered/etched during the preheating of a substrate. One embodiment of the method pertains to the preheating of a substrate which includes a material which is to be pattern etched at a temperature in excess of 150° C. The method comprises exposing the substrate to a preheating plasma generated from a plasma source gas which includes a reactive gas that aids in the production of a sputtered/etched residue during the preheating which is more easily etched during a subsequent pattern etching step than the material which is being pattern etched. In another embodiment of the method, the reactive gas in the preheating plasma source gas is slightly reactive with the material which is to etched during the subsequent pattern etching step.
    Type: Application
    Filed: December 22, 2000
    Publication date: August 29, 2002
    Inventors: Jeng H. Hwang, Xiaoyi Chen
  • Publication number: 20020117472
    Abstract: A substrate processing apparatus has a chamber with a substrate transport to transport a substrate onto a substrate support in the chamber, a gas supply to provide a gas in the chamber, a gas energizer to energize the gas, and a gas exhaust to exhaust the gas. A controller operates one or more of the substrate support, gas supply, gas energizer, and gas exhaust, to set etching process conditions in the chamber to etch a plurality of substrates, thereby depositing etchant residues on surfaces in the chamber. The controller also operates one or more of the substrate support, gas supply, gas energizer, and gas exhaust, to set cleaning process conditions in the chamber to clean the etchant residues. The cleaning process conditions comprise a volumetric flow ratio of O2 to CF4 of from about 1:1 to about 1:40.
    Type: Application
    Filed: February 23, 2001
    Publication date: August 29, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Zhi-Wen Sun, Anbei Jiang, Tuo-Chuan Huang
  • Patent number: 6440873
    Abstract: A post metal etch cleaning method which begins by providing a wafer with an etched metal layer formed thereon, wherein the etched metal layer is covered with a polymer residue. A fluorine based organic acid solvent is used to clean the metal layer, followed by removing the solvent by a physical method. Next, a de-ionized water is applied to flush the metal layer before performing a drying step on the wafer to dry the metal layer.
    Type: Grant
    Filed: February 26, 2001
    Date of Patent: August 27, 2002
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Ning Wu, Chan-Lon Yang
  • Patent number: 6440870
    Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically, the oxide is selected from silicon oxide, silicon oxynitride, tantalum pentoxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD).
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: August 27, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Padmapani Nallan, Hakeem Oluseyi
  • Patent number: 6440865
    Abstract: A method of profile control in metal etching, wherein a metal layer is positioned on a dielectric layer comprising an aluminum-alloy layer on the dielectric and an anti-reflection layer on the aluminum-alloy layer. The method of the present invention includes a step of performing a breakthrough step of a first etch recipe to remove the anti-reflection layer and a certain thickness of the aluminum-alloy layer until a predetermined depth is reached. The method then further includes a step of performing a main etch step of a second etch recipe having a higher etch rate than the first etch recipe to remove the remaining residue of the aluminum-alloy layer. The main object of the present invention is to achieve formations of metal lines with smooth and tapered sidewalls. Thereby, the method of the present invention reduces the possibility of forming voids during the subsequent deposition process, which improves the reliability of the IC devices made.
    Type: Grant
    Filed: May 22, 2000
    Date of Patent: August 27, 2002
    Assignee: Winbond Electronics Corp.
    Inventor: Szetsen Steven Lee
  • Patent number: 6432317
    Abstract: This is a method for masking a structure 12 for patterning micron and submicron features, the method comprises: forming at least one monolayer 32 of adsorbed molecules on the structure; prenucleating portions 46,48 of the adsorbed layer by exposing the portions corresponding to a desired pattern 36 of an energy source 42; and selectively forming build-up layers 66,68 over the prenucleated portions to form a mask over the structure to be patterned. Other methods are also disclosed.
    Type: Grant
    Filed: August 4, 1994
    Date of Patent: August 13, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Monte A. Douglas, Richard A. Stoltz
  • Patent number: 6428714
    Abstract: An improved process for manufacturing a spin valve structure that has buried leads is disclosed. A key feature is the inclusion in the process of a temporary protective layer over the seed layer on which the spin valve structure will be grown. This protective layer remains in place while the buried leads as well as longitudinal bias means are formed. Processing includes use of photoresist liftoff. The protective layer is removed as a natural byproduct of surface cleanup just prior the formation of the spin valve.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: August 6, 2002
    Assignee: Headway Technologies, Inc.
    Inventors: Chyu-Jiuh Torng, Chen-Jung Chien, Kochan Ju, Jei-Wei Chang
  • Publication number: 20020102496
    Abstract: A thin film circuit substrate is manufactured by forming a lower thin film electrode on a substrate, forming an organic insulating film with via holes on the lower thin film electrode, and irradiating the substrate with an inert gas ion to remove an oxidized surface film on the lower thin film electrode, and to generate functional groups, such that a modified surface layer with a surface modification coefficient of about 0.1 to about 0.5 is formed on the surface of the organic insulating film, and such that the oxidized surface film on the lower thin film electrode is removed at the same time. Accordingly, a thin film circuit substrate having excellent adhesion strength between the organic insulating film and the upper thin film electrode as well as excellent reliability of electroconductivity between the upper and the lower thin film electrodes is efficiently manufactured.
    Type: Application
    Filed: January 29, 2002
    Publication date: August 1, 2002
    Inventors: Koji Yoshida, Makoto Tose
  • Patent number: 6426012
    Abstract: A three-part etching process is employed to selectively pattern exposed magnetic film layers of a magnetic thin film structure. The magnetic structure to be etched includes at least one bottom magnetic film layer and at least one top film layer which are separated by a tunnel barrier layer. The three-part etching process employs various etching steps that selective removing various layers of the magnetic thin film structure stopping on the tunnel barrier layer. The first etching step selective removes any surface oxide that may be present in the passivating layer that is formed on the top magnetic thin film layer, the second etching step selectively removes portions of the passivating layer and the third etching step selectively removes a portion of the exposed magnetic film layer of the structure stopping on the tunnel barrier layer.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: July 30, 2002
    Assignee: International Business Machines Corporation
    Inventors: Eugene John O'Sullivan, Alejandro Gabriel Schrott
  • Publication number: 20020096492
    Abstract: A device for utilizing an optical infrared emitter/detector to sense substances of interest is provided. The infrared emitter/detector comprises a single crystal semiconductor, photonic band gap structure which functions both as an infrared emitter, a narrow-band filter, and as a broad-band infrared bolometer detector to exert wavelength control directly on the active element emitter/detector surface using the periodic symmetry of the photonic band gap structure to produce narrow wavelength “forbidden” optical transmission bands or modes to sense the presence of a specified substance in the environment. A system and method for sensing specific substances using the optical infrared emitter/detector of this invention in a sensor device is also provided. Finally, a method of manufacturing the infrared emitter/detectors of the present invention is also provided.
    Type: Application
    Filed: January 26, 2001
    Publication date: July 25, 2002
    Inventors: Thomas George, Daniel S. Choi, Eric Jones
  • Patent number: 6423240
    Abstract: A method of altering the topography of a trailing edge of a slider is disclosed, the slider having a substrate surface, at least one magnetic recording head imbedded in an alumina undercoat, and a vertical axis relative to the substrate surface. The steps include first applying an alumina overcoat to at least the trailing edge, followed by lapping at least the trailing edge of the slider. The slider (or sliders) is then placed on a pallet that rotates, exposing the trailing edge to an ion beam. The ion beam is generated using an etchant gas such as Argon, or a mixture of gases such as Argon and Hydrogen, or Argon and CHF3. The trailing edge (or trailing edges) are then exposed at least once to the ion beam at a predetermined milling angle and predetermined time, the milling angle being the angle made by the ion beam relative to the vertical axis. The milling angle is typically between 0° and 85°.
    Type: Grant
    Filed: January 7, 2000
    Date of Patent: July 23, 2002
    Assignee: International Business Machines Corporation
    Inventors: Benjamin Wang, Cherngye Hwang
  • Patent number: 6423644
    Abstract: The present invention relates to a method of etching tungsten or tungsten nitride in semiconductor structures, and particularly to the etching of gate electrodes which require precise control over the etching process. We have discovered a method of etching tungsten or tungsten nitride which permits precise etch profile control while providing excellent selectivity, of at least 175:1, for example, in favor of etching tungsten or tungsten nitride rather than an adjacent oxide layer. Typically the oxide is selected from silicon oxide, silicon oxynitride, tantalum oxide, zirconium oxide, and combinations thereof. The method appears to be applicable to tungsten or tungsten nitride, whether deposited by physical vapor deposition (PVD) of chemical vapor deposition (CVD).
    Type: Grant
    Filed: July 12, 2000
    Date of Patent: July 23, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Padmapani Nallan, Hakeem Oluseyi
  • Patent number: 6418941
    Abstract: There is disclosed a method of the plasma cleaning of a chip-mounted board, in which the destruction of a chip due to the charge build-up in a land during the plasma cleaning is prevented. There is provided a mask member for covering a board placed on a plasma-generating electrode. This mask member has openings through which the chip, mounted on the land on the board, and electrodes on the board are exposed, respectively, and an exposed portion of the land, extending outwardly of the chip, and a conducting portion on the board are covered with the mask member. A high-frequency voltage is applied to the plasma-generating electrode, thereby producing plasm within a vacuum chamber, so that ions Ar+ impinge on pads on the chip to clean and charge up these pads. The land is covered with the mask member, and therefore will not be charged up with the ions Ar+ and electrons e−.
    Type: Grant
    Filed: October 2, 1998
    Date of Patent: July 16, 2002
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kiyoshi Arita, Tanemasa Asano
  • Patent number: 6419845
    Abstract: It is an object to provide a method of etching which enables measurement control of the micro width of a magnetic layer while shortening the time required for the etching procedure. An inorganic insulating film made of alumina which is the same material as the write gap layer is formed on a top pole layer by, for example, sputtering method. A photoresist film (first mask) is formed on the inorganic insulating film by photolithography. Next, an inorganic insulating mask (second mask) is formed by selectively etching the inorganic insulating film by reactive ion etching (RIE) using gas etchant such as CF4 (carbon ride), BCl3(boron trichloride), Cl2 (chlorine), SF6 (sulfur hexafluoride) and so on using the photoresist film as a mask. The top layer is selectively removed by, for example, ion milling with Ar (argon) using the inorganic insulating mask.
    Type: Grant
    Filed: May 24, 1999
    Date of Patent: July 16, 2002
    Assignee: TDK Corporation
    Inventor: Yoshitaka Sasaki
  • Publication number: 20020084034
    Abstract: The processing with a low gate rate of destruction and high anisotropy is achieved in dry etching. Plasma is generated by ECR resonance of electromagnetic wave which arose by supplying Ultra High Frequency electric power in microstripline 4 arranged on the atmosphere side of a dielectric 2, which separates a vacuum inside and an outside and magnetic field. A conducting layer is etched by this plasma, which is stable and uniform plasma.
    Type: Application
    Filed: July 29, 1999
    Publication date: July 4, 2002
    Inventors: NAOYUKI KOFUJI, MASAHITO MORI, KEN?apos;ETSU YOKOGAWA, NAOSHI ITABASHI, KAZUNORI TSUJIMOTO, SHIN?apos;ICHI TACHI
  • Publication number: 20020070195
    Abstract: A sensor for measuring a physical amount such as an amount of air includes a membrane structure composed of metal stripes sandwiched between first and second insulating layers. A metal layer made of platinum or the like is formed on the first insulating layer and then heat-treated to improve its properties. Then, the metal layer is etched into a form of the metal stripes. The second insulating layer made of a material such as silicon dioxide is formed on the etched metal stripes. Since the metal layer is heat-treated before it is etched into the form of metal stripes, the metal stripes are not deformed by the heat-treatment. The second insulating layer can be formed on the metal stripes without generating cracks in the second insulating layer.
    Type: Application
    Filed: November 26, 2001
    Publication date: June 13, 2002
    Inventors: Hiroyuki Wado, Makiko Sugiura, Toshimasa Yamamoto, Yukihiro Takeuchi, Yasushi Kohno
  • Patent number: 6393685
    Abstract: A wafer level interconnecting mechanism for assembling and packaging multiple MEMS devices (modules), using microfabricated, interlocking, mechanical joints to interconnect different modules and to create miniature devices. Various devices can be fabricated using these joints, including fiber-optic switches, xyz translational stages, push-n-lock locking mechanisms, slide-n-lock locking mechanisms, t-locking joints, fluidic interconnects, on/off valves, optical fiber couplers with xy adjustments, specimen holders, and membrane stops.
    Type: Grant
    Filed: June 9, 1998
    Date of Patent: May 28, 2002
    Assignee: The Regents of the University of California
    Inventor: Scott D. Collins
  • Publication number: 20020060201
    Abstract: A method and an apparatus for etching a semiconductor device which can perform an etching process without causing electrical and physical damages using a neutral beam generated by a simple apparatus. In the method, ions of an ion beam having a predetermined polarity are extracted from an ion source and accelerated. An accelerated ion beam is reflected by a reflector and neutralized. A substrate to be etched positioned in the path of the neutral beam in order to etch a special material layer on the substrate with the neutral beam. The gradient of the reflector is adjusted to control an angle of incidence of the ion beam incident on the reflector, and a voltage is applied to the reflector to control the path of an incident ion beam.
    Type: Application
    Filed: November 8, 2001
    Publication date: May 23, 2002
    Inventors: Geun-Young Yeom, Do-Haing Lee
  • Patent number: 6391214
    Abstract: A method and apparatus is provided for locating with improved vertical positioning accuracy a discrete element on a semiconductor optoelectronic integrated circuit. The method employs an etch stop layer located beneath a series of semiconductor layers. The semiconductor layers may include waveguides to couple light between integrated or discrete elements. Pits with accurate depth are etched in the semiconductor layers down to the etch stop layer. Accurate alignment between a discrete element and another element is made possible by controlling their respective distances from the etch stop layer.
    Type: Grant
    Filed: June 1, 2000
    Date of Patent: May 21, 2002
    Assignee: Nortel Networks Limited
    Inventor: Stephen J. Kovacic
  • Patent number: 6391790
    Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.
    Type: Grant
    Filed: July 25, 2000
    Date of Patent: May 21, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Brigitte C. Stoehr, Michael D. Welch
  • Patent number: 6383942
    Abstract: A dry etching method is disclosed for use in patterning a stacked film of a metal film containing aluminum as the base component and a thin film including at least one of titanium and titanium nitride. In this method, the thin film is dry-etched using a first etching gas (a mixture of CF4 gas, Ar gas and Cl gas) having a gas composition for preventing the metal film from being processed. The metal film is then dry-etched using a second etching gas (a mixture of Cl gas and BCl3 gas) having a gas composition other than the first etching gas.
    Type: Grant
    Filed: March 9, 2000
    Date of Patent: May 7, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masaki Narita, Hiroshi Sugiura
  • Patent number: 6379981
    Abstract: In one aspect, the invention includes a method of etching, comprising: a) forming a material over a substrate, the material comprising a lower portion near the substrate and an upper portion above the lower portion; b) providing a quantity of detectable atoms within the material, the detectable atoms being provided at a different concentration in the lower portion than in the upper portion; c) etching into the material and forming etching debris; and d) detecting the detectable atoms in the debris. In another aspect, the invention includes a method of etching, comprising: a) providing a semiconductor wafer substrate, the substrate having a center and an edge; b) forming a material over the substrate, the material comprising detectable atoms; c) etching into the material and forming etching debris; d) detecting the detectable atoms in the debris; and e) estimating a degree of center-to-edge uniformity of the etching from the detecting.
    Type: Grant
    Filed: March 27, 1998
    Date of Patent: April 30, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Terry Gilton
  • Patent number: 6375857
    Abstract: A new method is provided for the creation of a fuse. A layer of metal is first deposited, the layer of metal is patterned and etched creating a metal strip that is interrupted by a gap. The fusing function is created in the gap, the interrupted metal strip serves as the connectors to the fuse. A layer of conducting conjugated polymer is deposited over the metal strip and the therein created gap, the polymer is etched back leaving the deposited polymer in the gap between the two metal strips.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: April 23, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Chit Hwei Ng, Xu Yi, Sanford Chu
  • Patent number: 6372150
    Abstract: Water vapor plasma etching of metal surfaces facilitates removal of organic residues over metal surfaces. By plasma etching metal surfaces covered with an organic material, such as photoresist, in an atmosphere in which the water vapor to O2 ratio exceeds 5:3 (such as about 5:1, for example), superior organic material removal results are observed, particularly over relatively wide metal surfaces. The duration of the water vapor plasma etch also may be increased, relative to conventional organic material-removing processes. The effectiveness of the high vapor etch according to the present invention allows the elimination of a subsequent dry organic material stripping step, reducing processing time and cost while increasing yields.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: April 16, 2002
    Assignee: Cypress Semiconductor Corp.
    Inventors: Kaichiu Wong, Gregory M. McMahon
  • Patent number: 6372649
    Abstract: A method for forming a multi-level metal interconnection, comprising the step of forming a first metal interconnection over an underlying layer; forming an insulating layer having a selected thickness over the underlying layer including the first metal interconnection; etching the insulating layer to form a contact hole, thereby exposing the first metal interconnection; forming a metal plug in the contact hole to contact with the first metal interconnection; etching the insulating layer by a portion of the selected thickness; forming a pair of metal spacers in sidewalls of the metal plug over the insulating layer; and forming a second metal interconnection over the insulating layer to contact with the first metal interconnection through one of the metal spacers.
    Type: Grant
    Filed: June 22, 2000
    Date of Patent: April 16, 2002
    Assignee: Hyundai Electronics Industries Co., Ltd.
    Inventors: Min Sub Han, Tae Gook Lee, Wan Soo Kim, Byoung Ju Kang
  • Patent number: 6368978
    Abstract: The present invention is a method for hydrogen-free plasma etching of indium tin oxide using a plasma generated from an etchant gas containing chlorine as a major constituent (i.e., chlorine comprises at least 20 atomic %, preferably at least 50 atomic %, of the etchant gas). Etching is performed at a substrate temperature of 100° C. or lower. The chlorine-comprising gas is preferably Cl2. The etchant gas may further comprise a non-reactive gas, which is used to provide ion bombardment of the surface being etched, and which is preferably argon. The present invention provides a clean, fast method for plasma etching indium tin oxide. The method of the invention is particularly useful for etching a semiconductor device film stack which includes at least one layer of a material that would be adversely affected by exposure to hydrogen, such as N- or P-doped silicon.
    Type: Grant
    Filed: March 4, 1999
    Date of Patent: April 9, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Ajay Kumar, Padmapani Nallan, Jeffrey D. Chinn
  • Patent number: 6368518
    Abstract: A method for removing an iridium- and/or rhodium-containing material from a substrate, such as a semiconductor-based substrate, is provided. The method includes providing a substrate having an exposed iridium- and/or rhodium-containing material and exposing the substrate to a composition that includes at least one halogen-containing gas, whereby at least a portion of the exposed iridium- and/or rhodium-containing material is removed from the substrate.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: April 9, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Brian A. Vaartstra
  • Patent number: 6365235
    Abstract: A surface treatment method wherein one or more active particle streams are generated and aimed at a surface to be treated so that the particle stream interacts therewith. The active particle stream consists of activated particles forming chemically active sites on the surface, and modifying particles occupying said sites. The energy of the activated particles is greater than the energy at break of the inhibited surface bonds of the surface, and lower than the radiative flaw formation energy on the surface. The strength of the particle stream at the treated surface is greater than a quantity N/t where N is the surface density of the inhibited bonds to be broken and t is the duration of exposure of any point on the treated surface to the stream. A device for carrying out the method is also provided.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: April 2, 2002
    Assignee: TePla AG
    Inventors: Pavel Koulik, Evgenia Zorina
  • Patent number: 6350699
    Abstract: A method of anisotropically etching metals, especially iridium, platinum, ruthenium, osmium, and rhenium using a non-chlorofluorocarbon, fluorine-based chemistry. A substrate having metal deposited thereon, is inserted into an ECR plasma etch chamber and heated. A fluorine containing gas, such as, carbon tetrafluoride (CF4), nitrogen trifluoride (NF3) or sulfur hexafluoride (SF6) is introduced into the chamber and ionized to form a plasma. Fluorine ions within the plasma strike, or contact, the metal to form volatile metal-fluorine compounds. The metal-fluorine compounds are exhausted away from the substrate to reduce, or eliminate, redeposition of etch reactants.
    Type: Grant
    Filed: May 30, 2000
    Date of Patent: February 26, 2002
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jer-shen Maa, Fengyan Zhang
  • Publication number: 20020011463
    Abstract: A method for removing from a microelectronic device structure a noble metal residue including at least one metal selected from the group consisting of platinum, palladium, iridium and rhodium, by contacting the microelectronic device structure with a cleaning gas including a reactive halide composition, e.g., XeF2, SF6, SiF4, Si2F6 or SiF3 and SiF2 radicals. The method may be carried out in a batch-cleaning mode, in which fresh charges of cleaning gas are successively introduced to a chamber containing the residue-bearing microelectronic device structure. Each charge is purged from the chamber after reaction with the residue, and the charging/purging is continued until the residue has been at least partially removed to a desired extent. Alternatively, the cleaning gas may be continuously flowed through the chamber containing the microelectronic device structure, until the noble metal residue has been sufficiently removed.
    Type: Application
    Filed: January 24, 2001
    Publication date: January 31, 2002
    Applicant: Advanced Technology Materials, Inc.
    Inventors: Peter C. Van Buskirk, Frank DiMeo, Peter S. Kirlin, Thomas H. Baum
  • Publication number: 20020011461
    Abstract: The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound and at least one oxidizing agent. The concentration of the oxidizing agent is thereby set higher than the concentration of the halogen compound.
    Type: Application
    Filed: June 4, 2001
    Publication date: January 31, 2002
    Inventors: Stephan Wege, Kerstin Krahl
  • Publication number: 20020011465
    Abstract: The present invention is directed to a method of etching a compound metal oxide film containing plural kinds of metallic element, such as Ba, Sr, Ti or the like. A first cleaning step employing Cl2 gas is carried out in order to remove alkaline earth metal (Ba, Sr) from the film, then a second cleaning step employing ClF3 gas is carried out in order to remove a metal (Ti) other than the alkaline earth metal from the film. The etching method is applicable not only to the etching process in the semiconductor manufacturing but also to the cleaning process for cleaning the processing vessel for film deposition.
    Type: Application
    Filed: May 25, 2001
    Publication date: January 31, 2002
    Inventors: Hiroyuki Yamamoto, Kazuaki Nishimura, Kazuhide Hasebe, Phillip Spaull
  • Publication number: 20020008079
    Abstract: A dry etching method for an iridium electrode, wherein the dry etching method includes depositing an iridium metal film on a substrate, forming a photoresist mask on the metal film in a predetermined pattern, etching the metal film which is not covered with the photoresist mask in the predetermined pattern by generating plasma using an etch gas containing an inert gas and fluorine-based gas, and removing the photoresist mask. Accordingly, no etch residues remain even if a photoresist is used as an etch mask, and it is not necessary to heat a substrate to a high temperature. In addition, since the selectivity of an iridium electrode with respect to a photoresist mask can be increased, an iridium electrode having a satisfactory etch profile can be formed.
    Type: Application
    Filed: March 9, 2001
    Publication date: January 24, 2002
    Inventor: Chee-won Chung
  • Publication number: 20020008083
    Abstract: In a dry etching method for etching a structure obtained by successively depositing, on a substrate, a gate insulating film, a silicon base film, a tungsten film or an alloy film containing tungsten, the dry etching includes a first process of dry-etching the tungsten film or the alloy film including tungsten, and a second process of dry-etching the silicon base film, and the first process employs, as an etching gas, a gas mixture obtained by mixing O2 gas into a gas including at least C and F, with the flow ratio of the O2 gas being 10˜50% by volume percentages. This dry etching method realizes highly-precise dry etching by which a vertical configuration of the poly-metal structure is obtained, and the selection ratio of W with respect to poly-Si can be controlled and, moreover, penetration through the underlying gate oxide film is prevented.
    Type: Application
    Filed: July 6, 2001
    Publication date: January 24, 2002
    Inventor: Tetsuya Matsutani
  • Patent number: 6334856
    Abstract: Microneedle devices are provided for transport of therapeutic and biological molecules across tissue barriers and for use as microflameholders. In a preferred embodiment for transport across tissue, the microneedles are formed of a biodegradable polymer. Methods of making these devices, which can include hollow and/or porous microneedles, are also provided. A preferred method for making a microneedle includes forming a micromold having sidewalls which define the outer surface of the microneedle, electroplating the sidewalls to form the hollow microneedle, and then removing the micromold from the microneedle. In a preferred method of use, the microneedle device is used to deliver fluid material into or across a biological barrier from one or more chambers in fluid connection with at least one of the microneedles. The device preferably further includes a means for controlling the flow of material through the microneedles.
    Type: Grant
    Filed: May 21, 1999
    Date of Patent: January 1, 2002
    Assignee: Georgia Tech Research Corporation
    Inventors: Mark G. Allen, Mark R. Prausnitz, Devin V. McAllister, Florent Paul Marcel Cros
  • Publication number: 20010054599
    Abstract: The method deals with plasma-structuring by etching, in particular with the plasma-structuring of materials at high temperatures. The application of a chemical etching process at high temperatures is made possible by the prior deposition of a polyimide mask.
    Type: Application
    Filed: May 21, 2001
    Publication date: December 27, 2001
    Inventors: Manfred Engelhardt, Volker Weinrich, Carlos Mazure-Espejo
  • Publication number: 20010054600
    Abstract: A method and apparatus are provided for simulating a standard wafer in semiconductor manufacturing equipment. The apparatus includes a support layer suitable for being handled by the semiconductor manufacturing equipment. Applied to the support layer is a mixture including a process agent and a material. During use, the present invention simulates a standard production wafer including material similar to that in the mixture of the present invention.
    Type: Application
    Filed: August 6, 2001
    Publication date: December 27, 2001
    Inventors: Gregory J. Goldspring, Robert J. O'Donnell