Silicon Containing Substrate Is Glass Patents (Class 216/80)
  • Patent number: 7955440
    Abstract: After a water film is formed on a wafer front surface in a chamber, the water film is supplied sequentially with an oxidizing component of an oxidation gas, an organic acid component of an organic acid mist, an HF component of an HF gas, the organic acid mist, and the oxidizing component of the oxidation gas. As a result, the HF component and the organic acid component provide cleaning effect on the wafer surface, and a concentration of the cleaning components in the water film within a wafer surface can be even.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Sumco Corporation
    Inventors: Shigeru Okuuchi, Kazushige Takaishi
  • Patent number: 7931820
    Abstract: A dry etching gas that comprises a compound having a CF3CF fragment directly bonded to a double bond (provided that the compound is exclusive of CF3CF?CFCF?CF2). Said dry etching gas permits the formation of a pattern such as a contact hole with a high aspect ratio.
    Type: Grant
    Filed: September 5, 2001
    Date of Patent: April 26, 2011
    Assignee: Daikin Industries, Ltd.
    Inventors: Masataka Hirose, Shingo Nakamura, Mitsushi Itano, Hirokazu Aoyama
  • Patent number: 7914693
    Abstract: The present invention relates to a micro/nano imprint lithography technique and in particular, to a stamp that is used in an UV-micro/nano imprint lithography process or thermal micro/nano imprint lithography process and a method for fabricating the stamp. The method for fabricating a stamp for micro/nano imprint lithography of the present invention includes i) depositing a thin film of diamond-like carbon on a substrate, ii) applying resist on the diamond-like carbon thin film, iii) patterning the resist, iv) etching the diamond-like carbon thin film by using the resist as a protective layer, and v) removing the resist.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: March 29, 2011
    Assignee: Korea Institute of Machinery & Materials
    Inventors: Jun-Ho Jeong, Young-Suk Sim, Ki-Don Kim, Dae-Geun Choi, Eung-Sug Lee
  • Patent number: 7902080
    Abstract: Methods of filling a gap on a substrate with silicon oxide are described. The methods may include the steps of introducing an organo-silicon precursor and an oxygen precursor to a deposition chamber, reacting the precursors to form a first silicon oxide layer in the gap on the substrate, and etching the first silicon oxide layer to reduce the carbon content in the layer. The methods may also include forming a second silicon oxide layer on the first layer, and etching the second layer to reduce the carbon content in the second layer. The silicon oxide layers are annealed after the gap is filled.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: March 8, 2011
    Assignee: Applied Materials, Inc.
    Inventors: Xiaolin Chen, Srinivas D. Nemani, Shankar Venkataraman
  • Patent number: 7854853
    Abstract: An exemplary embodiment of the present invention provides a nano fabrication method for a glass, the method including forming a molecule substituting layer on a glass substrate, patterning the molecule substituting layer correspondent to shapes to be patterned on the glass substrate, substituting crystal atoms of the glass substrate with atoms of the molecule substituting layer, removing the patterned molecule substituting layer from the glass substrate, and etching the molecule substituted portion of the glass substrate.
    Type: Grant
    Filed: November 9, 2006
    Date of Patent: December 21, 2010
    Assignee: Postech Academy-Industry Foundation
    Inventors: Pan-Kyeom Kim, Geun-Bae Lim
  • Patent number: 7850863
    Abstract: A process for fabricating a hydrogenated amorphous silicon carbide film having through-pores includes the formation on a substrate of a film consisting of an amorphous hydrogenated silicon carbide matrix in which silicon oxide nanowires are dispersed therethrough, and then the selective destruction by a chemical agent of the silicon oxide nanowires present in the film formed at step a). Applications include microelectronics and micro-technology, in all fabrication processes that involve the degradation of a sacrificial material by diffusion of a chemical agent through a film permeable to this agent for the production of air gaps, in particular the fabrication of air-gap interconnects for integrated circuits.
    Type: Grant
    Filed: January 14, 2009
    Date of Patent: December 14, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventor: Aziz Zenasni
  • Patent number: 7845063
    Abstract: A method for manufacturing a quartz crystal unit comprises forming a quartz crystal tuning fork resonator that is capable of vibrating in a flexural mode of an inverse phase and that has a quartz crystal tuning fork base, and first and second quartz crystal tuning fork tines connected to the quartz crystal tuning fork base. An electrode is disposed on each of two of side surfaces of each of the first and second quartz crystal tuning fork tines so that the electrodes of the first quartz crystal tuning fork tine have an electrical polarity opposite to an electrical polarity of the electrodes of the second quartz crystal tuning fork tine, a motional capacitance C1 of a fundamental mode of vibration of the quartz crystal tuning fork resonator being greater than a motional capacitance C2 of a second overtone mode of vibration thereof.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: December 7, 2010
    Assignee: Piedek Technical Laboratory
    Inventor: Hirofumi Kawashima
  • Patent number: 7845064
    Abstract: A control apparatus and method for controlling an image display includes at least one reference object for generating a predetermined spectrum signal, a modulation unit for modulating the predetermined spectrum signal with a predetermined method, and a remote controller. The remote controller includes an image sensor for receiving the modulated predetermined spectrum signal and generating a digital signal and a processing unit for receiving the digital signal, demodulating the digital signal, and calculating an image variation of the image of the reference object formed on the digital image.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: December 7, 2010
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Jang Ho Park, Tae Hoon Kim, Jong Yeol Jeon
  • Patent number: 7838434
    Abstract: A method of etching high dielectric constant materials using a halogen gas, a reducing gas and an etch rate control gas chemistry.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: November 23, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Guangxiang Jin, Padmapani Nallan, Ajay Kumar
  • Patent number: 7803280
    Abstract: The invention provides a method in which waviness generated on a glass substrate surface during pre-polishing is removed, thereby finishing the glass substrate to have a surface excellent in flatness. The method for finishing a pre-polished glass substrate uses ion beam etching, gas cluster ion beam etching or plasma etching, the method including: a step of measuring flatness of the glass substrate surface using a shape measurement unit, and a step of measuring a concentration distribution of the dopant contained in the glass substrate. Processing conditions of the glass substrate surface are set up for each site of the glass substrate based on the results obtained from the step of measuring flatness and the step of measuring a concentration distribution of the dopant. Finishing includes keeping an angle formed by a normal line of the glass substrate and an incident beam onto the glass substrate at from 30° to 89°.
    Type: Grant
    Filed: June 1, 2009
    Date of Patent: September 28, 2010
    Assignee: Asahi Glass Company, Limited
    Inventors: Koji Otsuka, Kenji Okamura
  • Patent number: 7790049
    Abstract: A process for producing a structure containing silicon oxide includes a step of forming a first layer of organic spin-on glass on a substrate and a step of forming a second layer of inorganic spin-on glass on the first layer. Thereafter, the first layer is etched by using a pattern formed on the second layer as a mask and then the first layer and the second layer are calcined to prepare the structure containing silicon oxide.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: September 7, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Atsunori Terasaki, Junichi Seki, Toshiki Ito
  • Patent number: 7771603
    Abstract: A process for polishing a glass substrate, which enables to polish a glass substrate having a large waviness formed by mechanical polishing, to have a surface excellent in flatness, is provided. A process for polishing a glass substrate, comprising a step of measuring the surface profile of a mechanically polished glass substrate to identify the width of waviness present in the glass substrate, and a step of applying dry etching using a beam having a beam size in FWHM (full width of half maximum) value of at most the above size of waviness, to polish the surface of the glass substrate.
    Type: Grant
    Filed: July 18, 2007
    Date of Patent: August 10, 2010
    Assignee: Asahi Glass Company, Limited
    Inventors: Koji Otsuka, Masabumi Ito, Hiroshi Kojima
  • Patent number: 7718079
    Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: May 18, 2010
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Chien Liu, Ta-Shan Tseng, Wen Bin Shieh, Juan-Yuan Wu, Water Lur, Shih-Wei Sun
  • Patent number: 7718080
    Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation. In one example an electron beam array such as a carbon nanotube array is used to selectively expose a surface during a processing operation.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: May 18, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Neal R. Rueger, Mark J. Williamson, Gurtej S. Sandhu
  • Patent number: 7670496
    Abstract: A structural body comprising a substrate and a structural layer formed on the substrate through an air gap in which the structural layer functions as a micro movable element is produced by a process comprising a film-deposition step of successively forming a sacrificial layer made of a silicon oxide film and the structural layer on the substrate, an air gap-forming step of removing the sacrificial layer by etching with a treating fluid to form the air gap between the substrate and the structural layer, and a cleaning step. By using a supercritical carbon dioxide fluid containing a fluorine compound, a water-soluble organic solvent and water as the treating fluid, the sacrificial layer is removed in a short period of time with a small amount of the treating fluid without any damage to the structural body.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: March 2, 2010
    Assignees: SONY Corporation, Mitsubishiki Gas Chemical Company, Inc.
    Inventors: Koichiro Saga, Hiroya Watanabe, Tomoyuki Azuma
  • Patent number: 7644490
    Abstract: A method of forming an actuator and a relay using a micro-electromechanical (MEMS)-based process is disclosed. The method first forms the lower sections of a square copper coil, and then forms an actuation member that includes a core section and a horizontally adjacent floating cantilever section. The core section, which lies directly over the lower coil sections, is electrically isolated from the lower coil sections. The method next forms the side and upper sections of the coil, along with first and second electrodes that are separated by a switch gap. The first electrode lies directly over an end of the core section, while the second electrode lies directly over an end of the floating cantilever section.
    Type: Grant
    Filed: May 25, 2007
    Date of Patent: January 12, 2010
    Assignee: National Semiconductor Corporation
    Inventors: Trevor Niblock, Peter Johnson
  • Patent number: 7641806
    Abstract: By steps of forming first masks 13, 14 each having a first pattern on a first surface of a substrate 11 on which a membrane is to be formed, etching the first surface of the substrate 11 by using the first masks 13, 14 to forming first support beams 15, positioning a second surface of the substrate 11 on the basis of the first pattern on the first surface, forming a second mask 17 having a second pattern on the second surface of the substrate 11 based on the alignment and etching the second surface of the substrate 11 in dry by using the second mask 17 to form the second support beams 20, a membrane member 22a where the first and second support beams 15, 20 are formed on both surfaces of the membrane 12 is manufactured. Consequently, it is possible to provide the membrane member that is sufficient in strength and is hard to be deformed by heat.
    Type: Grant
    Filed: June 10, 2004
    Date of Patent: January 5, 2010
    Assignees: Tokyo Electron Limited, OCTEC Inc.
    Inventors: Katsuya Okumura, Kazuya Nagaseki, Naoyuki Satoh, Koji Maruyama
  • Patent number: 7618895
    Abstract: A method for etching doughnut-type glass substrates, which comprises laminating a plurality of doughnut-type glass substrates each having a circular hole at its center so that the circular holes form a cylindrical hole, and applying an etching treatment to inner peripheral edge surfaces of the plurality of the laminated doughnut-type glass substrates all at once by means of an etching liquid or an etching gas, wherein the etching liquid or the etching gas is supplied from one end of the cylindrical hole, made to flow in the cylindrical hole, and discharged from the other end of the cylindrical hole so that it is not in contact with exposed main surfaces of the doughnut-type glass substrates at both ends of the laminate consisting of the doughnut-type glass substrates.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: November 17, 2009
    Assignee: Asahi Glass Company, Limited
    Inventors: Osamu Miyahara, Masami Kaneko
  • Publication number: 20090261066
    Abstract: The present invention herein provides an apparatus and a method for dry etching, which can solve such a problem that an object to be processed undergoes cracking during the etching procedures due to the heat deformation thereof and thermal shocks, possibly encountered when subjecting, to dry etching procedures, the object having a high thermal expansion coefficient. A dry etching apparatus is provided with an electrode structure having a convex-shaped surface, the convex-shape is one concentric with the cross section of the electrode structure and the height thereof falls within the range of from 0.2 to 1.0 mm. An object consisting of a material having a thermal expansion coefficient of not less than 30×10?7/° C. is subjected to dry etching while using the foregoing dry etching apparatus.
    Type: Application
    Filed: September 5, 2007
    Publication date: October 22, 2009
    Applicant: ULVAC, INC
    Inventors: Yasuhiro Morikawa, Koukou Suu
  • Patent number: 7596851
    Abstract: The shape of a crotch portion of a tuning fork of a quartz piece is controlled such that main surfaces of two sheets of original plates, which are made of quartz crystal and the main surfaces thereof are orthogonal to the direction of the Z axis, which is a crystal axis, are bonded so that the plus/minus directions of the X axis, which is another crystal axis, are made in a reverse relation to each other to form a quartz substrate, and masks for forming the outer shape, through which the surfaces of the quartz substrate are exposed, are formed on both front and back surfaces of the quartz substrate in a manner that the mask follows along the outer shape of the quartz piece and the width direction of the outer shape agrees with the X axis, and the quartz substrate is etched to form the outer shape of the quartz piece.
    Type: Grant
    Filed: October 29, 2007
    Date of Patent: October 6, 2009
    Assignee: Nihon Dempa Kogyo Co., Ltd.
    Inventor: Takehiro Takahashi
  • Patent number: 7591958
    Abstract: The manufacturing of electronic components on individual substrates made of an insulating material includes molding, in a silicon wafer, an insulating material with a thickness corresponding to the final thickness desired for the substrates, manufacturing the electronic components, and removing the silicon from the rear surface of the wafer after manufacturing of the components.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: September 22, 2009
    Assignee: STMicroelectronics SA
    Inventors: Pascal Gardes, Fabrice Guitton
  • Patent number: 7585422
    Abstract: A new and improved optical element manufacturing method, through which lens elements can be efficiently mounted on a silicon V-shaped groove substrate at lower manufacturing costs, is provided. The method comprises a lens element forming step in which an oxide layer 104 is formed at a supporting layer 102 and lens elements 120 are formed at the upper surface of the silicon oxide film, a coating step in which a solder connection metal film is coated onto the side surfaces of the lens elements and a separating step in which the lens elements are separated by removing the silicon oxide film. Through this method, the solder connection metal film can be formed with ease at the sidewalls of the lens elements. The lens elements with the solder connection metal film formed at the side walls thereof can easily be soldered onto a supporting substrate.
    Type: Grant
    Filed: March 14, 2006
    Date of Patent: September 8, 2009
    Assignee: Oki Electric Industry Co., Ltd.
    Inventors: Yoshinori Maeno, Daisuke Shimura
  • Publication number: 20090215156
    Abstract: The present invention relates to a method of fabricating a nanogap and a nanogap sensor, and to a nanogap and a nanogap sensor fabricated using the method. The present invention relates to a method of fabricating a nanogap and a nanogap sensor, which can be realized by an anisotropic etching using a semiconductor manufacturing process. According to the method of present invention, the nanogap and nanogap sensor can be simply and cheaply produced in large quantities.
    Type: Application
    Filed: September 5, 2006
    Publication date: August 27, 2009
    Inventors: Bong hyun Chung, Sang kyu Kim, Hye Jung Park
  • Patent number: 7578943
    Abstract: A loss in the rigidity of a substrate for a liquid discharge head having nozzles at a high density can be suppressed. A liquid discharge head includes plural pressure generating chambers respectively provided with pressure generating elements, plural nozzle apertures respectively communicating with the plural pressure generating chambers and adapted to discharge a liquid, and a reservoir with which the plural pressure generating chambers commonly communicate respectively through communicating parts. The pressure generating chambers and the reservoir respectively have recessed portions formed respectively on one and the other of two principal planes of the same substrate, and the reservoir contains a portion shallower than a portion within the reservoir that communicates with the pressure generating chambers.
    Type: Grant
    Filed: May 19, 2006
    Date of Patent: August 25, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Rei Kurashima, Takashi Ushijima, Koichiro Nakanishi
  • Publication number: 20090194507
    Abstract: The present invention relates to a device for cleaning, etching, activation and subsequent treatments of glass surfaces, glass surfaces coated with metal oxides or with organic material layers, SiO2-layer coated materials, and SiO2-layer coated materials with an organic material surface coating by effects of an electrical plasma layer. The invention disclosed herein includes at least one electrode system (1) consisting of at least two electrodes (2) and (3) situated inside of a dielectric body (4). An electrical plasma layer is generated preferably at atmospheric gas pressure, and preferably above the electrodes (2) and (3) situated on the same side of the treated glass, metal oxide coated glass, other SiO2-coated materials and SiO2-coated materials with a layer of organic material (5) and which are energized by an alternating or pulsed electrical voltage applied between them.
    Type: Application
    Filed: June 7, 2007
    Publication date: August 6, 2009
    Applicant: Faculty of Mathematics Physics and Informatics Comenius University
    Inventor: Mirko Cernak
  • Publication number: 20090197049
    Abstract: The invention relates to a method for dry chemical treatment of substrates selected from the group comprising silicon, ceramic, glass, and quartz glass, in which the substrate is treated in a heated reaction chamber with a gas which contains hydrogen chloride as etching agent, and also to a substrate which can be produced in this way. The invention likewise relates to uses of the previously mentioned method.
    Type: Application
    Filed: December 6, 2006
    Publication date: August 6, 2009
    Inventors: Stefan Reber, Gerhard Willeke
  • Publication number: 20090166330
    Abstract: A method of etching a device in one embodiment includes providing a silicon carbide substrate, forming a silicon nitride layer on a surface of the silicon carbide substrate, forming a silicon carbide layer on a surface of the silicon nitride layer, forming a silicon dioxide layer on a surface of the silicon carbide layer, forming a photoresist mask on a surface of the silicon dioxide layer, and etching the silicon dioxide layer through the photoresist mask.
    Type: Application
    Filed: December 31, 2007
    Publication date: July 2, 2009
    Applicant: Robert Bosch GmbH
    Inventor: Gary Yama
  • Patent number: 7547635
    Abstract: A process of etching openings in a dielectric layer includes supporting a semiconductor substrate in a plasma etch reactor, the substrate having a dielectric layer and a patterned photoresist and/or hardmask layer above the dielectric layer; supplying to the plasma etch reactor an etchant gas comprising (a) a fluorocarbon gas (CxFyHz, where x?1, y?1, and z?0), (b) a silane-containing gas, hydrogen or a hydrocarbon gas (CxHy, where x?1 and y?4), (c) an optional oxygen-containing gas, and (d) an optional inert gas, wherein the flow rate ratio of the silane-containing gas to fluorocarbon gas is less than or equal to 0.1, or the flow rate ratio of the hydrogen or hydrocarbon gas to fluorocarbon gas is less than or equal to 0.5; energizing the etchant gas into a plasma; and plasma etching openings in the dielectric layer with enhanced photoresist/hardmask to dielectric layer selectivity and/or minimal photoresist distortion or striation.
    Type: Grant
    Filed: June 14, 2002
    Date of Patent: June 16, 2009
    Assignee: Lam Research Corporation
    Inventors: Aaron Eppler, Mukund Srinivasan, Robert Chebi
  • Patent number: 7531104
    Abstract: A method of making micro-optic elements. In one embodiment, photo-resist elements each having predetermined dimensions are transferred onto a substrate. The photo-resist elements are exposed to a reflow process to shape the top surface of the elements into a curved surface. The method also involves a reactive ion etching process having controlled parameters, such as a photo-resist depth and the selectivity between the substrate and photo-resist. A predetermined photo-resist depth and selectivity form a micro-optic element having a predetermined shape, preferably an elliptical or parabolic shape. In another aspect of the present invention, a micro-optic element is used to construct a micro-mirror for eliminating filamentation and promoting single mode operation of high-power broad area semiconductor lasers.
    Type: Grant
    Filed: March 20, 2002
    Date of Patent: May 12, 2009
    Inventor: Ruey-Jen Hwu
  • Patent number: 7528682
    Abstract: In an electronic apparatus comprising a digital display portion and first and second oscillators comprising first and second oscillating circuits, each of the first and second oscillating circuits having a resonator, an amplifier, a plurality of capacitors, and at least one resistor, a mode of vibration of the resonator of the first oscillating circuit being the same as that of the resonator of the second oscillating circuit, an output signal being output from each of the first and second oscillating circuits, the output signal of one of the first and second oscillating circuits being a clock signal for use in operation of the electronic apparatus to display time information at the digital display portion.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: May 5, 2009
    Assignee: Piedek Technical Laboratory
    Inventor: Hirofumi Kawashima
  • Patent number: 7517804
    Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.
    Type: Grant
    Filed: August 31, 2006
    Date of Patent: April 14, 2009
    Assignee: Micron Technologies, Inc.
    Inventors: Mark Kiehlbauch, Ted Taylor
  • Patent number: 7514014
    Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: April 7, 2009
    Assignee: United Microelectronics Corporation
    Inventors: Chih-Chien Liu, Ta-Shan Tseng, W. B. Shieh, J. Y. Wu, Water Lur, Shih-Wei Sun
  • Patent number: 7514283
    Abstract: There are many inventions described and illustrated herein. In one aspect, the present invention is directed to a technique of fabricating or manufacturing MEMS having mechanical structures that operate in controlled or predetermined mechanical damping environments. In this regard, the present invention encapsulates the mechanical structures within a chamber, prior to final packaging and/or completion of the MEMS. The environment within the chamber containing and/or housing the mechanical structures provides the predetermined, desired and/or selected mechanical damping. The parameters of the encapsulated fluid (for example, the gas pressure) in which the mechanical structures are to operate are controlled, selected and/or designed to provide a desired and/or predetermined operating environment.
    Type: Grant
    Filed: March 20, 2003
    Date of Patent: April 7, 2009
    Assignee: Robert Bosch GmbH
    Inventors: Aaron Partridge, Markus Lutz, Silvia Kronmueller
  • Patent number: 7510664
    Abstract: Fabrication apparatus and methods are disclosed for shaping and finishing difficult materials with no subsurface damage. The apparatus and methods use an atmospheric pressure mixed gas plasma discharge as a sub-aperture polisher of, for example, fused silica and single crystal silicon, silicon carbide and other materials. In one example, workpiece material is removed at the atomic level through reaction with fluorine atoms. In this example, these reactive species are produced by a noble gas plasma from trace constituent fluorocarbons or other fluorine containing gases added to the host argon matrix. The products of the reaction are gas phase compounds that flow from the surface of the workpiece, exposing fresh material to the etchant without condensation and redeposition on the newly created surface. The discharge provides a stable and predictable distribution of reactive species permitting the generation of a predetermined surface by translating the plasma across the workpiece along a calculated path.
    Type: Grant
    Filed: November 1, 2001
    Date of Patent: March 31, 2009
    Assignee: RAPT Industries, Inc.
    Inventor: Jeffrey W. Carr
  • Patent number: 7476623
    Abstract: In the method for microstructuring flat glass substrates a substrate surface of a glass substrate is coated with at least one structured mask layer and subsequently exposed to a chemically reactive ion etching process (RIE) with at least one chemical etching gas. In order to provide the same or a higher quality etching and etching rate even for economical types of glass the chemical etching gas is mixed with at least one noble gas, so that the proportion of sputtering etching in the ion etching process is significantly increased.
    Type: Grant
    Filed: October 4, 2005
    Date of Patent: January 13, 2009
    Assignee: Schott AG
    Inventors: Bianca Schreder, Rainer Liebald, Edgar Pawlowski, Dirk Sprenger, Dietrich Mund, Juergen Leib
  • Patent number: 7468323
    Abstract: An etching process includes providing a dielectric first film on a substrate and a sacrificial second film on the dielectric first film. A conductive structure such as a container capacitor is formed in a recess in the first and second films. The conductive structure is exposed as to its external surface by an etch process that resists destructive collapse of the conductive structure.
    Type: Grant
    Filed: February 27, 2004
    Date of Patent: December 23, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Kevin Torek, Kevin Shea, Thomas Graettinger
  • Patent number: 7427359
    Abstract: A method of preparing high capacity hydrous ruthenium oxide micro-ultracapacitors. A laser direct-write process deposits a film of hydrous ruthenium oxide in sulfuric acid under ambient temperature and atmospheric conditions. A dual laser process combining infrared and ultraviolet light is used for fabricating a complete wet electrochemical cell in a single processing step. Ultraviolet laser micromachining is used to tailor the shape and size of the deposited material into planar electrodes. The micro-ultracapacitors have improved size, weight, and cost efficiency and exhibit high specific power and high specific energy.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: September 23, 2008
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Craig B. Arnold, Alberto Pique
  • Patent number: 7425277
    Abstract: Broadly speaking, methods and an apparatus are provided for removing an inorganic material from a substrate. More specifically, the methods provide for removing the inorganic material from the substrate through exposure to a high density plasma generated using an inductively coupled etching apparatus. The high density plasma is set and controlled to isotropically contact particular regions of the inorganic material to allow for trimming and control of a critical dimension associated with the inorganic material.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: September 16, 2008
    Assignee: Lam Research Corporation
    Inventors: C. Robert Koemtzopoulos, Shibu Gangadharan, Chris G. N. Lee, Alan Miller
  • Patent number: 7412764
    Abstract: In a method for manufacturing a quartz crystal unit, a quartz crystal tuning fork resonator is formed by etching a quartz crystal wafer to form a quartz crystal tuning fork base and first and second quartz crystal tuning fork tines connected to the quartz crystal tuning fork base. The quartz crystal tuning fork resonator has a piezoelectric constant e?12 within a range of 0.12 C/m2 to 0.19 C/m2 in the absolute value to drive the quartz crystal tuning fork resonator. An electrode is disposed on each of two of side surfaces of each of the first and second quartz crystal tuning fork tines so that the electrodes disposed on the side surfaces of the first quartz crystal tuning fork tine have an electrical polarity opposite to an electrical polarity of the electrodes disposed on the side surfaces of the second quartz crystal tuning fork tine. The quartz crystal tuning fork resonator is mounted on a mounting portion of a case.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: August 19, 2008
    Assignee: Piedek Technical Laboratory
    Inventor: Hirofumi Kawashima
  • Patent number: 7402255
    Abstract: A micro-electro-mechanical system (MEMS) device includes a mirror having a top surface with trenches, a beam connected to the mirror, rotational comb teeth connected to the beam, and one or more springs connecting the beam to a bonding pad. The mirror can have a bottom surface for reflecting light. The mirror can include a top flange and a bottom flange joined by a web, wherein the top and the bottom flanges form the top and the bottom surfaces, respectively. The rotational comb teeth can have a tapered shape. Stationary comb teeth can be interdigitated with the rotational comb teeth either in-plane or out-of-plane. Steady or oscillating voltage difference between the rotational and the stationary comb teeth can be used to oscillate or tune the mirror.
    Type: Grant
    Filed: March 7, 2006
    Date of Patent: July 22, 2008
    Assignee: Advanced NuMicro Systems, Inc.
    Inventor: Yee-Chung Fu
  • Patent number: 7393795
    Abstract: Methods for post-etch deposition on a dielectric film are provided in the present invention. In one embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in a etch reactor, etching the low-k dielectric layer in the etch reactor, and forming a protection layer on the etched low-k dielectric layer. In another embodiment, the method includes providing a substrate having a low-k dielectric layer disposed thereon in an etch reactor, etching the low-k dielectric layer in the reactor, bonding the etched low-k dielectric layer with a polymer gas supplied into the reactor, forming a protection layer on the etched low-k dielectric layer, and removing the protection layer formed on the etched low-k dielectric layer.
    Type: Grant
    Filed: February 1, 2006
    Date of Patent: July 1, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Robin Cheung, Siyi Li
  • Patent number: 7361285
    Abstract: A method for fabricating a cliché including: providing a transparent glass substrate; depositing a metal layer on the substrate; patterning the metal layer and thereby forming a first metal pattern; etching the glass substrate by using the first metal pattern as a mask and thereby forming a first convex pattern; patterning the first metal pattern and thereby forming a second metal pattern; and etching the first convex pattern by using the second metal pattern as a mask and thereby forming a second convex pattern.
    Type: Grant
    Filed: April 26, 2005
    Date of Patent: April 22, 2008
    Assignee: LG.Philips LCD Co., Ltd.
    Inventor: Chul-Ho Kim
  • Patent number: 7354526
    Abstract: A processing method for glass substrate of the present invention includes: applying heat and external force to a glass substrate and then cooling it down to thereby form a compression stressed part having a different etching rate from that of other parts with respect to an etching reagent to be used, on the surface of the glass substrate and in the vicinity thereof, and performing chemical etching using the etching reagent on the glass substrate having the compression stressed part formed thereon, so as to form a relief on the surface of the glass substrate.
    Type: Grant
    Filed: November 19, 2004
    Date of Patent: April 8, 2008
    Assignees: Olympus Corporation, Nippon Sheet Glass Co., Ltd.
    Inventors: Takeshi Hidaka, Hiroaki Kasai, Masamichi Hijino, Yasushi Nakamura, Akihiro Koyama, Keiji Tsunetomo, Junji Kurachi, Hirotaka Koyo, Shinya Okamoto, Yasuhiro Saito
  • Publication number: 20080078743
    Abstract: A temperature-controlled substrate holder having a high temperature substrate chuck is mounted within a chemical treatment chamber. The temperature-controlled substrate holder secures a substrate and maintains the substrate at a temperature that ranges from about 10° C. up to about 150° C. during execution of a chemical oxide removal process.
    Type: Application
    Filed: September 28, 2006
    Publication date: April 3, 2008
    Inventors: Andres F. Munoz, Siddhartha Panda, Michael R. Sievers, Richard Wise
  • Patent number: 7351347
    Abstract: GaN crystal having few dislocations is grown by using together ELO-mask and defect-seeding-mask means. ELO masks make it so that GaN crystal does not grow directly, but grows laterally; defect-seeding masks make it so that closed defect-gathering regions in which defects are concentrated are grown. Any of the materials SiN, SiON or SiO2 is utilized for the ELO mask, while any of the materials Pt, Ni or Ti is utilized for the defect-seeding masks. With a sapphire, GaAs, spinel, Si, InP, SiC, etc. single-crystal substrate, or one in which a GaN buffer layer is coated onto a single-crystal substrate of these, as an under-substrate, the ELO mask and defect-seeding masks are provided complementarily and GaN is vapor-phase deposited.
    Type: Grant
    Filed: January 23, 2003
    Date of Patent: April 1, 2008
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Katsushi Akita, Takuji Okahisa
  • Patent number: 7346981
    Abstract: A process for fabricating a MEMS device comprises the steps of depositing and patterning on one side of a wafer a layer of material having a preselected electrical resistivity; bonding a substrate to the one side of the wafer using an adhesive bonding agent, the substrate overlying the patterned layer of material; selectively removing portions of the wafer from the side opposite the one side to define stationary and movable MEMS elements; and selectively removing the adhesive bonding agent to release the movable MEMS element, at least a portion of the layer of material being disposed so as to be attached to the movable MEMS element.
    Type: Grant
    Filed: June 2, 2003
    Date of Patent: March 25, 2008
    Assignee: Teledyne Licensing, LLC
    Inventors: Robert L. Borwick, III, Philip A. Stupar, Jeffrey F. DeNatale, Jun J. Yao, Sangtae Park
  • Patent number: 7341952
    Abstract: A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: March 11, 2008
    Assignee: Nanya Technology Corporation
    Inventors: Kaan-Lu Tzou, Tzu-Ching Tsai, Yi-Nan Chen
  • Patent number: 7335600
    Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is then subjected to a surface treatment that provides sufficient energy for the extra electrons caused by the ashing process to escape from the substrate, and the remaining photoresist and polymer are stripped with stripping solvents after the surface treatment.
    Type: Grant
    Filed: December 15, 2004
    Date of Patent: February 26, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Wen-Sheng Chien, Yen-Wu Hsieh
  • Patent number: 7316785
    Abstract: In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma processing chamber, wherein the pre-coat gas mixture has an affinity for a etchant gas flow mixture; striking a first plasma from the pre-coat gas mixture; and introducing a substrate comprising the substrate material. The method also includes flowing the etchant gas mixture into the plasma processing chamber; striking a second plasma from the etchant gas mixture; and etching the substrate with the second plasma. Wherein the first plasma creates a pre-coat residual on a set of exposed surfaces in the plasma processing chamber, and the etch resistance of the substrate material is maintained.
    Type: Grant
    Filed: June 30, 2004
    Date of Patent: January 8, 2008
    Assignee: Lam Research Corporation
    Inventors: Yoko Yamaguchi Adams, George Stojakovic, Alan Miller
  • Patent number: 7311852
    Abstract: A semiconductor manufacturing process wherein a low-k dielectric layer is plasma etched with selectivity to an overlying mask layer. The etchant gas can be oxygen-free and include a fluorocarbon reactant, a nitrogen reactant and an optional carrier gas, the fluorocarbon reactant and nitrogen reactant being supplied to a chamber of a plasma etch reactor at flow rates such that the fluorocarbon reactant flow rate is less than the nitrogen reactant flow rate. The etch rate of the low-k dielectric layer can be at least 5 times higher than that of a silicon dioxide, silicon nitride, silicon oxynitride or silicon carbide mask layer. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.
    Type: Grant
    Filed: March 30, 2001
    Date of Patent: December 25, 2007
    Assignee: Lam Research Corporation
    Inventors: Si Yi Li, Helen H. Zhu, S. M. Reza Sadjadi, James V. Tietz, Bryan A. Helmer