Silicon Containing Substrate Is Glass Patents (Class 216/80)
  • Patent number: 7247252
    Abstract: A method for avoiding plasma arcing during a reactive ion etching (RIE) process including providing a semiconductor wafer having a process surface for depositing a dielectric insulating layer; depositing at least a portion of a dielectric insulating layer to form a deposition layer according to plasma assisted chemical vapor deposition (CVD) process; treating the deposition layer portion with a hydrogen plasma treatment to reduce an electrical charge nonuniformity of the deposition layer including applying a biasing power to the semiconductor wafer; and, carrying out a subsequent reactive ion etching process.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: July 24, 2007
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chyang Pan, Yu-Chun Huang, Shwangming Jing
  • Patent number: 7201852
    Abstract: A method for eliminating eruptions, impurities, and/or damage in a crystal lattice by selectively etching silicon elements of surface-plated and sawn-out parts of a silicon wafer. At least areas of the silicon elements are brought into contact with a gaseous etching medium that etches silicon selectively in a chemical reaction, and gaseous reaction products are produced during etching. An interhalogen or fluorine-noble gas compound that is in a gaseous state or was converted to the gaseous phase may be used as the etching medium. The method is believed to be suitable for producing power diodes sawn from a wafer or for overetching fully mounted individual diodes.
    Type: Grant
    Filed: April 26, 2000
    Date of Patent: April 10, 2007
    Assignee: Robert Bosch GmbH
    Inventors: Richard Spitz, Helga Uebbing, Doerte Eimers-Klose, Franz Laermer, Andrea Schilp
  • Patent number: 7118683
    Abstract: The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or more elements selected from Group VIII of the periodic table is provided within a reaction chamber; and a substrate is provided within the reaction chamber. The substrate has both a silicon-oxide-containing composition and at least one organic substance thereover. The silicon-oxide-containing composition is plasma etched within the reaction chamber. The plasma etching of the silicon-oxide-containing composition has increased selectivity for the silicon oxide of the composition relative to the at least one organic substance than would plasma etching conducted without the material in the chamber. The invention also encompasses a plasma reaction chamber assembly. The assembly comprises at least one interior wall, and at least one liner along the at least one interior wall. The liner comprises one or more of Ru, Fe, Co, Ni, Rh, Pd, Os, W, Ir, Pt and Ti.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: October 10, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Max F. Hineman, Li Li
  • Patent number: 7098137
    Abstract: A method of making a micro corner cube array includes the steps of: providing a substrate, at least a surface portion of which consists of cubic single crystals and which has a surface that is substantially parallel to {111} planes of the crystals; and dry-etching the surface of the substrate anisotropically with an etching gas that is reactive with the substrate, thereby forming a plurality of unit elements of the micro corner cube array on the surface of the substrate. Each of the unit elements is made up of a number of crystal planes that have been etched at a lower etch rate than the {111} planes of the crystals.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: August 29, 2006
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Ichiro Ihara, Kiyoshi Minoura, Yutaka Sawayama
  • Patent number: 7094670
    Abstract: A method of performing plasma immersion ion implantation on a workpiece in a plasma reactor chamber, includes placing the workpiece on a workpiece support in the chamber, controlling a temperature of the wafer support near a constant level, performing plasma immersion ion implantation on the workpiece by introducing an implant species precursor gas into the chamber and generating a plasma while minimizing deposition and minimizing etching by holding the temperature of the workpiece within a temperature range that is above a workpiece deposition threshold temperature and below a workpiece etch threshold temperature.
    Type: Grant
    Filed: January 28, 2005
    Date of Patent: August 22, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Kenneth S. Collins, Hiroji Hanawa, Kartik Ramaswamy, Andrew Nguyen, Amir Al-Bayati, Biagio Gallo
  • Patent number: 7090782
    Abstract: A method of forming semiconductor devices on a wafer is provided. An etch layer is formed over a wafer. A photoresist mask is formed over the etch layer. The photoresist mask is removed only around an outer edge of the wafer to expose the etch layer around the outer edge of the wafer. A deposition gas is provided comprising carbon and hydrogen containing species. A plasma is formed from the deposition gas. A polymer layer is deposited on the exposed etch layer around the outer edge of the wafer, wherein the polymer is formed from the plasma from the deposition gas. The etch layer is etched through the photoresist mask, while consuming the photoresist mask and the polymer deposited on the exposed etch layer around the outer edge of the wafer.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: August 15, 2006
    Assignee: Lam Research Corporation
    Inventors: Seiji Kawaguchi, Kenji Takeshita
  • Patent number: 7083740
    Abstract: A piezoelectric member and an electrode are formed over a silicon substrate. The piezoelectric member and the electrode are patterned by photolithography. The silicon substrate is etched to form a body. A protective film is formed on at least one surface of the body. Another surface having no protective film thereon is etched to obtain a resonant device. The body is etched in its thickness direction accurately while a resonance frequency of the body is measured. The manufacturing processes allow the resonance frequency and a gap frequency of the resonant device to be adjusted to predetermined values.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: August 1, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaya Nakatani, Hirofumi Tajika
  • Patent number: 7081417
    Abstract: To provide a planarization method which does not depend upon the size and the density of a wiring pattern and in which a reliable wiring system and a Josephson device can be formed and wiring structure, an insulation layer is planarized by forming a reversal pattern mask of wiring and selectively removing the insulation layer on the wiring.
    Type: Grant
    Filed: June 24, 2004
    Date of Patent: July 25, 2006
    Assignees: Hitachi, Ltd., NEC Corporation, International Superconductivity Technology Center, the Judicial Foundation
    Inventors: Kenji Hinode, Shuichi Nagasawa, Yoshihiro Kitagawa, Mutsuo Hidaka, Keiichi Tanabe
  • Patent number: 7078334
    Abstract: According to one embodiment, a method (100) may include forming a first insulating layer over a semiconductor substrate (step 102), forming a hard mask layer (step 104), and forming a photoresist etch mask having a thickness of less than about 4,000 angstroms (step 106). Such a reduced thickness may conventionally lead to uncontrolled etching and/or may require multiple steps to ensure feature formation. A method (100) may further include etching an opening through at least one half the thickness of the hard mask layer to form a hard mask (step 108) and etching through a first insulating layer without first removing a photoresist layer (step 110). Such etching can essentially consume a photoresist layer, however controllability can be maintained as etching may continue with a hard mask in place.
    Type: Grant
    Filed: June 6, 2002
    Date of Patent: July 18, 2006
    Assignee: Cypress Semiconductor Corporation
    Inventors: Saurabh Dutta Chowdhury, Mehran Sedigh, Chan Lon Yang, Prabhu Goplana
  • Patent number: 7059335
    Abstract: In a process for treating moulds or mould halves (3) for the production of ophthalmic lenses, in particular contact lenses, the moulds or mould halves (3) are exposed to a plasma at least in the area of their shaping surfaces (310).
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: June 13, 2006
    Assignee: Novartis AG
    Inventor: Michael Rothaug
  • Patent number: 7041230
    Abstract: A semiconductor chip formed on a substrate is provided. An oxygen-doped silicon carbide etch stop layer is formed over the substrate. An organosilicate glass layer is formed over the oxygen-doped silicon carbide etch stop layer. A feature is selectively etched in the organosilicate glass layer using an etch with an organosilicate glass to oxygen-doped silicon carbide selectivity greater than 5:1.
    Type: Grant
    Filed: January 21, 2003
    Date of Patent: May 9, 2006
    Assignee: Lam Research Corporation
    Inventors: Xingcai Su, Bi Ming Yen, Peter Loewenhardt
  • Patent number: 7005079
    Abstract: Due to lights with different wavelengths having different indexes of refraction in a liquid crystal, a retardation between lights with different wavelengths occurs and causes the problem of viewing angle of the liquid crystal display. The present invention provides a manufacturing method of light-guiding apparatus of a liquid crystal display to form light-guiding pillars having a characteristic of total reflection as a fiber. The light from back light module through the light-guiding pillars enters the liquid crystal at an incident angle smaller than 150 for reducing the retardation between lights with different wavelengths.
    Type: Grant
    Filed: April 7, 2003
    Date of Patent: February 28, 2006
    Assignee: Chungwha Picture Tubes, Ltd.
    Inventors: Chih-Yu Chao, Wen-Jiunn Hsieh, Wen-Tse Tseng, Mine-Wei Tsai
  • Patent number: 6995094
    Abstract: A method for etching a silicon on insulator (SOI) substrate includes opening a hardmask layer formed on an SOI layer, and etching through the SOI layer, a buried insulator layer underneath the SOI layer, and a bulk silicon layer beneath the buried insulator layer using a single etch step.
    Type: Grant
    Filed: October 13, 2003
    Date of Patent: February 7, 2006
    Assignee: International Business Machines Corporation
    Inventors: Herbert L. Ho, Mahender Kumar, Brian Messenger, Michael D. Steigerwalt
  • Patent number: 6974547
    Abstract: According to a flexible thin film capacitor of the present invention, an adhesive film is formed on a substrate composed of at least one selected from the group consisting of an organic polymer and a metal foil, and an inorganic high dielectric film and metal electrode films are formed thereon. A metal oxide adhesive film can be used as the adhesive film. The adhesive film is formed in contact with the inorganic high dielectric film and at least one of the metal electrode films.
    Type: Grant
    Filed: November 13, 2000
    Date of Patent: December 13, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Naoki Kohara, Taisuke Sawada, Masatoshi Kitagawa
  • Patent number: 6969568
    Abstract: A chromeless phase lithography mask (30) that does not require photoresist to manufacture has a quartz substrate (32) is etched by using a plasma (38) containing one of a nitrogen augmented hydro-fluorocarbon oxygen mixture and a nitrogen augmented fluorocarbon oxygen mixture. Various hydro-fluorocarbons or fluorocarbons may be used. The nitrogen addition results in etched openings in the quartz substrate that have substantially vertical sidewalls in a uniform manner across the substrate. Surface roughness is minimized and edges of the openings are well-defined with minimal rounding. The etch rate is rendered controllable by reducing bias power without degrading a desired vertical sidewall profile.
    Type: Grant
    Filed: January 28, 2004
    Date of Patent: November 29, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shahid Rauf, Peter L. G. Ventzek, Wei E. Wu
  • Patent number: 6942816
    Abstract: A method for substantially reducing photoresist wiggling while etching a layer on a substrate is provided. The substrate having thereon the layer disposed below a photoresist mask is introduced into the plasma processing chamber. An etchant source gas mixture is flowed into the plasma processing chamber, where the etchant source gas mixture comprises xenon and an active etchant, where a flow rate of the xenon is at least 35% of etchant source gas mixture. A plasma is struck from the etchant source gas mixture. The layer is etched with the plasma, where the flow rate of xenon reduces photoresist wiggling.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: September 13, 2005
    Assignee: Lam Research Corporation
    Inventors: Camelia Rusu, Mukund Srinivasan
  • Patent number: 6942812
    Abstract: In producing an etalon, a thickness of an etalon base plate is measured, and the etalon base plate is placed in a process chamber. Then, a gas having a chemical reactivity with respect to a material of the etalon base plate is introduced into the process chamber, and a surface of the etalon base plate is etched for only a predetermined time corresponding to a thickness of the etalon base plate, thereby obtaining the etalon having a desired thickness.
    Type: Grant
    Filed: October 28, 2002
    Date of Patent: September 13, 2005
    Assignee: Shimadzu Corporation
    Inventors: Ryo Tateno, Masaru Koeda, Satoshi Irikuchi
  • Patent number: 6933236
    Abstract: A method for forming a photoresist pattern with minimally reduced transformations through the use of ArF photolithography, including the steps of: forming an organic anti-reflective coating layer on a an etch-target layer already formed on a substrate; coating a photoresist for ArF on the organic anti-reflective coating layer; exposing the photoresist with ArF laser; forming a first photoresist pattern by developing the photoresist, wherein portions of the organic anti-reflective coating layer are revealed; etching the organic anti-reflective coating layer with the first photoresist pattern as an etch mask and forming a second photoresist pattern by attaching polymer to the first photoresist pattern, wherein the polymer is generated during etching the organic anti-reflection coating layer with an etchant including O2 plasma; and etching the etch-target layer by using the second photoresist pattern as an etch mask.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: August 23, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Sung-Kwon Lee, Sang-Ik Kim, Weon-Joon Suh
  • Patent number: 6926841
    Abstract: An improved stepped etalon comprises a transparent body having a stepped surface. The lands of the steps are separated by a non-abrupt or softened transition region. This reduces the diffraction of light caused by the step transitions, thereby reducing the dead spot behind the step transition portions where interference prevents accurate measurements of light transmission from being made. Methods for producing a smoothly stepped etalon and for smoothing the step transitions in an abruptly stepped etalon are also disclosed.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: August 9, 2005
    Assignee: Agere Systems Inc.
    Inventor: Stephen O'Brien
  • Patent number: 6920765
    Abstract: A method for reducing the density of sites on the surface of fused silica optics that are prone to the initiation of laser-induced damage, resulting in optics which have far fewer catastrophic defects, and are better capable of resisting optical deterioration upon exposure to a high-power laser beam.
    Type: Grant
    Filed: April 17, 2002
    Date of Patent: July 26, 2005
    Assignee: The Regents of the University of California
    Inventors: Joseph A. Menapace, John E. Peterson, Bernardino M. Penetrante, Philip E. Miller, Thomas G. Parham, Michael A. Nichols
  • Patent number: 6896821
    Abstract: A method of making an etched structure in the fabrication of a MEMS device involves depositing a bulk layer, typically of polysilicon, prone to surface roughness. At least one layer of photo-insensitive spin-on planarizing material, such as silicate-based spin-on glass, is formed on the bulk layer to reduce surface roughness. This is patterned with a photoresist layer. A deep etch is then performed through the photoresist layer into the bulk layer. This technique results in much more precise etch structures.
    Type: Grant
    Filed: August 23, 2002
    Date of Patent: May 24, 2005
    Assignee: DALSA Semiconductor Inc.
    Inventor: Luc Louellet
  • Patent number: 6852242
    Abstract: A substrate processing apparatus has a chamber with a substrate transport to transport a substrate onto a substrate support in the chamber, a gas supply to provide a gas in the chamber, a gas energizer to energize the gas, and a gas exhaust to exhaust the gas. A controller operates one or more of the substrate support, gas supply, gas energizer, and gas exhaust, to set etching process conditions in the chamber to etch a plurality of substrates, thereby depositing etchant residues on surfaces in the chamber. The controller also operates one or more of the substrate support, gas supply, gas energizer, and gas exhaust, to set cleaning process conditions in the chamber to clean the etchant residues. The cleaning process conditions comprise a volumetric flow ratio of O2 to CF4 of from about 1:1 to about 1:40.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: February 8, 2005
    Inventors: Zhi-Wen Sun, Anbei Jiang, Tuo-Chuan Huang
  • Patent number: 6849193
    Abstract: An oxide etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a corner that is prone to faceting during the oxide etch. The invention uses a heavy perfluorocarbon, for example, hexafluorobutadiene (C4F6) or hexafluorobenzene (C6F6). The fluorocarbon together with a substantial amount of a noble gas such as argon is excited into a high-density plasma in a reactor which inductively couples plasma source power into the chamber and RF biases the pedestal electrode supporting the wafer. A more strongly polymerizing fluorocarbon such as difluoromethane (CH2F2) is added in the over etch to protect the nitride corner. Oxygen or nitrogen may be added to counteract the polymerization. The same chemistry can be used in a magnetically enhanced reactive ion etcher (MERIE) or with a remote plasma source.
    Type: Grant
    Filed: May 13, 2002
    Date of Patent: February 1, 2005
    Inventors: Hoiman Hung, Joseph P Caulfield, Hongqing Shan, Ruiping Wang, Gerald Zheyao Yin
  • Patent number: 6838012
    Abstract: Methods of etching dielectric materials in a semiconductor processing apparatus use a thick silicon upper electrode that can be operated at high power levels for an extended service life.
    Type: Grant
    Filed: October 31, 2002
    Date of Patent: January 4, 2005
    Assignee: Lam Research Corporation
    Inventor: Eric H. Lenz
  • Patent number: 6821449
    Abstract: This invention relates to a method of preparing an optical fiber preform with the preform having a uniform refractive index profile for the deposited oxide material that ultimately forms the optical fiber core. One embodiment of the invention relates to a process for preparing an optical fiber preform comprising the steps of etching a substrate a first time to remove a portion of a deposited oxide material from the preform by using a gas comprising an etchant gas containing fluorine at a sufficient temperature and gas concentration to create a fluorine contamination layer in the remaining deposited oxide material; and etching the preform a second time using a gas comprising an etchant gas containing fluorine at a sufficient temperature and gas concentration to remove the fluorine contamination layer without any substantial further fluorine contamination of the remaining deposited oxide material. Further embodiments relate to similar processes.
    Type: Grant
    Filed: December 12, 2002
    Date of Patent: November 23, 2004
    Assignee: Corning Incorporated
    Inventors: Julie E. Caplen, Jean-Philippe J. deSandro, Joohyun Koh
  • Patent number: 6808606
    Abstract: This invention relates to a method of making a window (e.g., vehicle windshield, architectural window, etc.), and the resulting window product. At least one glass substrate of the window is ion beam treated and/or milled prior to application of a coating (e.g., sputter coated coating) over the treated/milled substrate surface and/or prior to heat treatment. As a result, defects in the resulting window and/or haze may be reduced. The ion beam used in certain embodiments may be diffused. In certain embodiments, the ion beam treating and/or milling is carried out using a fluorine (F) inclusive gas(es) and/or argon/oxygen gas(es) at the ion source(s). In certain optional embodiments, F may be subimplanted into to treated/milled glass surface for the purpose of reducing Na migration to the glass surface during heat treatment or thereafter, thereby enabling corrosion and/or stains to be reduced for long periods of time.
    Type: Grant
    Filed: September 10, 2002
    Date of Patent: October 26, 2004
    Assignee: Guardian Industries Corp.
    Inventors: Scott V. Thomsen, Rudolph Hugo Petrmichl, Vijayen S. Veerasamy, Anthony V. Longobardo, Henry A. Luten, David R. Hall, Jr.
  • Patent number: 6808920
    Abstract: A microchip device for chemotaxis observation according to the present invention is provided with the first well in which chemotactic factors are to be filled, and the second well in which chemotactic cells are to be filled. There is provided a channel between the first well and the second well. The channel has a plurality of paths. A sidewall surfaces of the path is substantially perpendicular to a bottom surface, as formed by anisotropic dry etching.
    Type: Grant
    Filed: January 28, 2003
    Date of Patent: October 26, 2004
    Assignee: Yamatake Corporation
    Inventors: Yasuhiro Goshoo, Takaaki Kuroiwa
  • Patent number: 6802944
    Abstract: A method of depositing a film on a substrate. In one embodiment, the method includes depositing a first portion of the film using a high density plasma to partially fill a gap formed between adjacent features formed on the substrate. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a two step etching process that includes a first physical etch step that forms a plasma from a sputtering agent introduced into the processing chamber and biases the plasma towards the substrate and a subsequent chemical etch step that forms a plasma from a reactive etchant gas introduced into the processing chamber. After the etching sequence is complete, a second portion of the film is deposited over the first portion using a high density plasma to further fill the gap.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: October 12, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Farhan Ahmad, Michael Awdshiew, Alok Jain, Bikram Kapoor
  • Patent number: 6797187
    Abstract: Microfluidic devices are disclosed which can be manufactured using surface-micromachining. These devices utilize an electroosmotic force or an electromagnetic field to generate a flow of a fluid in a microchannel that is lined, at least in part, with silicon nitride. Additional electrodes can be provided within or about the microchannel for separating particular constituents in the fluid during the flow based on charge state or magnetic moment. The fluid can also be pressurized in the channel. The present invention has many different applications including electrokinetic pumping, chemical and biochemical analysis (e.g. based on electrophoresis or chromatography), conducting chemical reactions on a microscopic scale, and forming hydraulic actuators.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: September 28, 2004
    Assignee: Sandia Corporation
    Inventors: Paul C. Galambos, Murat Okandan, Stephen Montague, James H. Smith, Phillip H. Paul, Thomas W. Krygowski, James J. Allen, Christopher A. Nichols, Jerome F. Jakubczak, II
  • Patent number: 6783920
    Abstract: The direct-write pulsed UV laser technique combined with the variable laser exposure fabrication method entails the precise variation of the laser irradiance during pattern formation in the photostructurable glass for variable laser exposing processing. The variable laser exposure patterning utilizes the dependence of the chemical etching rate on the controlled laser exposure dose for forming variable laser irradiated and crystallized regions of the exposed glass, that have variable etch rates that are dependent on the laser irradiance, resulting in the formation of high and low aspect ratio features in a common substrate that are realized during a single, maskless etch step.
    Type: Grant
    Filed: January 15, 2003
    Date of Patent: August 31, 2004
    Assignee: The Aerospace Corporation
    Inventors: Frank E. Livingston, Henry Helvajian
  • Patent number: 6780336
    Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.
    Type: Grant
    Filed: November 2, 2001
    Date of Patent: August 24, 2004
    Inventors: James E. Moon, Timothy J. Davis, Gregory J. Galvin, Kevin A. Shaw, Paul C. Waldrop, Sharlene A. Wilson
  • Publication number: 20040129676
    Abstract: A method for producing an apparatus for transferring small amounts of liquids includes bonding a plurality of parallel fibers having plural coaxial layers into a bundle, slicing the bundle of parallel fibers in planes perpendicular to the direction of the fibers to form two opposite, planar surfaces, and selectively etching the fiber layers to create etched wells in the fibers at one of the planar surfaces. The etched wells are in fluid communication with corresponding capillary nozzles of the fibers that extend to an opposite one of the planar surfaces. Various apparatus configurations of the present invention include liquid transfer devices manufactured utilizing one or more of the various method configurations of the present invention. By way of example only, a bundle of three-layer optical fibers or a bundle of hollow two-layer optical fibers may be utilized to produce a liquid transfer device.
    Type: Application
    Filed: January 7, 2003
    Publication date: July 8, 2004
    Inventor: Roy H. Tan
  • Patent number: 6749763
    Abstract: A semiconductor substrate, on which a silicon dioxide film with a resist film defined thereon has been formed, is placed inside a reaction chamber of a plasma processing system. Then, a fluorocarbon gas with a C/F ratio of 0.5 or more is introduced into the reaction chamber. In this process step, the flow rate of the gas is controlled such that the residence time &tgr; of the gas in the reaction chamber becomes greater than 0.1 sec and equal to or less than 1 sec in accordance with an equation &tgr;=P×V/Q, where &tgr; is the residence time (unit: sec), P is a pressure (unit: Pa) of the gas, V is a volume (unit: L) of the reaction chamber and Q is the flow rate (unit: Pa·L/sec) of the gas. Thereafter, plasma is created from the fluorocarbon gas and the silicon dioxide film is plasma-etched using the resist film as a mask.
    Type: Grant
    Filed: August 1, 2000
    Date of Patent: June 15, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Shinichi Imai
  • Patent number: 6746615
    Abstract: An in-process microelectronics device is treated by applying a heated liquid to the surface of the in-process microelectronics device, removing a portion of the liquid from the surface of the in-process microelectronics device and applying anhydrous HF gas to the surface of the in-process microelectronics device.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: June 8, 2004
    Assignee: FSI International, Inc.
    Inventor: Christina Ann Ellis
  • Publication number: 20040079632
    Abstract: A method of depositing a film on a substrate disposed in a substrate processing chamber. In one embodiment the method includes depositing a first portion of the film to at partially fill a gap formed between to adjacent features formed on the substrate. The first portion of film is deposited using a high density plasma formed from a first gaseous mixture flown into the process chamber. The film deposition process is then stopped before or shortly after the entry of the gap pinches off and the film is etched to widen entry to the gap using a two step etching process that includes a first physical etch step and a subsequent chemical etch step. The physical etch step sputter etches the first portion of film by forming a plasma from a sputtering agent introduced into the processing chamber and biasing the plasma towards the substrate. After the physical etching step, the film is chemically etched by forming a plasma from a reactive etchant gas introduced into the processing chamber.
    Type: Application
    Filed: October 23, 2002
    Publication date: April 29, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Farhan Ahmad, Michael Awdshiew, Alok Jain, Bikram Kapoor
  • Patent number: 6719914
    Abstract: The present invention relates to a method of manufacturing a piezoelectric device of high sensitivity using direct bonded quartz plate. To achieve this object, the invented method comprises the steps of covalently bonding a plurality of quartz plates, dry etching the bonded quartz plates with plasma from one side of its surfaces down to a bonded plane, and dry etching with plasma thereafter from the other side of the surfaces.
    Type: Grant
    Filed: April 26, 2002
    Date of Patent: April 13, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaya Nakatani, Michihiko Hayashi, Hirofumi Tajika
  • Patent number: 6686293
    Abstract: Disclosed herein is a method of etching a trench in a silicon-containing dielectric material, in the absence of a trench etch-stop layer, where the silicon-containing dielectric material has a dielectric constant of about 4 or less. The method comprises exposing the dielectric material to a plasma generated from a source gas comprising a fluorine-containing etchant gas and an additive gas selected from the group consisting of carbon monoxide (CO), argon, and combinations thereof. A volumetric flow ratio of the additive gas to the fluorine-containing etchant gas is within the range of about 1.25:1 to about 20:1 (more typically, about 2.5:1 to about 20:1), depending on the particular fluorine-containing etchant gas used. The method provides good control over critical dimensions and etch profile during trench etching. Also disclosed herein is a method of forming a dual damascene structure, without the need for an intermediate etch stop layer.
    Type: Grant
    Filed: May 10, 2002
    Date of Patent: February 3, 2004
    Assignee: Applied Materials, Inc
    Inventors: Yunsang Kim, Kenny L. Doan, Claes H. Björkman, Hongqing Shan
  • Patent number: 6679995
    Abstract: A method of micromechanically manufacturing fixed and movable layer-like electrodes of a semiconductor element, for example, a capacitive acceleration sensor, which are exposed over a substrate over a certain area is provided. A sacrificial layer may be arranged between the substrate and the fixed and movable electrodes being removed in an etching step in order to expose the electrodes with respect to the substrate. The thickness of the sacrificial layer located in the area of the fixed electrodes may be less than the thickness of the sacrificial layer located in the area of the movable electrodes.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: January 20, 2004
    Assignee: Robert Bosch GmbH
    Inventors: Branko Banjac, Frank Fischer, Doris Schielein, Dirk Bueche
  • Patent number: 6660177
    Abstract: Reactive atom plasma processing can be used to shape, polish, planarize, and clean surfaces of difficult materials with minimal subsurface damage. The apparatus and methods use a plasma torch, such as a conventional ICP torch. The workpiece and plasma torch are moved with respect to each other, whether by translating and/or rotating the workpiece, the plasma, or both. The plasma discharge from the torch can be used to shape, planarize, polish, clean and/or deposit material on the surface of the workpiece, as well as to thin the workpiece. The processing may cause minimal or no damage to the workpiece underneath the surface, and may involve removing material from, and/or redistributing material on, the surface of the workpiece.
    Type: Grant
    Filed: November 7, 2001
    Date of Patent: December 9, 2003
    Assignee: Rapt Industries Inc.
    Inventor: Jeffrey W. Carr
  • Publication number: 20030205556
    Abstract: A process to form a capillary that is well insulated from its environment is described. Said process has two stages. The first stage, which is the same for both of the invention's two embodiments, comprises forming a micro-channel in the surface of a sheet of glassy material. For the first embodiment, this sheet is bonded to a layer of oxide, that lies on the surface of a sheet of silicon, thereby sealing in the capillary. After all silicon has been selectively removed, a thin membrane of oxide remains. Using a low temperature bonding process, a second sheet of glassy material is then bonded to this membrane. In the second embodiment, the silicon is not fully removed. Instead, the oxide layer of the first embodiment is replaced by an oxide/nitride/oxide trilayer which provides improved electrical insulation between the capillary and the remaining silicon at a lower level of inter-layer stress.
    Type: Application
    Filed: May 2, 2002
    Publication date: November 6, 2003
    Applicant: Institute of Microelectronics
    Inventors: Yu Chen, Janak Singh
  • Patent number: 6623652
    Abstract: A method of altering the topography of a trailing edge or ABS of a slider is disclosed, the slider having a substrate surface, at least one magnetic recording head on top of the alumina, and an overcoat of a material, preferably SiO2. The steps include first applying an SiO2 overcoat at the wafer level followed by slicing the wafer into rows, then lapping the rows. The rows are then placed on a bias electrode, exposing the trailing edge to a plasma generated from a controlled source in a reactive ion etching process. The plasma is generated using an chemical etchant such as CHF3 and other F-containing compounds, the plasma being generated with a combination of an inert gas such as Argon and the chemical etchant. In the plasma, the electrode is charged to accelerate the plasma ions towards the exposed surface. Reacted material is drawn from the surface of the slider. The SiO2 trailing edge reacts preferentially with the plasma, thus effectuating a change in the trailing edge topography.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: September 23, 2003
    Assignee: International Business Machines Corporation
    Inventors: Richard Hsiao, Cherngye Hwang, Hugo Alberto Emilio Santini
  • Patent number: 6620333
    Abstract: A optic is produced for operation at the fundamental Nd:YAG laser wavelength of 1.06 micrometers through the tripled Nd:YAG laser wavelength of 355 nanometers by the method of reducing or eliminating the growth of laser damage sites in the optics by processing the optics to stop damage in the optics from growing to a predetermined critical size. A system is provided of mitigating the growth of laser-induced damage in optics by virtue of very localized removal of glass and absorbing material.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: September 16, 2003
    Assignee: The Regents of the University of California
    Inventors: Raymond M. Brusasco, Bernardino M. Penetrante, James A. Butler, Walter Grundler, George K. Governo
  • Patent number: 6607675
    Abstract: We have discovered a method for plasma etching a carbon-containing silicon oxide film which provides excellent etch profile control, a rapid etch rate of the carbon-containing silicon oxide film, and high selectivity for etching the carbon-containing silicon oxide film preferentially to an overlying photoresist masking material. When the method of the invention is used, a higher carbon content in the carbon-containing silicon oxide film results in a faster etch rate, at least up to a carbon content of 20 atomic percent. In particular, the carbon-containing silicon oxide film is plasma etched using a plasma generated from a source gas comprising NH3 and CxFy. It is necessary to achieve the proper balance between the relative amounts of NH3 and CxFy in the plasma source gas in order to provide a balance between etch by-product polymer deposition and removal on various surfaces of the substrate being etched.
    Type: Grant
    Filed: August 29, 2000
    Date of Patent: August 19, 2003
    Assignee: Applied Materials Inc.
    Inventors: Chang Lin Hsieh, Hui Chen, Jie Yuan, Yan Ye
  • Patent number: 6602435
    Abstract: A processing gas constituted of C5F8, O2 and Ar achieving a flow rate ratio of 1≦C5F8 flow rate/O2 flow rate≦1.625 is supplied into a processing chamber 102 of an etching apparatus 100 and the atmosphere pressure is set within a range of 45 mTorr˜50 mTorr. High-frequency power is applied to a lower electrode 110 sustained within a temperature range of 20° C.˜40° C. on which a wafer W is mounted to raise the processing gas to plasma, and using the plasma, a contact hole 210 is formed at an SiO2 film 208 on an SiNx film 206 formed at the wafer W. The use of C5F8 and O2 makes it possible to form a contact hole 210 achieving near-perfect verticality at the SiO2 film 208 and also improves the selection ratio of the SiO2 film 208 relative to the SiNx film 206. C5F8, which becomes decomposed over a short period of time when released into the atmosphere, does not induce the greenhouse effect.
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: August 5, 2003
    Assignee: Tokyo Electron Limited
    Inventors: Masahiro Yamada, Youbun Ito, Kouichiro Inazawa
  • Patent number: 6585906
    Abstract: A method for recycling a disk having a layered structure on a glass substrate is disclosed. Initially, the disk is exposed to gaseous sulphur dioxide in a humid environment. Then, the disk is treated with hot water to remove the layered structure from the glass substrate.
    Type: Grant
    Filed: November 26, 2001
    Date of Patent: July 1, 2003
    Assignee: International Business Machines Corporation
    Inventors: Dirk Hammel, Holger Roehl, Theo Schmitz, Johannes Windeln
  • Publication number: 20030116277
    Abstract: A semiconductor etching apparatus and a method for etching semiconductor devices using the apparatus. The semiconductor etching apparatus includes a chamber for accommodating a wafer, a radical source for supplying a radical into the chamber, a beam source for supplying ion beams or plasma into the chamber, a wafer stage for supporting and holding the wafer accommodated by the chamber, and a neutralizer for neutralizing charge within the chamber ionized by the ion beams, plasma or the radical. The method of etching semiconductor devices includes the steps of forming a reaction layer on the surface of a semiconductor wafer through radical absorption, and etching the surface of the semiconductor wafer by desorbing the reaction layer formed on the surface of the semiconductor wafer.
    Type: Application
    Filed: February 12, 2003
    Publication date: June 26, 2003
    Inventors: Kyeong-Koo Chi, Seung-Pil Chung
  • Patent number: 6583065
    Abstract: A process of reducing critical dimension (CD) microloading in dense and isolated regions of etched features of silicon-containing material on a substrate uses a plasma of an etchant gas and an additive gas. In one version, the etchant gas comprises halogen species absent fluorine, and the additive gas comprises fluorine species and carbon species, or hydrogen species and carbon species.
    Type: Grant
    Filed: August 3, 1999
    Date of Patent: June 24, 2003
    Assignee: Applied Materials Inc.
    Inventors: Raney Williams, Jeffrey Chinn, Jitske Trevor, Thorsten B. Lill, Padmapani Nallan, Tamas Varga, Herve Mace
  • Patent number: RE38760
    Abstract: Oxides are etched with a halide-containing species and a low molecular weight organic molecule having a high vapor pressure at standard conditions, where etching is performed at preset wafer temperature in an enclosed chamber at a pressure such that all species present in the chamber, including water, are in the gas phase and condensation of species present on the etched surface is controlled. Thus all species involved remain in the gas phase even if trace water vapor appears in the process chamber. Preferably, etching is performed in a cluster dry tool apparatus.
    Type: Grant
    Filed: July 30, 1997
    Date of Patent: July 19, 2005
    Assignee: Penn State Research Foundation
    Inventors: Robert W. Grant, Jerzy Ruzyllo, Kevin Torek
  • Patent number: RE39273
    Abstract: A method for forming a patterned microelectronics layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable microelectronics layer. There is then formed upon the oxygen containing plasma etchable microelectronics layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while employing the patterned photoresists layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching a hard mask material from which is formed the hard mask layer.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: September 12, 2006
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Syun-Ming Jang, Ming-Hsin Huang
  • Patent number: RE39895
    Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.
    Type: Grant
    Filed: March 8, 2002
    Date of Patent: October 23, 2007
    Assignee: Renesas Technology Corp.
    Inventors: Takafumi Tokunaga, Sadayuki Okudaira, Tatsumi Mizutani, Kazutami Tago, Hideyuki Kazumi, Ken Yoshioka