Abstract: A method of removing a planarized insulating layer from over an alignment mark on a wafer. The invention allows steppers to see alignment marks without the difficulty of viewing the alignment marks through the insulating layer overlying the alignment marks. The method begins by chemical mechanical polishing a conformal oxide layer over a substrate. Next, a first photoresist layer is formed over the conformal oxide layer. Then vias are etched in the conformal oxide layer in the device area and etch the conformal oxide layer in the alignment mark area. Subsequently, we form a second photoresist layer over the first photoresist layer and the conformal oxide layer. The second photoresist layer filling the vias, but not the alignment mark resist opening. Then etch the second photoresist layer leaving sidewall spacers on the sidewall of the first photoresist layer in the alignment mark area and leaving photoresist plugs filling the vias.

Abstract: A laser ablation process is described for removing the polymeric buffer layer from glass optical fibers. The ablation takes place within a flow of substantially non-oxidizing gas. In preferred embodiments, the fiber cable is flushed with dry nitrogen and irradiated by a sequence of laser pulses 200-800 .mu.s in width. A currently preferred laser is a carbon-dioxide laser emitting in the infrared portion of the spectrum. The irradiating wavelength is preferably chosen to be 90% absorbed at a depth of 0.5 to 1.0 times the thickness of the buffer layer. The polymeric buffer layer can be removed without previously treating the optical fiber with a chemical softening agent, and without causing any significant reduction in the tensile strength of the fiber.

Abstract: In a method for manufacturing a diffraction type optical element having an arbitrary cross-section, a laser beam of a single mode is divided into two and then is again focused on a thin film on a substrate, thereby obtaining a laser beam pattern changing periodically in intensity through interference thereof which is then irradiated onto the substrate while the substrate is positioned inclined with respect to a plane which is perpendicular to an average light beam axis of the two laser beams.

Abstract: An optical micro-machining method of glass characterized in that after light is applied to glass including SiO.sub.2 and 30-70 mol % GeO.sub.2, the irradiated area is removed by etching.

Abstract: This invention relates to a method of making fiber optic interferometers. First, a plurality of optical fibers are bundled and placed into a sleeve. The bundle is then encased in the sleeve and the fiber ends are cut and polished. An area of cladding is stripped back from the polished fiber ends and layers of material are deposited on the fiber ends. These layers of material have varying indexes of refraction and form a grating. The bundle of optical fibers is then removed from encasing in the sleeve.

Abstract: Planar waveguides are produced by using radiation to write path regions into a photosensitive layer. Originally, the photosensitive layer had the same refractive index as the confining regions, e.g., it consists of silica doped with oxides of Ge and B. Composite path regions are produced by depositing a glass soot onto a partial region. On sintering the soot melts to fill up the empty spaces and thereby create a composite layer.

Abstract: A method (202) for etching photolithographically produced quartz crystal blanks for singulation. In a first step (202), a quartz wafer is plated on both sides with metal and subsequently coated on both sides with photoresist. In a second step (204), the photoresist is patterned and developed and the metal layer on one side is etched through to form a narrow channel in the quartz defining a perimeter of a quartz blank. In a third step (206), the quartz channel is preferentially etched partially into the wafer along parallel atomic planes to provide a mechanically weak junction between the quartz wafer and the blanks to be singulated. In a fourth step (208), the photoresist layers are stripped from the quartz wafer. In a final step (210), the quartz blank is cleaved substantially along the bottom of the quartz channel to singulate the crystal blanks from the quartz wafer.

Abstract: The present invention provides a method of to planarize a spin-on-glass layer overlying a HDP-CVD oxide layer using a six etchback process. The process comprises: forming a spin-on-glass layer 40 over a plasma chemical vapor deposition (HDP-CVD)oxide layer 30 over spaced raised portions 20 on a semiconductor structure. The spin-on-glass and the density plasma chemical vapor deposition (HDP-CVD) oxide layer 30 are then planarized using a six etch back process comprising: Step 2, (Etch High), a CF4 gas flow of between about 88 and 108 sccm, CHF.sub.3 flow between about 35 and 45 sccm, an argon flow of between about 40 and 60 sccm, at a pressure of between about 210 and 310 mtorr, at a power of between 650 and 950 watts; Step 3 (Etch Low) a CF4 gas flow of between about 10 and 20 sccm, CHF.sub.

Abstract: Accelerometer and method in which parts such as the seismic mass and force sensors are all fabricated of a single material such as crystalline quartz and bonded together in a manner which reduces the possibility of creep between them. Damping plates and squeeze film gas damping dampen movement of the seismic mass, and the parts are oriented in a predetermined manner relative to the crystallographic axes of the wafers from which they are fabricated to control the character of breakaway tabs which hold the parts to the wafers during fabrication.

Abstract: In accordance with the invention, a continuously chirped fiber Bragg grating is made by fabricating a continuously chirped phase mask and using the mask to write a Bragg grating on a parallel fiber. The chirped phase mask is made by exposing a photoresist-coated mask substrate to two interfering beams: one a collimated beam and the other a beam reflected from a continuously curved mirror. After etching, the resulting phase mask can be used to write a chirped fiber grating having a continuously varying grating period without physical modification of the fiber. The resulting fiber grating has a widened bandwidth and uniform dispersive delay characteristics useful for dispersion compensation in critical telecommunications applications.

Abstract: Photoetchable glass is used to form spacer elements for large area field emission displays. Frit dots are placed onto a substrate. A sheet of photo etchable glass is exposed to UV light using a mask such that the UV light exposes the etchable areas and does not expose the areas which will form the spacers. The etchable glass is then heat treated to crystallize the UV exposed areas and to tailor the coefficient of thermal expansion. Next the glass is adhered to the frit coated substrate and the UV exposed areas etched away leaving spacers adhered to frit dots.

Abstract: A method of producing sealed cavity structures in the surface layer of a selectively etchable substrate (1), comprises: a) depositing a masking layer (2) of etchable material on the substrate (1), b) by means of etching, opening at least one hole (3) in the masking layer (2) down to the substrate surface, c) through said hole or holes (3) in the masking layer (2) selectively etching the substrate (1) in under the masking layer (2) so as to form one more cavities (4) which extend under the masking layer, and d) sealing said hole or holes (3) in the masking layer (2).

Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A shallow etch stop trench (46) is first ion milled around each ceramic island on the front side and then filled with an etch step material (e.g. parylene 48). An optical coat (e.g transparent metal layer 54, transparent organic layer 56 and conductive metallic layer 58) is elevated above the etch step material by an elevation layer (e.g. polyimide 49). For some applications, it has been experimentally verified that there is no loss, and sometimes a measured increase, in optical efficiency when the optical coating is not planar in topology. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 86) containing a massive array of sensing circuits.

Abstract: The process for the preparation of a waveguide buried in a glass substrate according to the invention consists of the following stages:a stage of producing a waveguide (28, 38) by ion exchange on the surface of each of two glass substrates (22, 32),a stage of aligning both substrates, so that the surfaces in which the waveguides have been produced face one another,a direct wafer bonding stage of the two substrates.

Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 40) which are fabricated from novel materials using unique methods of patterning. A front side optical coating (e.g. transparent metal layer 44, transparent organic layer 46 and conductive metallic layer 48) is elevated above the substrate between the ceramic islands. This allows additional material (e.g. polyimide 38) between the optical coating and the substrate above the regions where cavities are to be etched. Etching of the cavities (72) is performed from the back side of the substrate without damaging the front side optical coating. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 80) containing a massive array of sensing circuits.

Abstract: A method for etching (200) photolithographically produced quartz crystal blanks for singulation. First, a quartz wafer is plated on both sides with metal and subsequently coated on both sides with photoresist (202). Second, the photoresist is patterned and developed and the metal layers etched to define the periphery of a quartz blank with a narrow quartz channel exposed between the blank to be singulated and the parent quartz wafer (204). Third, the quartz channel is preferentially etched partially into the wafer along parallel atomic planes to provide a mechanically weak junction between the quartz wafer and the blank to be singulated, while the periphery around the remainder of the quartz blank is etched completely through the parent quartz wafer (206). Fourth, the photoresist layers are stripped from the quartz wafer (208). Finally, the quartz blank is cleaved substantially along the bottom of the quartz channel to singulate the crystal blank from the wafer (210).

Abstract: In a method of etch profile shaping through wafer temperature control during an etch process wherein deposition of a passivation film is temperature dependent, a gap between a semiconductor wafer to be etched and a cathode is pressurized at a first pressure, and the pressure in the gap is changed to a second pressure at a predetermined time during the etch process, thereby altering heat transfer from the semiconductor wafer to the cathode. The temperature of the wafer is adjusted one or more times during an etching process to control profile shaping of deep trenches, contact holes and shapes for mask opening shaping during the etch process.

Abstract: This is a system and method of etching pyroelectric devices post ion milling. The method may comprise: forming a mask 32 for thermal isolation trenches on a substrate 14; ion milling thermal isolation trenches 40 in the substrate 14; and etching undesired defects 44 caused by the ion milling by applying a dry etch, a solvent etch, or a liquid etch to the trenches. The etch may include: hydrofluoric acid, perchloric acid, a solution of a chlorine salt and water which is then exposed to ultraviolet light or any similar chemical solution giving the correct reducing properties. The mask 32 and ion milling may be applied from either the front side or the back side of the infrared detector.

Abstract: The invention is embodied in a method of operating a plasma etch reactor, consisting of introducing a gas into the reactor which disassociates as a plasma into an etch species which etches oxide films on a work piece in the reactor and a non-etching species combinable with the etch species into an etch-preventing polymer condensable onto the work piece below a characteristic deposition temperature, providing an interior wall comprising a material which scavenges the etching species, and maintaining a temperature of the interior wall above the deposition temperature.

Abstract: A novel reticulated array comprises islands of ceramic (e.g. BST 20) which are fabricated from novel materials using unique methods of patterning. Trenches (22) are formed in the ceramic substrate from the front side and filled with a filler material (e.g. parylene 24). An elevation layer (e.g. polyimide 26) is deposited above the filler material, and a front side optical coating (e.g. transparent metal layer 34, transparent organic layer 36 and conductive metallic layer 38 ) is elevated above the substrate between the ceramic islands. The elevation layer provides added protection to the optical coating during filler material removal. The substrate is thinned from the back side down through a portion of the trench filler material. Novel fabrication methods also provide for the convenient electrical and mechanical bonding of each of the massive number of ceramic islands to a signal processor substrate (e.g. Si 62) containing a massive array of sensing circuits.

Abstract: A method for forming contact vias in a integrated circuit which do not have planarizing material nearby. After a first insulating layer is deposited over the integrated circuit, a planarizing layer is deposited over the first insulating layer. The planarizing layer is etched back and portions of the planarizing layer may remain in the lower topographical regions of the first insulating layer to planarize the surface of the integrated circuit. A first masking layer is then formed over the surface of the integrated circuit. The openings created in the first masking layer have a size which is greater than the size of the contact vias to be formed. The first insulating layer is partially etched into so that portions of the planarizing layer near the locations of the contact vias are removed. The first masking layer is then removed, and a second insulating layer is deposited over the integrated circuit.

Abstract: A method for planarizing integrated circuit topographies, wherein, after a first layer of spin-on glass is deposited, a layer of low-temperature oxide is deposited before a second layer of spin-on glass.