Abstract: A flat display device, preferably of the PALC type, in which the plasma channels are formed by etching laterally-spaced slots in a spacer plate, attaching a thin dielectric sheet over the etched spacer plate, and bonding the etched spacer plate to a transparent substrate such that each channel is formed by the portion of the substrate between flanking walls formed by the etched slots in the spacer plate, adjacent flanking walls in the spacer plate, and the overlying portion of the thin dielectric sheet. In a modification, strengthening crossbars are formed between adjacent flanking walls.

Abstract: A method of forming an optical component is disclosed. The method includes obtaining an optical component precursor having a first medium positioned over a base and converting a portion of the first medium to a second medium. The method further includes removing a portion of the second medium so as to form a ridge in the second medium. The portion of the second medium is removed so as to expose a portion of the first medium.

Abstract: Method of fabricating microstructures on a substrate. The method comprises providing a substrate layer having a first surface with a resist layer. First selected regions of the resist layer are exposed to an environment that renders the resist layer more or less soluble in a developer solution. The resist layer is then developed in the developer solution to expose selected regions of the substrate surface. Second selected regions of the resist layer are then exposed to an environment that renders the resist layer more or less soluble in the developer solution by aligning exposure of the second selected regions to the first selected regions. The first selected regions of the substrate surface are etched. Second selected regions of the resist layer are then developed to expose the second selected regions of the substrate surface.

Abstract: The invention encompasses a method of enhancing selectivity of etching silicon dioxide relative to one or more organic substances. A material comprising one or more elements selected from Group VIII of the periodic table is provided within a reaction chamber; and a substrate is provided within the reaction chamber. The substrate has both a silicon-oxide-containing composition and at least one organic substance thereover. The silicon-oxide-containing composition is plasma etched within the reaction chamber. The plasma etching of the silicon-oxide-containing composition has increased selectivity for the silicon oxide of the composition relative to the at least one organic substance than would plasma etching conducted without the material in the chamber. The invention also encompasses a plasma reaction chamber assembly. The assembly comprises at least one interior wall, and at least one liner along the at least one interior wall. The liner comprises one or more of Ru, Fe, Co, Ni, Rh, Pd, Os, W, Ir, Pt and Ti.

Abstract: The subject of the present invention is to keep the wiring resistance low and reduce the variation of the wiring resistance in one identical lot in semiconductor devices of a multi level interconnect structure in which at least the lower wiring layer is an aluminum wiring layer. Contact holes (31, 51) are formed in dielectric interlayers (3, 5) of upper and lower wiring layers (1, 2, 4) by dry etching. In the method of forming the contact holes of the invention, the dry etching was applied in two steps divisionally. The first step of etching is applied with supplying CF4, CHF3, Ar and N2 into an etching chamber. The second step of etching is conducted with supplying CF4, CHF3 and Ar into the etching gas chamber.

Abstract: An improved CVD apparatus for depositing a uniform film is shown. The apparatus comprises a reaction chamber, a substrate holder and a plurality of light sources for photo CVD or a pair of electrodes for plasma CVD. The substrate holder is a cylindrical cart which is encircled by the light sources, and which is rotated around its axis by a driving device. With this configuration, the substrates mounted on the cart and the surroundings can be energized by light of plasma evenly throughout the surfaces to be coated.

Abstract: A method and a system for etching a substrate are disclosed. The substrate is disposed in a process chamber. A flow of precursor gas is introduced into the process chamber. An ionic plasma is then formed from the precursor gas in a plasma volume within the process chamber. A magnetic field is generated in the process chamber using magnetic sources disposed external to the plasma volume. The magnetic field divides the ionic plasma into a two regions, plasma within one region having a higher electron temperature than plasma within the other region. The low-electron temperature region is confined substantially above the substrate. Radicals are formed in this region for etching the substrate.

Abstract: A micro-fluidic device is disclosed with a gasket layer laminated between a silicon wafer patterned with channels and a glass wafer. The gasket layer is formed in two parts. A first portion of the gasket layer is formed on the inner walls of the channels and along the channel edges. A complimentary gasket is formed on the glass wafer. The silicon wafer and the glass wafer are anodically bonded together through their respective surface to enclosed channels or portions thereof. The fluidic properties of the micro-fluidic devices are altered depending on the gasket material that is used. In the preferred embodiments of the invention, the gasket material is selected from the group consisting of silicon carbide and silicon nitride.

Abstract: Disclosed is fluorocarbon-based dry etching gas which is free of global environmental problems and a dry etching method using a plasma gas obtained therefrom. The dry etching gas includes a fluorinated ether of carbon, fluorine, hydrogen and oxygen and having 2-6 carbon atoms.

Abstract: The present invention relates to a method of manufacturing a microstructure such as a barrier lib or a spacer formed at an internal space between two flat panels constructing a flat panel display and, in particular, to a method of manufacturing a microstructure using a photosensitive glass substrate. The method of manufacturing a microstructure in accordance with the present invention includes the steps of preparing a photosensitive glass substrate, forming a mask pattern having a light transmission unit and a shading unit on the photosensitive glass substrate, exposing the photosensitive glass substrate, heat-treating the photosensitive glass substrate, and etching an unexposed portion of the photosensitive glass substrate. In addition, the process of changing the thermal expansive coefficient of the microstructure by heat-treating the photosensitive substrate again can be additionally included after etching and removing the unexposed portion.

Abstract: A system of coupling optical energy in a waveguide mode, into a resonator that operates in a whispering gallery mode. A first part of the operation uses a fiber in its waveguide mode to couple information into a resonator e.g. a microsphere. The fiber is cleaved at an angle &PHgr; which causes total internal reflection within the fiber. The energy in the fiber then forms an evanescent field and a microsphere is placed in the area of the evanescent field. If the microsphere resonance is resonant with energy in the fiber, then the information in the fiber is effectively transferred to the microsphere.

Abstract: A plasma etching process, particularly useful for selectively etching oxide over a feature having a non-oxide composition, such as silicon nitride and especially when that feature has a comer that is prone to faceting during the oxide etch. A primary fluorine- containing gas, preferably hexafluorobutadiene (C4F6), is combined with a significantly larger amount of the diluent gas xenon (Xe) enhance nitride selectivity without the occurrence of etch stop. The chemistry is also useful for etching oxides in which holes and comers have already been formed, for which the use of xenon also reduces faceting of the oxide. For this use, the relative amount of xenon need not be so high. The invention may be used with related heavy fluorocarbons and other fluorine-based etching gases.

Abstract: In the method of fabricating an inductor, at least first and second conductive segments are formed in a semiconductor layer spaced apart in a first direction. A first dielectric layer is formed over a portion of the semiconductor layer along the first direction such that the first dielectric layer crosses the first and second conductive segments. A conductive core is formed on the first dielectric layer, and a second dielectric layer is formed over the semiconductor layer. First and second contact holes are formed in the second dielectric layer such that the first contact hole exposes a portion of the first conductive segment on a first side of the first dielectric layer and the second contact hole exposes a portion of the second conductive segment on a second side of the first dielectric layer.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: The invention relates to a method for etching of silica-based layers/substrates by reactive ion etching system (10) using an etching gas mixture of CHF3/AR through a photoresist mask. Reactive ion etching is carried out under conditions of simultaneous isotropic deposition of a carbon-based polymer where the polymer deposition rate is controlled by adjusting process control parameters of RF power, sample temperature, O2 and CF4 additions.

Abstract: When in a chamber, an upper electrode and a lower electrode (suscepter) are provided opposite to each other and with a to-be-treated substrate supported by the lower electrode, the high-frequency electric field is formed between the upper electrode and the lower electrode to generate plasma of the process gas while introducing the process gas into the chamber held to the reduced pressure, and an etching is provided to the to-be-treated substrate with this plasma, the high frequency in the range from 50 to 150 MHZ, for example, 60 MHz, is applied to the upper electrode, and the high frequency in the range from 1 to 4 MHz, for example, 2 MHz, is applied to the lower electrode.

Abstract: An etching gas is supplied into a process chamber and turned into plasma so as to etch a silicon nitride film arranged on a field silicon oxide film on a wafer (w). A mixture gas containing at least CH2F2 gas and O2 gas is used as the etching gas. Parameters for planar uniformity, by which the etching apparatus is set in light of a set value of the planar uniformity, include the process pressure and the mixture ratio (CH2F2/O2) of the mixture gas. As the set value of the planar uniformity is more strict, either one of the process pressure and the mixture ratio is set higher.

Abstract: A method for recycling a disk having a layered structure on a glass substrate is disclosed. Initially, the disk is exposed to gaseous sulphur dioxide in a humid environment. Then, the disk is treated with hot water to remove the layered structure from the glass substrate.

Abstract: When a via hole is formed in an insulating film formed by stacking a TEOS oxide film over an organic SOG film whose surface is modified as a low-K interlayer dielectric, by dry etching, a mixed gas of CHF3, CH2F2 and CO is used as an etching gas and a mixture ratio between CH2F2 and (CHF3+CH2F2) is set to 50% or more, whereby the dry etching for the formation of the via hole is performed.

Abstract: The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus in which a concentration of oxygen at flash striking is greater than a concentration during etching.

Abstract: A plasma process for etching oxide and having a high selectivity to silicon including flowing into a plasma reaction chamber a fluorine-containing etching gas and maintaining a temperature of an exposed silicon surface within said chamber at a temperature of between 200° C. and 300° C. An example of the etching gas includes SiF4 and a fluorocarbon gas. The plasma may be generated by a capacitive discharge type plasma generator or by an electromagnetically coupled plasma generator, such as an inductively coupled plasma generator. The high selectivity exhibited by the etch process permits use of an electromagnetically coupled plasma generator, which in turn permits the etch process to be performed at low pressures of between 1 and 30 milliTorr, resulting the etching of vertical sidewalls in the oxide layer.

Abstract: A method and apparatus is provided for locating with improved vertical positioning accuracy a discrete element on a semiconductor optoelectronic integrated circuit. The method employs an etch stop layer located beneath a series of semiconductor layers. The semiconductor layers may include waveguides to couple light between integrated or discrete elements. Pits with accurate depth are etched in the semiconductor layers down to the etch stop layer. Accurate alignment between a discrete element and another element is made possible by controlling their respective distances from the etch stop layer.

Abstract: An apparatus and method for scavenging etchant species from a plasma formed of etchant gas prior to the etchant gas entering a primary processing chamber of a plasma reactor. There is at least one scavenging chamber, each of which is connected at an inlet thereof to an etchant gas source and at an outlet thereof to a gas distribution device of the primary processing chamber. Each scavenging chamber has a radiation applicator that irradiates the interior of the scavenging chamber and creates a plasma therein from etchant gas flowing through the chamber from the etchant gas source to the gas distribution apparatus of the primary processing chamber. The applicator uses either an inductive discharge, capacitive discharge, direct current (DC) discharge or microwave discharge to irradiate the interior of the scavenging chamber and ignite the plasma. An etchant species scavenging source is also disposed within the scavenging chamber.

Abstract: An integrated in situ oxide etch process particularly useful for a counterbore dual-damascene structure over copper having in one inter-layer dielectric level a lower nitride stop layer, a lower oxide dielectric, a lower nitride stop layer, an upper oxide dielectric layer, and an anti-reflective coating (ARC). The process is divided into a counterbore etch and a trench etch with photolithography for each, and each step is preferably performed in a high-density plasma reactor having an inductively coupled plasma source primarily generating the plasma and a capacitively coupled pedestal supporting the wafer and producing the bias power. The counterbore etch preferably includes at least four substeps of opening the ARC, etching through the upper oxide and nitride layers, selectively etching the lower oxide layer but stopping on the lower nitride layer, and a post-etch treatment for removing residue.

Abstract: A plasma etch process, particularly applicable to an self-aligned contact etch in a high-density plasma for selectively etching oxide over nitride, although selectivity to silicon is also achieved. In the process, a fluoropropane or a fluoropropylene is a principal etching gas in the presence of a substantial amount of an inactive gas such as argon. Good nitride selectivity has been achieved with hexafluoropropylene (C3F6), octafluoropropane (C3F8), heptafluoropropane (C3HF7), hexafluoropropane (C3H2F6). The process may use one or more of the these gases in proportions to optimize selectivity and a wide process window. Difluoromethane (CH2F2) or other fluorocarbons may be combined with the above gases, particularly with C3F6 for optimum selectivity over other materials without the occurrence of etch stop in narrow contact holes and with a wide process window.

Abstract: For use with a sub-micron semiconductor process, a trench isolation process improves the etch profile of trenches among dense and isolated lines. In an example embodiment, a process forms a dielectric stack of silicon dioxide, silicon nitride and silicon oxynitride on a silicon substrate. Photolithography and etch define trench regions in the silicon substrate through the dielectric stack. Silicon oxynitride acts as a hard mask reducing differences in the sidewall slope among dense areas of the semiconductor device and the sparse areas of the semiconductor device.

Abstract: Compositely micro-textured thin film, magnetic disc media, with methods and apparatus for producing such, which are characterized by the incorporation of a first stage of micro-texturing provided by etching of a disc substrate, with a second, disparate, micro-texturing stage depositing rounded globules of eutectic alloy on the etched substrate.

Abstract: The invention pertains to dielectric films for the production of microelectronic devices. A relatively stabile fluorinated silicate glass film is produced by depositing a fluorinated silicate glass film onto a substrate and then exposing the fluorinated silicate glass film to electron beam radiation. The electron beam exposing step is conducted by overall exposing the dielectric layer with a wide, large beam of electron beam radiation from a large-area electron beam source.

Abstract: A damascene method of forming conductive lines in an integrated circuit chip. Trenches are etched by a plasma formed by capacitively coupling a gas mixture at 500 to 3000 watts under a pressure of 50-400 mTorr. The gas mixture includes 2-30 sccm of C4F8, 20-80 sccm of CO, 2-30 sccm of O2 and 50-400 sccm of Ar. Gas flow can be adjusted to an optimum level, thereby achieving a high degree of uniformity. Wafers falling below a selected uniformity may be reworked. A damascene wiring layer formed in the trenches with an acceptable flow exhibit a high degree of sheet resistance uniformity and improved line to line shorts yield.

Abstract: In one aspect, the invention includes a method of removing at least a portion of a material from a substrate, comprising: a) first etching the material in a reaction chamber; b) second etching the material in the reaction chamber; and c) cleaning a component of the material from at least one sidewall of the reaction chamber between the first etching and the second etching.

Abstract: An integrated in situ oxide etch process particularly useful for a counterbore dual-damascene structure over copper having in one inter-layer dielectric level a lower nitride stop layer, a lower oxide dielectric, a lower nitride stop layer, an upper oxide dielectric layer, and an anti-reflective coating (ARC). The process is divided into a counterbore etch and a trench etch with photolithography for each, and each step is preferably performed in a high-density plasma reactor having an inductively coupled plasma source primarily generating the plasma and a capacitively coupled pedestal supporting the wafer and producing the bias power. The counterbore etch preferably includes at least four substeps of opening the ARC, etching through the upper oxide and nitride layers, selectively etching the lower oxide layer but stopping on the lower nitride layer, and a post-etch treatment for removing residue.

Abstract: Disclosed are methods and systems for etching dielectric layers in a high density plasma etcher. A method includes providing a wafer having a photoresist mask over a dielectric layer in order to define at least one contact via hole or open area that is electrically interconnected down to the silicon substrate of the wafer. The method then proceeds to inserting the wafer into the high density plasma etcher and pulsed application a TCP power source of the high density plasma etcher. The pulsed application includes ascertaining a desired etch performance characteristic, which includes photoresist selectivity and etch rate which is associated with a continuous wave application of the TCP source. Then, selecting a duty cycle of the pulsed application of the TCP source and scaling a peak power of the pulsed application of the TCP source in order to match a cycle-averaged power that would be delivered by the continuous wave application of the TCP source.

Abstract: A plasma etch process, particularly applicable to a self-aligned contact etch or other advanced structures requiring high-selectivity to nitride or other non-oxide materials and producing no etch stop. The process is preferably performed in a high-density plasma reactor for etching holes with either high or low aspect rations. In this process, hexafluoropropylene (C3F6) is the principal etching gas and another hydrofluorocarbon such as CH2F2 or C3H2F6 is added at least in part for its polymer-forming ability, which increases selectivity of etching oxide to nitride. The process gas also includes a substantial amount of an inactive gas such as argon. The process gas mixture can be balanced between the active etching gas and the polymer former in proportions to optimize selectivity over other materials without the occurrence of etch stop in narrow contact holes and with a wide process window.

Abstract: A plasma is generated by feeding an antenna with radio-frequency electric power generated by a radio-frequency power source, and one end of the antenna is grounded to the earth through a capacitor of variable capacitance. A Faraday shield is electrically isolated from the earth, and the capacitance of the variable capacitor is determined to be such a value that the voltage at the two ends of the antenna may be equal in absolute values and inverted to reduce the partial removal of the wall after the plasma ignition. At the time of igniting the plasma, the capacitance of the capacitor is adjusted to a larger or smaller value than that minimizing the damage of the wall.

Abstract: There is provided a CVD apparatus and a cleaning method which can precisely perform cleaning at a high speed, in order to increase the throughput of a CVD apparatus. A film formation gas (e.g., SiH.sub.4 and O.sub.2 gases) is introduced from a source gas supply pipe into a chamber to form a silicon oxide film (SiO.sub.2) on a wafer placed on a susceptor by using a plasma or the like. A thin film (SiO.sub.2) mainly consisting of silicon and oxygen, an imperfect oxide film of silicon, or the like also attaches to a wall surface and the respective surfaces of a window plate, a vacuum seal portion, the susceptor, an electrode, an insulator, an exhaust pipe, and the like in the chamber. An HF-based gas supply system for a cleaning etching gas is arranged to clean the interior of the chamber of the CVD apparatus. Particularly, a film formed with a source gas of Si.sub.x H.sub.2x+2 (x=1, 2, 3) and O.sub.2 is more perfect than an imperfect oxide film (e.g.

Abstract: The present invention relates to a fabrication process relating to a fabrication process for manufacture of micro-electromechanical (MEM) devices such as cantilever supported beams. This fabrication process requires only two lithographic masking steps and offers moveable electromechanical devices with high electrical isolation. A preferred embodiment of the process uses electrically insulating glass substrate as the carrier substrate and single crystal silicon as the MEM component material. The process further includes deposition of an optional layer of insulating material such as silicon dioxide on top of a layer of doped silicon grown on a silicon substrate. The silicon dioxide is epoxy bonded to the glass substrate to create a silicon--silicon dioxide-epoxy-glass structure. The silicon is patterned using anisotropic plasma dry etching techniques.

Abstract: A semiconductor wafer (11) having a dielectric layer (12) is used as a calibration standard (10) to calibrate thickness measuring equipment in a wafer processing or manufacturing area. The thickness of the dielectric layer (12) is maintained to a desired thickness by heating the calibration standard (10) to remove contaminants from the dielectric layer (12).

Abstract: A method of fabricating a lens comprising providing a photosoluble substrate having opposed first and second surfaces; exposing one of the surfaces of the substrate to a photoactive etchant; and exposing said etchant to patterned light such that a convex or concave, generally semi-spherical bulge or recess is formed in said substrate.

Abstract: A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the formation of a cap layer and the formation of gaps into which high density plasma chemical vapor deposition (HDPCVD) dielectric material is deposited. First and second antireflective coatings may be formed on the wiring line layer, the first and second antireflective coatings being made from different materials. Both antireflective coatings and the wiring line layer are etched through to form wiring lines separated by gaps. The gaps between wiring lines may be filled using high density plasma chemical vapor deposition.

Abstract: Apparatus and method for direct delivery of enabling chemical gas from a liquid source and of HF gas in a hydrogen fluoride/enabling chemical based cleaning or etching process, such as a silicon dioxide film etching process. The liquid enabling chemical is temperature controlled to generate a vapor pressure which is sufficient to operate a mass flow controller at a desired processing pressure without a carrier gas. Prior to entering the process chamber, the enabling chemical gas is pre-mixed with HF and optionally, a carrier gas, all of which are supplied at flow rates independent of each other. By controlling the vapor pressure of the solvent in this way, solvent/HF/carrier mixtures which are not physically possible with carrier gas systems are attainable allowing access to a larger process space.

Abstract: A method of manufacturing a semiconductor device, including the steps of: cooling a semiconductor wafer to a predetermined temperature, the semiconductor wafer being mounted on a stage provided with cooling means and having a thin oxide film on a surface thereof; supplying energy to gas containing hydrogen and water vapor to excite the gas into a plasma state; adding nitrogen fluoride downstream into a flow of the gas in the plasma state; and introducing a flow of the gas, including the nitrogen fluoride, to the semiconductor wafer to etch the thin oxide film while maintaining the semiconductor wafer at the predetermined temperature.

Abstract: A process is described for producing a desired breaking point for breaking the glass wall of a glass body, in particular a break-open ampule or a tube, or for separating parts out of a pane of glass by generating microcracks in the breaking zone, in which process the microcracks are generated in the interior of the glass wall or the pane of glass.

Abstract: A general method of the invention is to provide a polymer-hardening precursor piece (such as silicon, carbon, silicon carbide or silicon nitride, but preferably silicon) within the reactor chamber during an etch process with a fluoro-carbon or fluoro-hydrocarbon gas, and to heat the polymer-hardening precursor piece above the polymerization temperature sufficiently to achieve a desired increase in oxide-to-silicon etch selectivity. Generally, this polymer-hardening precursor or silicon piece may be an integral part of the reactor chamber walls and/or ceiling or a separate, expendable and quickly removable piece, and the heating/cooling apparatus may be of any suitable type including apparatus which conductively or remotely heats the silicon piece.

Abstract: A process involving vapor etching of nuclear tracks in dielectric materials for creating high aspect ratio (i.e., length much greater than diameter), isolated cylindrical holes in dielectric materials that have been exposed to high-energy atomic particles. The process includes cleaning the surface of the tracked material and exposing the cleaned surface to a vapor of a suitable etchant. Independent control of the temperatures of the vapor and the tracked materials provide the means to vary separately the etch rates for the latent track region and the non-tracked material. As a rule, the tracked regions etch at a greater rate than the non-tracked regions. In addition, the vapor-etched holes can be enlarged and smoothed by subsequent dipping in a liquid etchant.

Abstract: A method for etching of sub-quarter micron openings in insulative layers for contacts and vias is described. The method uses high resolution DUV photolithography. By using a thin layer of photoresist to pattern a hardmask, full advantage of the high resolution can be attained. The hardmask in turn, is sufficiently durable to withstand subsequent etching of the insulative layer. The methods taught by this invention are of particular value for the formation of contacts to semiconductive devices although they are also applied to forming via openings. DUV photoresists having thicknesses of less than 500 nm are used with a DUV stepper. The hardmask materials include Ti/TiN and amorphous silicon. Etching selectivities of these materials with respect to typical insulative materials used in integrated circuit manufacture are of the order of 50:1.

Abstract: In order to study an etching rate difference of a layer formed mainly with silicon dioxide on a wafer, a thermal oxide film (113) and layers of BSG (117), BPSG (125), and PSG (129) are laminated on a wafer and are etched in a gaseous etching atmosphere consisting essentially of hydrogen fluoride or a mixture of hydrogen fluoride and water vapor. The layers are etched with various etching rates which are higher than that of the thermal oxide film. The etching rate difference is a difference between the etching rate of each layer and an etching rate of the thermal oxide film. The layers may include impurities, such as boron and phosphorus, collectively as a part of a layer material of each layer. The etching rate difference depends on the layer material. Preferably, the gaseous etching atmosphere should have a reduced pressure. Alternatively, a water vapor partial pressure should not be greater than 2000 Pa. As a further alternative, either the layer or the gaseous etching atmosphere should be heated.

Abstract: A catalytic method and an apparatus for selectively removing material from a solid substrate is provided. The method comprises contacting a surface of a solid substrate with a catalyst material in the presence of a reactant under conditions effective to selectively remove material from those areas of said solid substrate in contact with said catalyst material and said reactant.

Abstract: A method for forming a patterned layer within a microelectronics fabrication. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate an oxygen containing plasma etchable layer, where the oxygen containing plasma etchable layer is formed of a material which is also susceptible to etching within a fluorine containing plasma. There is then formed upon the oxygen containing plasma etchable layer a hard mask layer. There is then formed upon the hard mask layer a patterned photoresist layer. There is then etched through use of a first anisotropic plasma etch method the hard mask layer to form a patterned hard mask layer while simultaneously reaching the oxygen containing plasma etchable layer and while employing the patterned photoresist layer as a first etch mask layer. The first anisotropic plasma etch method employs an etchant gas composition appropriate for etching the hard mask material.

Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.